content
stringlengths 0
376M
|
|---|
//======================================================================
//
// adder.v
// -------
// Adder with separate carry in and carry out. Used in the montprod
// amd residue modules of the modexp core.
//
//
// Author: Peter Magnusson, Joachim Strömbergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module adder #(parameter OPW = 32)
(
input [(OPW - 1) : 0] a,
input [(OPW - 1) : 0] b,
input carry_in,
output wire [(OPW - 1) : 0] sum,
output wire carry_out
);
reg [(OPW) : 0] adder_result;
assign sum = adder_result[(OPW - 1) : 0];
assign carry_out = adder_result[(OPW)];
always @*
begin
adder_result = {1'b0, a} + {1'b0, b} + {{OPW{1'b0}}, carry_in};
end
endmodule // adder
//======================================================================
// EOF adder.v
//======================================================================
|
//======================================================================
//
// blockmem1rw1.v
// --------------
// Synchronous block memory with one read and one write port.
// The data size is the same for both read and write operations.
//
// The memory is used in the modexp core.
//
// paremeter OPW is operand word width in bits.
// parameter ADW is address width in bits.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module blockmem1r1w #(parameter OPW = 32, parameter ADW = 8)
(
input wire clk,
input wire [(ADW - 1) : 0] read_addr,
output wire [(OPW - 1) : 0] read_data,
input wire wr,
input wire [(ADW - 1) : 0] write_addr,
input wire [(OPW - 1) : 0] write_data
);
reg [(OPW - 1) : 0] mem [0 : ((2**ADW) - 1)];
reg [(OPW - 1) : 0] tmp_read_data;
assign read_data = tmp_read_data;
always @ (posedge clk)
begin : reg_mem
if (wr)
mem[write_addr] <= write_data;
tmp_read_data <= mem[read_addr];
end
endmodule // blockmem1r1w
//======================================================================
// EOF blockmem1r1w.v
//======================================================================
|
//======================================================================
//
// blockmem2r1w.v
// --------------
// Synchronous block memory with two read ports and one write port.
// The data size is the same for both read and write operations.
//
// The memory is used in the modexp core.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module blockmem2r1w #(parameter OPW = 32, parameter ADW = 8)
(
input wire clk,
input wire [(ADW - 1) : 0] read_addr0,
output wire [(OPW - 1) : 0] read_data0,
input wire [(ADW - 1) : 0] read_addr1,
output wire [(OPW - 1) : 0] read_data1,
input wire wr,
input wire [(ADW - 1) : 0] write_addr,
input wire [(OPW - 1) : 0] write_data
);
reg [(OPW - 1) : 0] mem [0 : ((2**ADW) - 1)];
reg [(OPW - 1) : 0] tmp_read_data0;
reg [(OPW - 1) : 0] tmp_read_data1;
assign read_data0 = tmp_read_data0;
assign read_data1 = tmp_read_data1;
always @ (posedge clk)
begin : reg_mem
if (wr)
mem[write_addr] <= write_data;
tmp_read_data0 <= mem[read_addr0];
tmp_read_data1 <= mem[read_addr1];
end
endmodule // blockmem2r1w
//======================================================================
// EOF blockmem2r1w.v
//======================================================================
|
//======================================================================
//
// blockmem2r1wptr.v
// -----------------
// Synchronous block memory with two read ports and one write port.
// For port 1 the address is implicit and instead given by the
// internal pointer. The pointer is automatically increased
// when the cs signal is set. The pointer is reset to zero when
// the rst signal is asserted.
//
//
// NOTE: This memory needs to be rebuilt if interface 0 is changed
// to use bigger operand widths and fewer words than interface 1.
// This adaption is NOT automatic.
//
//
// The memory is used in the modexp core.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module blockmem2r1wptr #(parameter OPW = 32, parameter ADW = 8)
(
input wire clk,
input wire reset_n,
input wire [(ADW - 1) : 0] read_addr0,
output wire [(OPW - 1) : 0] read_data0,
output wire [31 : 0] read_data1,
input wire rst,
input wire cs,
input wire wr,
input wire [31 : 0] write_data
);
//----------------------------------------------------------------
// Memories and regs including update variables and write enable.
//----------------------------------------------------------------
reg [(OPW - 1) : 0] mem [0 : ((2**ADW) - 1)];
reg [(OPW - 1) : 0] tmp_read_data0;
reg [31 : 0] tmp_read_data1;
reg [7 : 0] ptr_reg;
reg [7 : 0] ptr_new;
reg ptr_we;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data0 = tmp_read_data0;
assign read_data1 = tmp_read_data1;
//----------------------------------------------------------------
// mem_update
//
// Clocked update of memory This should cause
// the memory to be implemented as a block memory.
//----------------------------------------------------------------
always @ (posedge clk)
begin : mem_update
if (wr)
mem[ptr_reg] <= write_data;
tmp_read_data0 <= mem[read_addr0];
tmp_read_data1 <= mem[ptr_reg];
end
//----------------------------------------------------------------
// ptr_update
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : ptr_update
if (!reset_n)
ptr_reg <= 8'h00;
else
if (ptr_we)
ptr_reg <= ptr_new;
end
//----------------------------------------------------------------
// ptr_logic
//----------------------------------------------------------------
always @*
begin : ptr_logic
ptr_new = 8'h00;
ptr_we = 1'b0;
if (rst)
begin
ptr_new = 8'h00;
ptr_we = 1'b1;
end
if (cs)
begin
ptr_new = ptr_reg + 1'b1;
ptr_we = 1'b1;
end
end
endmodule // blockmem2r1wptr
//======================================================================
// EOF blockmem2r1wptr.v
//======================================================================
|
//======================================================================
//
// blockmem2r1wptr.v
// -----------------
// Synchronous block memory with two read ports and one write port.
// For port 1 the address is implicit and instead given by the
// internal pointer. But write address is explicitly given.
//
// The memory is used in the modexp core.
//
//
// NOTE: This memory needs to be rebuilt if interface 0 is changed
// to use bigger operand widths and fewer words than interface 1.
// This adaption is NOT automatic.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module blockmem2rptr1w #(parameter OPW = 32, parameter ADW = 8)
(
input wire clk,
input wire reset_n,
input wire [(ADW - 1) : 0] read_addr0,
output wire [(OPW - 1) : 0] read_data0,
output wire [31 : 0] read_data1,
input wire rst,
input wire cs,
input wire wr,
input wire [07 : 0] write_addr,
input wire [31 : 0] write_data
);
//----------------------------------------------------------------
// Memories and regs including update variables and write enable.
//----------------------------------------------------------------
reg [(OPW - 1) : 0] mem [0 : ((2**ADW) - 1)];
reg [(OPW - 1) : 0] tmp_read_data0;
reg [31 : 0] tmp_read_data1;
reg [7 : 0] ptr_reg;
reg [7 : 0] ptr_new;
reg ptr_we;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data0 = tmp_read_data0;
assign read_data1 = tmp_read_data1;
//----------------------------------------------------------------
// mem_update
//
// Clocked update of memory This should cause
// the memory to be implemented as a block memory.
//----------------------------------------------------------------
always @ (posedge clk)
begin : mem_update
if (wr)
mem[write_addr] <= write_data;
tmp_read_data0 <= mem[read_addr0];
tmp_read_data1 <= mem[ptr_reg];
end
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_mem_update
if (!reset_n)
ptr_reg <= 8'h00;
else
if (ptr_we)
ptr_reg <= ptr_new;
end
//----------------------------------------------------------------
// ptr_logic
//----------------------------------------------------------------
always @*
begin : ptr_logic
ptr_new = 8'h00;
ptr_we = 1'b0;
if (rst)
begin
ptr_new = 8'h00;
ptr_we = 1'b1;
end
if (cs)
begin
ptr_new = ptr_reg + 1'b1;
ptr_we = 1'b1;
end
end
endmodule // blockmem2r1wptr
//======================================================================
// EOF blockmem2r1wptr.v
//======================================================================
|
//======================================================================
//
// modexp.v
// --------
// Top level wrapper for the modula exponentiation core. The core
// is used to implement public key algorithms such as RSA,
// DH, ElGamal etc.
//
// The core calculates the following function:
//
// C = M ** e mod N
//
// M is a message with a length of n bits
// e is the exponent with a length of m bits
// N is the modulus with a length of n bits
//
// n can be 32 and up to and including 8192 bits in steps
// of 32 bits.
// m can be one and up to and including 8192 bits in steps
// of 32 bits.
//
// The core has a 32-bit memory like interface, but provides
// status signals to inform the system that a given operation
// has is done. Additionally, any errors will also be asserted.
//
//
// Author: Joachim Strombergson, Peter Magnusson
// Copyright (c) 2015, NORDUnet A/S
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//
//======================================================================
module modexp(
input wire clk,
input wire reset_n,
input wire cs,
input wire we,
input wire [ 7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
// The operand width is the internal operand width in bits.
// The address width is the size of the address space used. This
// value must be balances with OPERAND_WIDTH to allow a total
// of 8192 bits of data. OPERAND_WIDTH * (ADDRESS_WIDTH ** 2)
// is the formula. Note that the API data with is always 32 bits.
localparam OPERAND_WIDTH = 32;
localparam ADDRESS_WIDTH = 8;
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam ADDR_CYCLES_HIGH = 8'h10;
localparam ADDR_CYCLES_LOW = 8'h11;
localparam ADDR_MODULUS_LENGTH = 8'h20;
localparam ADDR_EXPONENT_LENGTH = 8'h21;
localparam ADDR_MODULUS_PTR_RST = 8'h30;
localparam ADDR_MODULUS_DATA = 8'h31;
localparam ADDR_EXPONENT_PTR_RST = 8'h40;
localparam ADDR_EXPONENT_DATA = 8'h41;
localparam ADDR_MESSAGE_PTR_RST = 8'h50;
localparam ADDR_MESSAGE_DATA = 8'h51;
localparam ADDR_RESULT_PTR_RST = 8'h60;
localparam ADDR_RESULT_DATA = 8'h61;
localparam DEFAULT_MODLENGTH = 8'h80; // 2048 bits.
localparam DEFAULT_EXPLENGTH = 8'h80;
localparam CORE_NAME0 = 32'h6d6f6465; // "mode"
localparam CORE_NAME1 = 32'h78702020; // "xp "
localparam CORE_VERSION = 32'h302e3532; // "0.52"
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [07 : 0] exponent_length_reg;
reg [07 : 0] exponent_length_new;
reg exponent_length_we;
reg [07 : 0] modulus_length_reg;
reg [07 : 0] modulus_length_new;
reg modulus_length_we;
reg start_reg;
reg start_new;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg exponent_mem_api_rst;
reg exponent_mem_api_cs;
reg exponent_mem_api_wr;
wire [31 : 0] exponent_mem_api_read_data;
reg modulus_mem_api_rst;
reg modulus_mem_api_cs;
reg modulus_mem_api_wr;
wire [31 : 0] modulus_mem_api_read_data;
reg message_mem_api_rst;
reg message_mem_api_cs;
reg message_mem_api_wr;
wire [31 : 0] message_mem_api_read_data;
reg result_mem_api_rst;
reg result_mem_api_cs;
wire [31 : 0] result_mem_api_read_data;
wire ready;
wire [63 : 0] cycles;
reg [31 : 0] tmp_read_data;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
//----------------------------------------------------------------
// core instantiations.
//----------------------------------------------------------------
modexp_core #(.OPW(OPERAND_WIDTH), .ADW(ADDRESS_WIDTH))
core_inst(
.clk(clk),
.reset_n(reset_n),
.start(start_reg),
.ready(ready),
.exponent_length(exponent_length_reg),
.modulus_length(modulus_length_reg),
.cycles(cycles),
.exponent_mem_api_cs(exponent_mem_api_cs),
.exponent_mem_api_wr(exponent_mem_api_wr),
.exponent_mem_api_rst(exponent_mem_api_rst),
.exponent_mem_api_write_data(write_data),
.exponent_mem_api_read_data(exponent_mem_api_read_data),
.modulus_mem_api_cs(modulus_mem_api_cs),
.modulus_mem_api_wr(modulus_mem_api_wr),
.modulus_mem_api_rst(modulus_mem_api_rst),
.modulus_mem_api_write_data(write_data),
.modulus_mem_api_read_data(modulus_mem_api_read_data),
.message_mem_api_cs(message_mem_api_cs),
.message_mem_api_wr(message_mem_api_wr),
.message_mem_api_rst(message_mem_api_rst),
.message_mem_api_write_data(write_data),
.message_mem_api_read_data(message_mem_api_read_data),
.result_mem_api_cs(result_mem_api_cs),
.result_mem_api_rst(result_mem_api_rst),
.result_mem_api_read_data(result_mem_api_read_data)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
start_reg <= 1'b0;
exponent_length_reg <= DEFAULT_EXPLENGTH;
modulus_length_reg <= DEFAULT_MODLENGTH;
end
else
begin
start_reg <= start_new;
if (exponent_length_we)
begin
exponent_length_reg <= write_data[7 : 0];
end
if (modulus_length_we)
begin
modulus_length_reg <= write_data[7 : 0];
end
end
end // reg_update
//----------------------------------------------------------------
// api
//
// The interface command decoding logic.
//----------------------------------------------------------------
always @*
begin : api
modulus_length_we = 1'b0;
exponent_length_we = 1'b0;
start_new = 1'b0;
modulus_mem_api_rst = 1'b0;
modulus_mem_api_cs = 1'b0;
modulus_mem_api_wr = 1'b0;
exponent_mem_api_rst = 1'b0;
exponent_mem_api_cs = 1'b0;
exponent_mem_api_wr = 1'b0;
message_mem_api_rst = 1'b0;
message_mem_api_cs = 1'b0;
message_mem_api_wr = 1'b0;
result_mem_api_rst = 1'b0;
result_mem_api_cs = 1'b0;
tmp_read_data = 32'h00000000;
if (cs)
begin
if (we)
begin
case (address)
ADDR_CTRL:
begin
start_new = write_data[0];
end
ADDR_MODULUS_LENGTH:
begin
modulus_length_we = 1'b1;
end
ADDR_EXPONENT_LENGTH:
begin
exponent_length_we = 1'b1;
end
ADDR_MODULUS_PTR_RST:
begin
modulus_mem_api_rst = 1'b1;
end
ADDR_MODULUS_DATA:
begin
modulus_mem_api_cs = 1'b1;
modulus_mem_api_wr = 1'b1;
end
ADDR_EXPONENT_PTR_RST:
begin
exponent_mem_api_rst = 1'b1;
end
ADDR_EXPONENT_DATA:
begin
exponent_mem_api_cs = 1'b1;
exponent_mem_api_wr = 1'b1;
end
ADDR_MESSAGE_PTR_RST:
begin
message_mem_api_rst = 1'b1;
end
ADDR_MESSAGE_DATA:
begin
message_mem_api_cs = 1'b1;
message_mem_api_wr = 1'b1;
end
ADDR_RESULT_PTR_RST:
begin
result_mem_api_rst = 1'b1;
end
default:
begin
end
endcase // case (address[7 : 0])
end // if (we)
else
begin
case (address)
ADDR_NAME0:
tmp_read_data = CORE_NAME0;
ADDR_NAME1:
tmp_read_data = CORE_NAME1;
ADDR_VERSION:
tmp_read_data = CORE_VERSION;
ADDR_CTRL:
tmp_read_data = {31'h00000000, start_reg};
ADDR_STATUS:
tmp_read_data = {31'h00000000, ready};
ADDR_CYCLES_HIGH:
tmp_read_data = cycles[63 : 32];
ADDR_CYCLES_LOW:
tmp_read_data = cycles[31 : 0];
ADDR_MODULUS_LENGTH:
tmp_read_data = {24'h000000, modulus_length_reg};
ADDR_EXPONENT_LENGTH:
tmp_read_data = {24'h000000, exponent_length_reg};
ADDR_MODULUS_DATA:
begin
modulus_mem_api_cs = 1'b1;
tmp_read_data = modulus_mem_api_read_data;
end
ADDR_EXPONENT_DATA:
begin
exponent_mem_api_cs = 1'b1;
tmp_read_data = exponent_mem_api_read_data;
end
ADDR_MESSAGE_DATA:
begin
message_mem_api_cs = 1'b1;
tmp_read_data = message_mem_api_read_data;
end
ADDR_RESULT_DATA:
begin
result_mem_api_cs = 1'b1;
tmp_read_data = result_mem_api_read_data;
end
default:
begin
end
endcase // case (address)
end // else: !if(we)
end // if (cs)
end // block: api
endmodule // modexp
//======================================================================
// EOF modexp.v
//======================================================================
|
//======================================================================
//
// modexp_core.v
// -------------
// Modular exponentiation core for implementing public key algorithms
// such as RSA, DH, ElGamal etc.
//
// The core calculates the following function:
//
// C = M ** e mod N
//
// M is a message with a length of n bits
// e is the exponent with a length of m bits
// N is the modulus with a length of n bits
//
// n can be 32 and up to and including 8192 bits in steps
// of 32 bits.
// m can be one and up to and including 8192 bits in steps
// of 32 bits.
//
// The core has access ports for the exponent, modulus, message and
// result memories.
//
//
// Author: Joachim Strombergson, Peter Magnusson
// Copyright (c) 2015, NORDUnet A/S
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//
//======================================================================
module modexp_core #(parameter OPW = 32, parameter ADW = 8)
(
input wire clk,
input wire reset_n,
input wire start,
output wire ready,
input wire [07 : 0] exponent_length,
input wire [07 : 0] modulus_length,
output wire [63 : 0] cycles,
input wire exponent_mem_api_cs,
input wire exponent_mem_api_wr,
input wire exponent_mem_api_rst,
input wire [31 : 0] exponent_mem_api_write_data,
output wire [31 : 0] exponent_mem_api_read_data,
input wire modulus_mem_api_cs,
input wire modulus_mem_api_wr,
input wire modulus_mem_api_rst,
input wire [31 : 0] modulus_mem_api_write_data,
output wire [31 : 0] modulus_mem_api_read_data,
input wire message_mem_api_cs,
input wire message_mem_api_wr,
input wire message_mem_api_rst,
input wire [31 : 0] message_mem_api_write_data,
output wire [31 : 0] message_mem_api_read_data,
input wire result_mem_api_cs,
input wire result_mem_api_rst,
output wire [31 : 0] result_mem_api_read_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam MONTPROD_SELECT_ONE_NR = 3'h0;
localparam MONTPROD_SELECT_X_NR = 3'h1;
localparam MONTPROD_SELECT_Z_P = 3'h2;
localparam MONTPROD_SELECT_P_P = 3'h3;
localparam MONTPROD_SELECT_Z_ONE = 3'h4;
localparam MONTPROD_DEST_Z = 2'b00;
localparam MONTPROD_DEST_P = 2'b01;
localparam MONTPROD_DEST_NOWHERE = 2'b10;
localparam CTRL_IDLE = 4'h0;
localparam CTRL_RESIDUE = 4'h1;
localparam CTRL_CALCULATE_Z0 = 4'h2;
localparam CTRL_CALCULATE_P0 = 4'h3;
localparam CTRL_ITERATE = 4'h4;
localparam CTRL_ITERATE_Z_P = 4'h5;
localparam CTRL_ITERATE_P_P = 4'h6;
localparam CTRL_ITERATE_END = 4'h7;
localparam CTRL_CALCULATE_ZN = 4'h8;
localparam CTRL_DONE = 4'h9;
//for rsa, c=M^65537 etc, there is no need to slow down to hide the exponent
localparam EXPONATION_MODE_SECRET_SECURE = 1'b0;
localparam EXPONATION_MODE_PUBLIC_FAST = 1'b1;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg ready_reg;
reg ready_new;
reg ready_we;
reg [2 : 0] montprod_select_reg;
reg [2 : 0] montprod_select_new;
reg montprod_select_we;
reg [1 : 0] montprod_dest_reg;
reg [1 : 0] montprod_dest_new;
reg montprod_dest_we;
reg [3 : 0] modexp_ctrl_reg;
reg [3 : 0] modexp_ctrl_new;
reg modexp_ctrl_we;
reg [31 : 0] one_reg;
reg [31 : 0] one_new;
reg [31 : 0] b_one_reg;
reg [31 : 0] b_one_new;
reg [12 : 0] loop_counter_reg;
reg [12 : 0] loop_counter_new;
reg loop_counter_we;
reg [07 : 0] E_word_index;
reg [04 : 0] E_bit_index;
reg last_iteration;
reg ei_reg;
reg ei_new;
reg ei_we;
reg exponation_mode_reg;
reg exponation_mode_new;
reg exponation_mode_we;
reg [31 : 0] cycle_ctr_low_reg;
reg [31 : 0] cycle_ctr_low_new;
reg cycle_ctr_low_we;
reg [31 : 0] cycle_ctr_high_reg;
reg [31 : 0] cycle_ctr_high_new;
reg cycle_ctr_high_we;
reg cycle_ctr_state_reg;
reg cycle_ctr_state_new;
reg cycle_ctr_state_we;
reg cycle_ctr_start;
reg cycle_ctr_stop;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [07 : 0] modulus_mem_int_rd_addr;
wire [31 : 0] modulus_mem_int_rd_data;
reg [07 : 0] message_mem_int_rd_addr;
wire [31 : 0] message_mem_int_rd_data;
reg [07 : 0] exponent_mem_int_rd_addr;
wire [31 : 0] exponent_mem_int_rd_data;
reg [07 : 0] result_mem_int_rd_addr;
wire [31 : 0] result_mem_int_rd_data;
reg [07 : 0] result_mem_int_wr_addr;
reg [31 : 0] result_mem_int_wr_data;
reg result_mem_int_we;
reg [07 : 0] p_mem_rd0_addr;
wire [31 : 0] p_mem_rd0_data;
reg [07 : 0] p_mem_rd1_addr;
wire [31 : 0] p_mem_rd1_data;
reg [07 : 0] p_mem_wr_addr;
reg [31 : 0] p_mem_wr_data;
reg p_mem_we;
reg [31 : 0] tmp_read_data;
reg montprod_calc;
wire montprod_ready;
reg [07 : 0] montprod_length;
wire [07 : 0] montprod_opa_addr;
reg [31 : 0] montprod_opa_data;
wire [07 : 0] montprod_opb_addr;
reg [31 : 0] montprod_opb_data;
wire [07 : 0] montprod_opm_addr;
reg [31 : 0] montprod_opm_data;
wire [07 : 0] montprod_result_addr;
wire [31 : 0] montprod_result_data;
wire montprod_result_we;
reg residue_calculate;
wire residue_ready;
reg [14 : 0] residue_nn;
reg [07 : 0] residue_length;
wire [07 : 0] residue_opa_rd_addr;
wire [31 : 0] residue_opa_rd_data;
wire [07 : 0] residue_opa_wr_addr;
wire [31 : 0] residue_opa_wr_data;
wire residue_opa_wr_we;
wire [07 : 0] residue_opm_addr;
reg [31 : 0] residue_opm_data;
reg [07 : 0] residue_mem_montprod_read_addr;
wire [31 : 0] residue_mem_montprod_read_data;
reg residue_valid_reg;
reg residue_valid_new;
reg residue_valid_int_validated;
wire [7 : 0] modulus_length_m1;
wire [7 : 0] exponent_length_m1;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign ready = ready_reg;
assign cycles = {cycle_ctr_high_reg, cycle_ctr_low_reg};
assign modulus_length_m1 = modulus_length - 8'h1;
assign exponent_length_m1 = exponent_length - 8'h1;
//----------------------------------------------------------------
// core instantiations.
//----------------------------------------------------------------
montprod #(.OPW(OPW), .ADW(ADW))
montprod_inst(
.clk(clk),
.reset_n(reset_n),
.calculate(montprod_calc),
.ready(montprod_ready),
.length(montprod_length),
.opa_addr(montprod_opa_addr),
.opa_data(montprod_opa_data),
.opb_addr(montprod_opb_addr),
.opb_data(montprod_opb_data),
.opm_addr(montprod_opm_addr),
.opm_data(montprod_opm_data),
.result_addr(montprod_result_addr),
.result_data(montprod_result_data),
.result_we(montprod_result_we)
);
residue #(.OPW(OPW), .ADW(ADW))
residue_inst(
.clk(clk),
.reset_n(reset_n),
.calculate(residue_calculate),
.ready(residue_ready),
.nn(residue_nn),
.length(residue_length),
.opa_rd_addr(residue_opa_rd_addr),
.opa_rd_data(residue_opa_rd_data),
.opa_wr_addr(residue_opa_wr_addr),
.opa_wr_data(residue_opa_wr_data),
.opa_wr_we(residue_opa_wr_we),
.opm_addr(residue_opm_addr),
.opm_data(residue_opm_data)
);
blockmem2r1w #(.OPW(OPW), .ADW(ADW))
residue_mem(
.clk(clk),
.read_addr0(residue_opa_rd_addr),
.read_data0(residue_opa_rd_data),
.read_addr1(residue_mem_montprod_read_addr),
.read_data1(residue_mem_montprod_read_data),
.wr(residue_opa_wr_we),
.write_addr(residue_opa_wr_addr),
.write_data(residue_opa_wr_data)
);
blockmem2r1w #(.OPW(OPW), .ADW(ADW))
p_mem(
.clk(clk),
.read_addr0(p_mem_rd0_addr),
.read_data0(p_mem_rd0_data),
.read_addr1(p_mem_rd1_addr),
.read_data1(p_mem_rd1_data),
.wr(p_mem_we),
.write_addr(p_mem_wr_addr),
.write_data(p_mem_wr_data)
);
blockmem2r1wptr #(.OPW(OPW), .ADW(ADW))
exponent_mem(
.clk(clk),
.reset_n(reset_n),
.read_addr0(exponent_mem_int_rd_addr),
.read_data0(exponent_mem_int_rd_data),
.read_data1(exponent_mem_api_read_data),
.rst(exponent_mem_api_rst),
.cs(exponent_mem_api_cs),
.wr(exponent_mem_api_wr),
.write_data(exponent_mem_api_write_data)
);
blockmem2r1wptr #(.OPW(OPW), .ADW(ADW))
modulus_mem(
.clk(clk),
.reset_n(reset_n),
.read_addr0(modulus_mem_int_rd_addr),
.read_data0(modulus_mem_int_rd_data),
.read_data1(modulus_mem_api_read_data),
.rst(modulus_mem_api_rst),
.cs(modulus_mem_api_cs),
.wr(modulus_mem_api_wr),
.write_data(modulus_mem_api_write_data)
);
blockmem2r1wptr #(.OPW(OPW), .ADW(ADW))
message_mem(
.clk(clk),
.reset_n(reset_n),
.read_addr0(message_mem_int_rd_addr),
.read_data0(message_mem_int_rd_data),
.read_data1(message_mem_api_read_data),
.rst(message_mem_api_rst),
.cs(message_mem_api_cs),
.wr(message_mem_api_wr),
.write_data(message_mem_api_write_data)
);
blockmem2rptr1w #(.OPW(OPW), .ADW(ADW))
result_mem(
.clk(clk),
.reset_n(reset_n),
.read_addr0(result_mem_int_rd_addr[7 : 0]),
.read_data0(result_mem_int_rd_data),
.read_data1(result_mem_api_read_data),
.rst(result_mem_api_rst),
.cs(result_mem_api_cs),
.wr(result_mem_int_we),
.write_addr(result_mem_int_wr_addr),
.write_data(result_mem_int_wr_data)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
ready_reg <= 1'b1;
montprod_select_reg <= MONTPROD_SELECT_ONE_NR;
montprod_dest_reg <= MONTPROD_DEST_NOWHERE;
modexp_ctrl_reg <= CTRL_IDLE;
one_reg <= 32'h0;
b_one_reg <= 32'h0;
loop_counter_reg <= 13'b0;
ei_reg <= 1'b0;
residue_valid_reg <= 1'b0;
exponation_mode_reg <= EXPONATION_MODE_SECRET_SECURE;
cycle_ctr_low_reg <= 32'h00000000;
cycle_ctr_high_reg <= 32'h00000000;
cycle_ctr_state_reg <= 1'b0;
end
else
begin
one_reg <= one_new;
b_one_reg <= b_one_new;
residue_valid_reg <= residue_valid_new;
if (ready_we)
ready_reg <= ready_new;
if (montprod_select_we)
montprod_select_reg <= montprod_select_new;
if (montprod_dest_we)
montprod_dest_reg <= montprod_dest_new;
if (loop_counter_we)
loop_counter_reg <= loop_counter_new;
if (ei_we)
ei_reg <= ei_new;
if (exponation_mode_we)
exponation_mode_reg <= exponation_mode_new;
if (cycle_ctr_low_we)
cycle_ctr_low_reg <= cycle_ctr_low_new;
if (cycle_ctr_high_we)
cycle_ctr_high_reg <= cycle_ctr_high_new;
if (cycle_ctr_state_we)
cycle_ctr_state_reg <= cycle_ctr_state_new;
if (modexp_ctrl_we)
modexp_ctrl_reg <= modexp_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// cycle_ctr
//
// Implementation of the cycle counter
//----------------------------------------------------------------
always @*
begin : cycle_ctr
cycle_ctr_low_new = 32'h00000000;
cycle_ctr_low_we = 1'b0;
cycle_ctr_high_new = 32'h00000000;
cycle_ctr_high_we = 1'b0;
cycle_ctr_state_new = 1'b0;
cycle_ctr_state_we = 1'b0;
if (cycle_ctr_start)
begin
cycle_ctr_low_new = 32'h00000000;
cycle_ctr_low_we = 1'b1;
cycle_ctr_high_new = 32'h00000000;
cycle_ctr_high_we = 1'b1;
cycle_ctr_state_new = 1'b1;
cycle_ctr_state_we = 1'b1;
end
if (cycle_ctr_stop)
begin
cycle_ctr_state_new = 1'b0;
cycle_ctr_state_we = 1'b1;
end
if (cycle_ctr_state_reg)
begin
cycle_ctr_low_new = cycle_ctr_low_reg + 1'b1;
cycle_ctr_low_we = 1'b1;
if (cycle_ctr_low_new == 32'h00000000)
begin
cycle_ctr_high_new = cycle_ctr_high_reg + 1'b1;
cycle_ctr_high_we = 1'b1;
end
end
end // cycle_ctr
//----------------------------------------------------------------
// one
//
// generates the big integer one ( 00... 01 )
//----------------------------------------------------------------
always @*
begin : one_process
one_new = 32'h00000000;
b_one_new = 32'h00000000;
if (montprod_opa_addr == modulus_length_m1)
one_new = 32'h00000001;
if (montprod_opb_addr == modulus_length_m1)
b_one_new = 32'h00000001;
end
//----------------------------------------------------------------
// Read mux for modulus. Needed since it is being
// addressed by two sources.
//----------------------------------------------------------------
always @*
begin : modulus_mem_reader_process
if (modexp_ctrl_reg == CTRL_RESIDUE)
modulus_mem_int_rd_addr = residue_opm_addr;
else
modulus_mem_int_rd_addr = montprod_opm_addr;
end
//----------------------------------------------------------------
// Feeds residue calculator.
//----------------------------------------------------------------
always @*
begin : residue_process
//N*2, N=length*32, *32 = shl5, *64 = shl6
residue_nn = { 1'b0, modulus_length, 6'h0 };
residue_length = modulus_length;
residue_opm_data = modulus_mem_int_rd_data;
end
//----------------------------------------------------------------
// Detects if modulus has been updated and we need to
// recalculate the residue
// and we need residue is valid or not.
//----------------------------------------------------------------
always @*
begin : residue_valid_process
residue_valid_new = residue_valid_reg;
if (modulus_mem_api_cs & modulus_mem_api_wr)
residue_valid_new = 1'b0;
else if ( residue_valid_int_validated == 1'b1)
residue_valid_new = 1'b1;
end
//----------------------------------------------------------------
// montprod_op_select
//
// Select operands used during montprod calculations depending
// on what operation we want to do.
//----------------------------------------------------------------
always @*
begin : montprod_op_select
montprod_length = modulus_length;
result_mem_int_rd_addr = montprod_opa_addr;
message_mem_int_rd_addr = montprod_opa_addr;
p_mem_rd0_addr = montprod_opa_addr;
residue_mem_montprod_read_addr = montprod_opb_addr;
p_mem_rd1_addr = montprod_opb_addr;
montprod_opm_data = modulus_mem_int_rd_data;
case (montprod_select_reg)
MONTPROD_SELECT_ONE_NR:
begin
montprod_opa_data = one_reg;
montprod_opb_data = residue_mem_montprod_read_data;
end
MONTPROD_SELECT_X_NR:
begin
montprod_opa_data = message_mem_int_rd_data;
montprod_opb_data = residue_mem_montprod_read_data;
end
MONTPROD_SELECT_Z_P:
begin
montprod_opa_data = result_mem_int_rd_data;
montprod_opb_data = p_mem_rd1_data;
end
MONTPROD_SELECT_P_P:
begin
montprod_opa_data = p_mem_rd0_data;
montprod_opb_data = p_mem_rd1_data;
end
MONTPROD_SELECT_Z_ONE:
begin
montprod_opa_data = result_mem_int_rd_data;
montprod_opb_data = b_one_reg;
end
default:
begin
montprod_opa_data = 32'h00000000;
montprod_opb_data = 32'h00000000;
end
endcase // case (montprod_selcect_reg)
end
//----------------------------------------------------------------
// memory write mux
//
// Direct memory write signals to correct memory.
//----------------------------------------------------------------
always @*
begin : memory_write_process
result_mem_int_wr_addr = montprod_result_addr;
result_mem_int_wr_data = montprod_result_data;
result_mem_int_we = 1'b0;
p_mem_wr_addr = montprod_result_addr;
p_mem_wr_data = montprod_result_data;
p_mem_we = 1'b0;
case (montprod_dest_reg)
MONTPROD_DEST_Z:
result_mem_int_we = montprod_result_we;
MONTPROD_DEST_P:
p_mem_we = montprod_result_we;
default:
begin
end
endcase
// inhibit Z=Z*P when ei = 0
if (modexp_ctrl_reg == CTRL_ITERATE_Z_P)
result_mem_int_we = result_mem_int_we & ei_reg;
end
//----------------------------------------------------------------
// loop_counter
//
// Calculate the loop counter and related variables.
//----------------------------------------------------------------
always @*
begin : loop_counters_process
loop_counter_new = 13'b0;
loop_counter_we = 1'b0;
if (loop_counter_reg == {exponent_length_m1, 5'b11111})
last_iteration = 1'b1;
else
last_iteration = 1'b0;
case (modexp_ctrl_reg)
CTRL_CALCULATE_P0:
begin
loop_counter_new = 13'b0;
loop_counter_we = 1'b1;
end
CTRL_ITERATE_END:
begin
loop_counter_new = loop_counter_reg + 1'b1;
loop_counter_we = 1'b1;
end
default:
begin
end
endcase
end
//----------------------------------------------------------------
// exponent
//
// Reads the exponent.
//----------------------------------------------------------------
always @*
begin : exponent_process
// Accessing new instead of reg - pick up update at
// CTRL_ITERATE_NEW to remove a pipeline stall.
E_word_index = exponent_length_m1 - loop_counter_new[ 12 : 5 ];
E_bit_index = loop_counter_reg[ 04 : 0 ];
exponent_mem_int_rd_addr = E_word_index;
ei_new = exponent_mem_int_rd_data[ E_bit_index ];
if (modexp_ctrl_reg == CTRL_ITERATE)
ei_we = 1'b1;
else
ei_we = 1'b0;
end
//----------------------------------------------------------------
// modexp_ctrl
//
// Control FSM logic needed to perform the modexp operation.
//----------------------------------------------------------------
always @*
begin
ready_new = 1'b0;
ready_we = 1'b0;
montprod_select_new = MONTPROD_SELECT_ONE_NR;
montprod_select_we = 0;
montprod_dest_new = MONTPROD_DEST_NOWHERE;
montprod_dest_we = 0;
montprod_calc = 0;
modexp_ctrl_new = CTRL_IDLE;
modexp_ctrl_we = 1'b0;
cycle_ctr_start = 1'b0;
cycle_ctr_stop = 1'b0;
residue_calculate = 1'b0;
residue_valid_int_validated = 1'b0;
case (modexp_ctrl_reg)
CTRL_IDLE:
begin
if (start)
begin
ready_new = 1'b0;
ready_we = 1'b1;
cycle_ctr_start = 1'b1;
if (residue_valid_reg)
begin
//residue has alrady been calculated, start with MONTPROD( 1, Nr, MODULUS )
montprod_select_new = MONTPROD_SELECT_ONE_NR;
montprod_select_we = 1;
montprod_dest_new = MONTPROD_DEST_Z;
montprod_dest_we = 1;
montprod_calc = 1;
modexp_ctrl_new = CTRL_CALCULATE_Z0;
modexp_ctrl_we = 1;
end
else
begin
//modulus has been written and residue (Nr) must be calculated
modexp_ctrl_new = CTRL_RESIDUE;
modexp_ctrl_we = 1;
residue_calculate = 1'b1;
end
end
end
CTRL_RESIDUE:
begin
if (residue_ready)
begin
montprod_select_new = MONTPROD_SELECT_ONE_NR;
montprod_select_we = 1;
montprod_dest_new = MONTPROD_DEST_Z;
montprod_dest_we = 1;
montprod_calc = 1;
modexp_ctrl_new = CTRL_CALCULATE_Z0;
modexp_ctrl_we = 1;
residue_valid_int_validated = 1'b1; //update registers telling residue is valid
end
end
CTRL_CALCULATE_Z0:
begin
if (montprod_ready)
begin
montprod_select_new = MONTPROD_SELECT_X_NR;
montprod_select_we = 1;
montprod_dest_new = MONTPROD_DEST_P;
montprod_dest_we = 1;
montprod_calc = 1;
modexp_ctrl_new = CTRL_CALCULATE_P0;
modexp_ctrl_we = 1;
end
end
CTRL_CALCULATE_P0:
begin
if (montprod_ready == 1'b1)
begin
modexp_ctrl_new = CTRL_ITERATE;
modexp_ctrl_we = 1;
end
end
CTRL_ITERATE:
begin
montprod_select_new = MONTPROD_SELECT_Z_P;
montprod_select_we = 1;
montprod_dest_new = MONTPROD_DEST_Z;
montprod_dest_we = 1;
montprod_calc = 1;
modexp_ctrl_new = CTRL_ITERATE_Z_P;
modexp_ctrl_we = 1;
if (ei_new == 1'b0 && exponation_mode_reg == EXPONATION_MODE_PUBLIC_FAST)
begin
//Skip the fake montgomery calculation, exponation_mode_reg optimizing for speed not blinding.
montprod_select_new = MONTPROD_SELECT_P_P;
montprod_dest_new = MONTPROD_DEST_P;
modexp_ctrl_new = CTRL_ITERATE_P_P;
end
end
CTRL_ITERATE_Z_P:
if (montprod_ready)
begin
montprod_select_new = MONTPROD_SELECT_P_P;
montprod_select_we = 1;
montprod_dest_new = MONTPROD_DEST_P;
montprod_dest_we = 1;
montprod_calc = 1;
modexp_ctrl_new = CTRL_ITERATE_P_P;
modexp_ctrl_we = 1;
end
CTRL_ITERATE_P_P:
if (montprod_ready == 1'b1)
begin
modexp_ctrl_new = CTRL_ITERATE_END;
modexp_ctrl_we = 1;
end
CTRL_ITERATE_END:
begin
if (!last_iteration)
begin
modexp_ctrl_new = CTRL_ITERATE;
modexp_ctrl_we = 1;
end
else
begin
montprod_select_new = MONTPROD_SELECT_Z_ONE;
montprod_select_we = 1;
montprod_dest_new = MONTPROD_DEST_Z;
montprod_dest_we = 1;
montprod_calc = 1;
modexp_ctrl_new = CTRL_CALCULATE_ZN;
modexp_ctrl_we = 1;
end
end
CTRL_CALCULATE_ZN:
begin
if (montprod_ready)
begin
modexp_ctrl_new = CTRL_DONE;
modexp_ctrl_we = 1;
end
end
CTRL_DONE:
begin
cycle_ctr_stop = 1'b1;
ready_new = 1'b1;
ready_we = 1'b1;
modexp_ctrl_new = CTRL_IDLE;
modexp_ctrl_we = 1;
end
default:
begin
end
endcase // case (modexp_ctrl_reg)
end
endmodule // modexp_core
//======================================================================
// EOF modexp_core.v
//======================================================================
|
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : modexp_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-RSA core
//
module modexp_top(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
wb_ack_o, wb_err_o, wb_dat_o,
wb_clk_i, wb_rst_i, int_o
);
parameter dw = 32;
parameter aw = 32;
input [aw-1:0] wb_adr_i; //Address
input wb_cyc_i; //bus cycle
input [dw-1:0] wb_dat_i; //Data IN
input [3:0] wb_sel_i; //Select Input Array
input wb_stb_i; //Chip Select
input wb_we_i; //Write Or Read Enabled
output wb_ack_o; //Acknowledge
output wb_err_o; //Error
output reg [dw-1:0] wb_dat_o; //Data OUT
output int_o; //Interrupt
input wb_clk_i; //Clk
input wb_rst_i; //Reset
assign wb_ack_o = 1'b1;
assign wb_err_o = 1'b0;
assign int_o = 1'b0;
wire reset_n=!wb_rst_i;
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
// The operand width is the internal operand width in bits.
// The address width is the size of the address space used. This
// value must be balances with OPERAND_WIDTH to allow a total
// of 8192 bits of data. OPERAND_WIDTH * (ADDRESS_WIDTH ** 2)
// is the formula. Note that the API data with is always 32 bits.
localparam OPERAND_WIDTH = 32;
localparam ADDRESS_WIDTH = 8;
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam ADDR_CYCLES_HIGH = 8'h10;
localparam ADDR_CYCLES_LOW = 8'h11;
localparam ADDR_MODULUS_LENGTH = 8'h20;
localparam ADDR_EXPONENT_LENGTH = 8'h21;
localparam ADDR_MODULUS_PTR_RST = 8'h30;
localparam ADDR_MODULUS_DATA = 8'h31;
localparam ADDR_EXPONENT_PTR_RST = 8'h40;
localparam ADDR_EXPONENT_DATA = 8'h41;
localparam ADDR_MESSAGE_PTR_RST = 8'h50;
localparam ADDR_MESSAGE_DATA = 8'h51;
localparam ADDR_RESULT_PTR_RST = 8'h60;
localparam ADDR_RESULT_DATA = 8'h61;
localparam DEFAULT_MODLENGTH = 8'h80; // 2048 bits.
localparam DEFAULT_EXPLENGTH = 8'h80;
localparam CORE_NAME0 = 32'h6d6f6465; // "mode"
localparam CORE_NAME1 = 32'h78702020; // "xp "
localparam CORE_VERSION = 32'h302e3532; // "0.52"
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [07 : 0] exponent_length_reg;
reg [07 : 0] exponent_length_new;
reg exponent_length_we;
reg [07 : 0] modulus_length_reg;
reg [07 : 0] modulus_length_new;
reg modulus_length_we;
reg start_reg;
reg start_new;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg exponent_mem_api_rst;
reg exponent_mem_api_cs;
reg exponent_mem_api_wr;
wire [31 : 0] exponent_mem_api_read_data;
reg modulus_mem_api_rst;
reg modulus_mem_api_cs;
reg modulus_mem_api_wr;
wire [31 : 0] modulus_mem_api_read_data;
reg message_mem_api_rst;
reg message_mem_api_cs;
reg message_mem_api_wr;
wire [31 : 0] message_mem_api_read_data;
reg result_mem_api_rst;
reg result_mem_api_cs;
wire [31 : 0] result_mem_api_read_data;
wire ready;
wire [63 : 0] cycles;
//reg [31 : 0] wb_dat_o;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
//assign wb_dat_o = wb_dat_o;
//----------------------------------------------------------------
// core instantiations.
//----------------------------------------------------------------
modexp_core #(.OPW(OPERAND_WIDTH), .ADW(ADDRESS_WIDTH))
core_inst(
.clk(wb_clk_i),
.reset_n(reset_n),
.start(start_reg),
.ready(ready),
.exponent_length(exponent_length_reg),
.modulus_length(modulus_length_reg),
.cycles(cycles),
.exponent_mem_api_cs(exponent_mem_api_cs),
.exponent_mem_api_wr(exponent_mem_api_wr),
.exponent_mem_api_rst(exponent_mem_api_rst),
.exponent_mem_api_write_data(wb_dat_i),
.exponent_mem_api_read_data(exponent_mem_api_read_data),
.modulus_mem_api_cs(modulus_mem_api_cs),
.modulus_mem_api_wr(modulus_mem_api_wr),
.modulus_mem_api_rst(modulus_mem_api_rst),
.modulus_mem_api_write_data(wb_dat_i),
.modulus_mem_api_read_data(modulus_mem_api_read_data),
.message_mem_api_cs(message_mem_api_cs),
.message_mem_api_wr(message_mem_api_wr),
.message_mem_api_rst(message_mem_api_rst),
.message_mem_api_write_data(wb_dat_i),
.message_mem_api_read_data(message_mem_api_read_data),
.result_mem_api_cs(result_mem_api_cs),
.result_mem_api_rst(result_mem_api_rst),
.result_mem_api_read_data(result_mem_api_read_data)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge wb_clk_i or negedge reset_n)
begin
if (!reset_n)
begin
start_reg <= 1'b0;
exponent_length_reg <= DEFAULT_EXPLENGTH;
modulus_length_reg <= DEFAULT_MODLENGTH;
end
else
begin
start_reg <= start_new;
if (exponent_length_we)
begin
exponent_length_reg <= wb_dat_i[7 : 0];
end
if (modulus_length_we)
begin
modulus_length_reg <= wb_dat_i[7 : 0];
end
end
end // reg_update
//----------------------------------------------------------------
// api
//
// The interface command decoding logic.
//----------------------------------------------------------------
always @*
begin : api
modulus_length_we = 1'b0;
exponent_length_we = 1'b0;
start_new = 1'b0;
modulus_mem_api_rst = 1'b0;
modulus_mem_api_cs = 1'b0;
modulus_mem_api_wr = 1'b0;
exponent_mem_api_rst = 1'b0;
exponent_mem_api_cs = 1'b0;
exponent_mem_api_wr = 1'b0;
message_mem_api_rst = 1'b0;
message_mem_api_cs = 1'b0;
message_mem_api_wr = 1'b0;
result_mem_api_rst = 1'b0;
result_mem_api_cs = 1'b0;
wb_dat_o = 32'h00000000;
if (wb_stb_i)
begin
if (wb_we_i)
begin
case (wb_adr_i[9:2])
ADDR_CTRL:
begin
start_new = wb_dat_i[0];
end
ADDR_MODULUS_LENGTH:
begin
modulus_length_we = 1'b1;
end
ADDR_EXPONENT_LENGTH:
begin
exponent_length_we = 1'b1;
end
ADDR_MODULUS_PTR_RST:
begin
modulus_mem_api_rst = 1'b1;
end
ADDR_MODULUS_DATA:
begin
modulus_mem_api_cs = 1'b1;
modulus_mem_api_wr = 1'b1;
end
ADDR_EXPONENT_PTR_RST:
begin
exponent_mem_api_rst = 1'b1;
end
ADDR_EXPONENT_DATA:
begin
exponent_mem_api_cs = 1'b1;
exponent_mem_api_wr = 1'b1;
end
ADDR_MESSAGE_PTR_RST:
begin
message_mem_api_rst = 1'b1;
end
ADDR_MESSAGE_DATA:
begin
message_mem_api_cs = 1'b1;
message_mem_api_wr = 1'b1;
end
ADDR_RESULT_PTR_RST:
begin
result_mem_api_rst = 1'b1;
end
default:
begin
end
endcase // case (wb_adr_i[7 : 0])
end // if (wb_we_i)
else
begin
case (wb_adr_i[9:2])
ADDR_NAME0:
wb_dat_o = CORE_NAME0;
ADDR_NAME1:
wb_dat_o = CORE_NAME1;
ADDR_VERSION:
wb_dat_o = CORE_VERSION;
ADDR_CTRL:
wb_dat_o = {31'h00000000, start_reg};
ADDR_STATUS:
wb_dat_o = {31'h00000000, ready};
ADDR_CYCLES_HIGH:
wb_dat_o = cycles[63 : 32];
ADDR_CYCLES_LOW:
wb_dat_o = cycles[31 : 0];
ADDR_MODULUS_LENGTH:
wb_dat_o = {24'h000000, modulus_length_reg};
ADDR_EXPONENT_LENGTH:
wb_dat_o = {24'h000000, exponent_length_reg};
ADDR_MODULUS_DATA:
begin
modulus_mem_api_cs = 1'b1;
wb_dat_o = modulus_mem_api_read_data;
end
ADDR_EXPONENT_DATA:
begin
exponent_mem_api_cs = 1'b1;
wb_dat_o = exponent_mem_api_read_data;
end
ADDR_MESSAGE_DATA:
begin
message_mem_api_cs = 1'b1;
wb_dat_o = message_mem_api_read_data;
end
ADDR_RESULT_DATA:
begin
result_mem_api_cs = 1'b1;
wb_dat_o = result_mem_api_read_data;
end
default:
begin
end
endcase // case (wb_adr_i)
end // else: !if(wb_we_i)
end // if (wb_stb_i)
end // block: api
endmodule // modexp
//======================================================================
// EOF modexp_top.v
//======================================================================
|
//======================================================================
//
// montprod.v
// ---------
// Montgomery product calculator for the modular exponentiantion core.
//
// parameter OPW is operand word width in bits.
// parameter ADW is address width in bits.
//
//
// Author: Peter Magnusson, Joachim Strombergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module montprod #(parameter OPW = 32, parameter ADW = 8)
(
input wire clk,
input wire reset_n,
input wire calculate,
output wire ready,
input wire [(ADW - 1) : 0] length,
output wire [(ADW - 1) : 0] opa_addr,
input wire [(OPW - 1) : 0] opa_data,
output wire [(ADW - 1) : 0] opb_addr,
input wire [(OPW - 1) : 0] opb_data,
output wire [(ADW - 1) : 0] opm_addr,
input wire [(OPW - 1) : 0] opm_data,
output wire [(ADW - 1) : 0] result_addr,
output wire [(OPW - 1) : 0] result_data,
output wire result_we
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam CTRL_IDLE = 4'h0;
localparam CTRL_LOOP_ITER = 4'h1;
localparam CTRL_LOOP_BQ = 4'h2;
localparam CTRL_CALC_ADD = 4'h3;
localparam CTRL_STALLPIPE_ADD = 4'h4;
localparam CTRL_CALC_SDIV2 = 4'h5;
localparam CTRL_STALLPIPE_SDIV2 = 4'h6;
localparam CTRL_L_STALLPIPE_ES = 4'h7;
localparam CTRL_EMIT_S = 4'h8;
localparam SMUX_ZERO = 2'h0;
localparam SMUX_ADD = 2'h1;
localparam SMUX_SHR = 2'h2;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg ready_reg;
reg ready_new;
reg ready_we;
reg [3 : 0] montprod_ctrl_reg;
reg [3 : 0] montprod_ctrl_new;
reg montprod_ctrl_we;
reg [1 : 0] s_mux_new;
reg [1 : 0] s_mux_reg;
reg s_mem_we_reg;
reg s_mem_we_new;
reg [(ADW - 1) : 0] s_mem_read_addr_reg;
reg q_new;
reg q_reg;
reg b_new;
reg b_reg;
reg bq_we;
reg [12 : 0] loop_ctr_reg;
reg [12 : 0] loop_ctr_new;
reg loop_ctr_we;
reg loop_ctr_set;
reg loop_ctr_dec;
reg [(13 - ADW - 1) : 0] b_bit_index_reg;
reg [(13 - ADW - 1) : 0] b_bit_index_new;
reg b_bit_index_we;
reg [(ADW - 1) : 0] word_index_reg;
reg [(ADW - 1) : 0] word_index_new;
reg word_index_we;
reg [(ADW - 1) : 0] word_index_prev_reg;
reg reset_word_index_lsw;
reg reset_word_index_msw;
reg inc_word_index;
reg dec_word_index;
reg add_carry_in_sa_reg;
reg add_carry_in_sa_new;
reg add_carry_in_sm_reg;
reg add_carry_in_sm_new;
reg shr_carry_in_reg;
reg shr_carry_in_new;
reg first_iteration_reg;
reg first_iteration_new;
reg first_iteration_we;
reg test_reg;
reg test_new;
reg [(OPW - 2) : 0] shr_data_out_reg;
reg shr_carry_out_reg;
reg shr_carry_out_new;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire [(OPW - 1) : 0] add_result_sa;
wire add_carry_out_sa;
wire [(OPW - 1) : 0] add_result_sm;
wire add_carry_out_sm;
reg [(ADW - 1) : 0] b_word_index; //loop counter as a word index
/* verilator lint_off UNOPTFLAT */
reg [(OPW - 1) : 0] shr_data_in;
/* verilator lint_on UNOPTFLAT */
wire shr_carry_out;
wire [(OPW - 1) : 0] shr_data_out;
reg [(ADW - 1) : 0] tmp_opa_addr;
reg tmp_result_we;
reg [(ADW - 1) : 0] s_mem_read_addr;
wire [(OPW - 1) : 0] s_mem_read_data;
reg [(ADW - 1) : 0] s_mem_write_addr;
reg [(OPW - 1) : 0] s_mem_write_data;
reg [(OPW - 1) : 0] tmp_s_mem_write_data;
reg [(OPW - 1) : 0] sa_adder_data_in;
/* verilator lint_off UNOPTFLAT */
reg [(OPW - 1) : 0] muxed_s_mem_read_data;
/* verilator lint_on UNOPTFLAT */
reg [(OPW - 1) : 0] shifted_s_mem_write_data;
wire [(ADW - 1) : 0] length_m1;
// Temporary debug wires.
reg [1 : 0] state_trace;
reg [1 : 0] mux_trace;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign length_m1 = length - 1'b1;
assign opa_addr = tmp_opa_addr;
assign opb_addr = b_word_index;
assign opm_addr = word_index_reg;
assign result_addr = word_index_prev_reg;
assign result_data = s_mem_read_data;
assign result_we = tmp_result_we;
assign ready = ready_reg;
//----------------------------------------------------------------
// Instantions
//----------------------------------------------------------------
blockmem1r1w #(.OPW(OPW), .ADW(ADW)) s_mem(
.clk(clk),
.read_addr(s_mem_read_addr),
.read_data(s_mem_read_data),
.wr(s_mem_we_reg),
.write_addr(s_mem_write_addr),
.write_data(s_mem_write_data)
);
adder #(.OPW(OPW)) s_adder_sm(
.a(muxed_s_mem_read_data),
.b(opm_data),
.carry_in(add_carry_in_sm_reg),
.sum(add_result_sm),
.carry_out(add_carry_out_sm)
);
adder #(.OPW(OPW)) s_adder_sa(
.a(sa_adder_data_in),
.b(opa_data),
.carry_in(add_carry_in_sa_reg),
.sum(add_result_sa),
.carry_out(add_carry_out_sa)
);
shr #(.OPW(OPW)) shifter(
.a(shr_data_in),
.carry_in(shr_carry_in_reg),
.adiv2(shr_data_out),
.carry_out(shr_carry_out)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
if (!reset_n)
begin
test_reg <= 1'b1;
ready_reg <= 1'b1;
loop_ctr_reg <= 13'h0;
word_index_reg <= {ADW{1'b0}};
word_index_prev_reg <= {ADW{1'b0}};
add_carry_in_sa_reg <= 1'b0;
add_carry_in_sm_reg <= 1'b0;
shr_data_out_reg <= {(OPW - 1){1'b0}};
shr_carry_in_reg <= 1'b0;
b_reg <= 1'b0;
q_reg <= 1'b0;
s_mux_reg <= SMUX_ZERO;
s_mem_we_reg <= 1'b0;
s_mem_read_addr_reg <= {ADW{1'b0}};
b_bit_index_reg <= {(13 - ADW){1'b0}};
first_iteration_reg <= 1'b0;
montprod_ctrl_reg <= CTRL_IDLE;
end
else
begin
test_reg <= test_new;
s_mem_read_addr_reg <= s_mem_read_addr;
s_mem_we_reg <= s_mem_we_new;
s_mux_reg <= s_mux_new;
word_index_prev_reg <= word_index_reg;
shr_carry_in_reg <= shr_carry_in_new;
add_carry_in_sa_reg <= add_carry_in_sa_new;
add_carry_in_sm_reg <= add_carry_in_sm_new;
shr_data_out_reg <= shr_data_out[(OPW - 2) : 0];
if (word_index_we)
word_index_reg <= word_index_new;
if (first_iteration_we)
first_iteration_reg <= first_iteration_new;
if (b_bit_index_we)
b_bit_index_reg <= b_bit_index_new;
if (bq_we)
begin
b_reg <= b_new;
q_reg <= q_new;
end
if (ready_we)
ready_reg <= ready_new;
if (loop_ctr_we)
loop_ctr_reg <= loop_ctr_new;
if (montprod_ctrl_we)
begin
montprod_ctrl_reg <= montprod_ctrl_new;
end
end
end // reg_update
//----------------------------------------------------------------
// s_logic
//
// Logic to calculate S memory updates including address
// and write enable. This is the main montprod datapath.
//----------------------------------------------------------------
always @*
begin : s_logic
shr_carry_in_new = 1'b0;
muxed_s_mem_read_data = {OPW{1'b0}};
sa_adder_data_in = {OPW{1'b0}};
add_carry_in_sa_new = 1'b0;
add_carry_in_sm_new = 1'b0;
s_mem_read_addr = word_index_reg;
s_mem_write_addr = s_mem_read_addr_reg;
s_mem_write_data = {OPW{1'b0}};
s_mem_we_new = 1'b0;
state_trace = 0;
mux_trace = 0;
tmp_s_mem_write_data = {OPW{1'b0}};
test_new = 1'b0;
case (montprod_ctrl_reg)
CTRL_LOOP_ITER:
begin
s_mem_read_addr = length_m1;
end
CTRL_CALC_ADD:
begin
//s = (s + q*M + b*A) >>> 1;, if(b==1) S+= A. Takes (1..length) cycles.
s_mem_we_new = b_reg | q_reg | first_iteration_reg;
state_trace = 1;
test_new = 1'b1;
end
CTRL_CALC_SDIV2:
begin
//s = (s + q*M + b*A) >>> 1; s>>=1. Takes (1..length) cycles.
s_mem_we_new = 1'b1;
end
default:
begin
end
endcase
case (s_mux_reg)
SMUX_ADD:
begin
mux_trace = 1;
if (first_iteration_reg)
muxed_s_mem_read_data = {OPW{1'b0}};
else
muxed_s_mem_read_data = s_mem_read_data;
if (q_reg)
sa_adder_data_in = add_result_sm;
else
sa_adder_data_in = muxed_s_mem_read_data;
if (b_reg)
tmp_s_mem_write_data = add_result_sa;
else if (q_reg)
tmp_s_mem_write_data = add_result_sm;
else if (first_iteration_reg)
tmp_s_mem_write_data = {OPW{1'b0}};
s_mem_write_data = tmp_s_mem_write_data;
add_carry_in_sa_new = add_carry_out_sa;
add_carry_in_sm_new = add_carry_out_sm;
// Experimental integration of shift in add.
shr_data_in = tmp_s_mem_write_data;
shifted_s_mem_write_data = {shr_carry_out, shr_data_out_reg};
end
SMUX_SHR:
begin
shr_data_in = s_mem_read_data;
s_mem_write_data = shr_data_out;
shr_carry_in_new = shr_carry_out;
end
default:
begin
end
endcase
end // s_logic
//----------------------------------------------------------------
// bq
//
// Extract b and q bits.
// b: current bit of B used.
// q = (s - b * A) & 1
// update the b bit and word indices based on loop counter.
//----------------------------------------------------------------
always @*
begin : bq
b_new = opb_data[b_bit_index_reg];
if (first_iteration_reg)
q_new = 1'b0 ^ (opa_data[0] & b_new);
else
q_new = s_mem_read_data[0] ^ (opa_data[0] & b_new);
// B_bit_index = 5'h1f - loop_counter[4:0];
b_bit_index_new = ((2**(13 - ADW)) - 1'b1) - loop_ctr_reg[(13 - ADW - 1) : 0];
b_word_index = loop_ctr_reg[12 : (13 - ADW)];
end // bq
//----------------------------------------------------------------
// word_index
//
// Logic that implements the word index used to drive
// addresses for operands.
//----------------------------------------------------------------
always @*
begin : word_index
word_index_new = {ADW{1'b0}};
word_index_we = 1'b0;
if (reset_word_index_lsw)
begin
word_index_new = length_m1;
word_index_we = 1'b1;
end
if (reset_word_index_msw)
begin
word_index_new = {ADW{1'b0}};
word_index_we = 1'b1;
end
if (inc_word_index)
begin
word_index_new = word_index_reg + 1'b1;
word_index_we = 1'b1;
end
if (dec_word_index)
begin
word_index_new = word_index_reg - 1'b1;
word_index_we = 1'b1;
end
end // word_index
//----------------------------------------------------------------
// loop_ctr
// Logic for updating the loop counter.
//----------------------------------------------------------------
always @*
begin : loop_ctr
loop_ctr_new = 13'h0;
loop_ctr_we = 1'b0;
if (loop_ctr_set)
begin
loop_ctr_new = {length, {(13 - ADW){1'b0}}} - 1'b1;
loop_ctr_we = 1'b1;
end
if (loop_ctr_dec)
begin
loop_ctr_new = loop_ctr_reg - 1'b1;
loop_ctr_we = 1'b1;
end
end
//----------------------------------------------------------------
// montprod_ctrl
//
// Control FSM for the montgomery product calculator.
//----------------------------------------------------------------
always @*
begin : montprod_ctrl
ready_new = 1'b0;
ready_we = 1'b0;
loop_ctr_set = 1'b0;
loop_ctr_dec = 1'b0;
b_bit_index_we = 1'b0;
bq_we = 1'b0;
s_mux_new = SMUX_ZERO;
dec_word_index = 1'b0;
inc_word_index = 1'b0;
reset_word_index_lsw = 1'b0;
reset_word_index_msw = 1'b0;
first_iteration_new = 1'b0;
first_iteration_we = 1'b0;
tmp_opa_addr = word_index_reg;
tmp_result_we = 1'b0;
montprod_ctrl_new = CTRL_IDLE;
montprod_ctrl_we = 1'b0;
case (montprod_ctrl_reg)
CTRL_IDLE:
begin
if (calculate)
begin
first_iteration_new = 1'b1;
first_iteration_we = 1'b1;
ready_new = 1'b0;
ready_we = 1'b1;
reset_word_index_lsw = 1'b1;
loop_ctr_set = 1'b1;
montprod_ctrl_new = CTRL_LOOP_ITER;
montprod_ctrl_we = 1'b1;
end
end
//calculate q = (s - b * A) & 1;.
// Also abort loop if done.
CTRL_LOOP_ITER:
begin
tmp_opa_addr = length_m1;
b_bit_index_we = 1'b1;
montprod_ctrl_new = CTRL_LOOP_BQ;
montprod_ctrl_we = 1'b1;
end
CTRL_LOOP_BQ:
begin
reset_word_index_lsw = 1'b1;
bq_we = 1'b1;
montprod_ctrl_new = CTRL_CALC_ADD;
montprod_ctrl_we = 1'b1;
end
CTRL_CALC_ADD:
begin
s_mux_new = SMUX_ADD;
if (word_index_reg == 0)
begin
reset_word_index_lsw = 1'b1;
montprod_ctrl_new = CTRL_STALLPIPE_ADD;
montprod_ctrl_we = 1'b1;
end
else
begin
dec_word_index = 1'b1;
end
end
CTRL_STALLPIPE_ADD:
begin
first_iteration_new = 1'b0;
first_iteration_we = 1'b1;
reset_word_index_msw = 1'b1;
montprod_ctrl_new = CTRL_CALC_SDIV2;
montprod_ctrl_we = 1'b1;
end
CTRL_CALC_SDIV2:
begin
s_mux_new = SMUX_SHR;
if (word_index_reg == length_m1)
begin
montprod_ctrl_new = CTRL_STALLPIPE_SDIV2;
montprod_ctrl_we = 1'b1;
end
else
inc_word_index = 1'b1;
end
CTRL_STALLPIPE_SDIV2:
begin
loop_ctr_dec = 1'b1;
montprod_ctrl_new = CTRL_LOOP_ITER;
montprod_ctrl_we = 1'b1;
reset_word_index_lsw = 1'b1;
if (loop_ctr_reg == 0)
begin
montprod_ctrl_new = CTRL_L_STALLPIPE_ES;
montprod_ctrl_we = 1'b1;
end
end
CTRL_L_STALLPIPE_ES:
begin
montprod_ctrl_new = CTRL_EMIT_S;
montprod_ctrl_we = 1'b1;
end
CTRL_EMIT_S:
begin
dec_word_index = 1'b1;
tmp_result_we = 1'b1;
if (word_index_prev_reg == 0)
begin
ready_new = 1'b1;
ready_we = 1'b1;
montprod_ctrl_new = CTRL_IDLE;
montprod_ctrl_we = 1'b1;
end
end
default:
begin
end
endcase // case (montprod_ctrl_reg)
end // montprod_ctrl
endmodule // montprod
//======================================================================
// EOF montprod.v
//======================================================================
|
//======================================================================
//
// residue.v
// ---------
// Modulus 2**2N residue calculator for montgomery calculations.
//
// m_residue_2_2N_array( N, M, Nr)
// Nr = 00...01 ; Nr = 1 == 2**(2N-2N)
// for (int i = 0; i < 2 * N; i++)
// Nr = Nr shift left 1
// if (Nr less than M) continue;
// Nr = Nr - M
// return Nr
//
//
//
// Author: Peter Magnusson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module residue #(parameter OPW = 32, parameter ADW = 8)
(
input wire clk,
input wire reset_n,
input wire calculate,
output wire ready,
input wire [14 : 0] nn, //MAX(2*N)=8192*2 (14 bit)
input wire [(ADW - 1) : 0] length,
output wire [(ADW - 1) : 0] opa_rd_addr,
input wire [(OPW - 1) : 0] opa_rd_data,
output wire [(ADW - 1) : 0] opa_wr_addr,
output wire [(OPW - 1) : 0] opa_wr_data,
output wire opa_wr_we,
output wire [(ADW - 1) : 0] opm_addr,
input wire [(OPW - 1) : 0] opm_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam CTRL_IDLE = 4'h0;
localparam CTRL_INIT = 4'h1;
localparam CTRL_INIT_STALL = 4'h2;
localparam CTRL_SHL = 4'h3;
localparam CTRL_SHL_STALL = 4'h4;
localparam CTRL_COMPARE = 4'h5;
localparam CTRL_COMPARE_STALL = 4'h6;
localparam CTRL_SUB = 4'h7;
localparam CTRL_SUB_STALL = 4'h8;
localparam CTRL_LOOP = 4'h9;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [(ADW - 1) : 0] opa_rd_addr_reg;
reg [(ADW - 1) : 0] opa_wr_addr_reg;
reg [(OPW - 1) : 0] opa_wr_data_reg;
reg opa_wr_we_reg;
reg [(ADW - 1) : 0] opm_addr_reg;
reg ready_reg;
reg ready_new;
reg ready_we;
reg [03 : 0] residue_ctrl_reg;
reg [03 : 0] residue_ctrl_new;
reg residue_ctrl_we;
reg reset_word_index;
reg reset_n_counter;
reg [14 : 0] loop_counter_1_to_nn_reg; //for i = 1 to nn (2*N)
reg [14 : 0] loop_counter_1_to_nn_new;
reg loop_counter_1_to_nn_we;
reg [14 : 0] nn_reg;
reg nn_we;
reg [(ADW - 1) : 0] length_m1_reg;
reg [(ADW - 1) : 0] length_m1_new;
reg length_m1_we;
reg [(ADW - 1) : 0] word_index_reg;
reg [(ADW - 1) : 0] word_index_new;
reg word_index_we;
reg [(OPW - 1) : 0] one_data;
wire [(OPW - 1) : 0] sub_data;
wire [(OPW - 1) : 0] shl_data;
reg sub_carry_in_new;
reg sub_carry_in_reg;
wire sub_carry_out;
reg shl_carry_in_new;
reg shl_carry_in_reg;
wire shl_carry_out;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign opa_rd_addr = opa_rd_addr_reg;
assign opa_wr_addr = opa_wr_addr_reg;
assign opa_wr_data = opa_wr_data_reg;
assign opa_wr_we = opa_wr_we_reg;
assign opm_addr = opm_addr_reg;
assign ready = ready_reg;
//----------------------------------------------------------------
// Instantions
//----------------------------------------------------------------
adder #(.OPW(OPW)) add_inst(
.a(opa_rd_data),
.b( ~ opm_data),
.carry_in(sub_carry_in_reg),
.sum(sub_data),
.carry_out(sub_carry_out)
);
shl #(.OPW(OPW)) shl_inst(
.a(opa_rd_data),
.carry_in(shl_carry_in_reg),
.amul2(shl_data),
.carry_out(shl_carry_out)
);
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
residue_ctrl_reg <= CTRL_IDLE;
word_index_reg <= {ADW{1'b1}};
length_m1_reg <= {ADW{1'b1}};
nn_reg <= 15'h0;
loop_counter_1_to_nn_reg <= 15'h0;
ready_reg <= 1'b1;
sub_carry_in_reg <= 1'b0;
shl_carry_in_reg <= 1'b0;
end
else
begin
if (residue_ctrl_we)
residue_ctrl_reg <= residue_ctrl_new;
if (word_index_we)
word_index_reg <= word_index_new;
if (length_m1_we)
length_m1_reg <= length_m1_new;
if (nn_we)
nn_reg <= nn;
if (loop_counter_1_to_nn_we)
loop_counter_1_to_nn_reg <= loop_counter_1_to_nn_new;
if (ready_we)
ready_reg <= ready_new;
sub_carry_in_reg <= sub_carry_in_new;
shl_carry_in_reg <= shl_carry_in_new;
end
end // reg_update
//----------------------------------------------------------------
// loop counter process. implements for (int i = 0; i < 2 * N; i++)
//
// m_residue_2_2N_array( N, M, Nr)
// Nr = 00...01 ; Nr = 1 == 2**(2N-2N)
// for (int i = 0; i < 2 * N; i++)
// Nr = Nr shift left 1
// if (Nr less than M) continue;
// Nr = Nr - M
// return Nr
//
//----------------------------------------------------------------
always @*
begin : process_1_to_2n
loop_counter_1_to_nn_new = loop_counter_1_to_nn_reg + 15'h1;
loop_counter_1_to_nn_we = 1'b0;
if (reset_n_counter)
begin
loop_counter_1_to_nn_new = 15'h1;
loop_counter_1_to_nn_we = 1'b1;
end
if (residue_ctrl_reg == CTRL_LOOP)
loop_counter_1_to_nn_we = 1'b1;
end
//----------------------------------------------------------------
// implements looping over words in a multiword operation
//----------------------------------------------------------------
always @*
begin : word_index_process
word_index_new = word_index_reg - 1'b1;
word_index_we = 1'b1;
if (reset_word_index)
word_index_new = length_m1_reg;
if (residue_ctrl_reg == CTRL_IDLE)
//reduce a pipeline stage with early read
word_index_new = length_m1_new;
end
//----------------------------------------------------------------
// writer process. implements:
// Nr = 00...01 ; Nr = 1 == 2**(2N-2N)
// Nr = Nr shift left 1
// Nr = Nr - M
//
// m_residue_2_2N_array( N, M, Nr)
// Nr = 00...01 ; Nr = 1 == 2**(2N-2N)
// for (int i = 0; i < 2 * N; i++)
// Nr = Nr shift left 1
// if (Nr less than M) continue;
// Nr = Nr - M
// return Nr
//----------------------------------------------------------------
always @*
begin : writer_process
opa_wr_addr_reg = word_index_reg;
case (residue_ctrl_reg)
CTRL_INIT:
begin
opa_wr_data_reg = one_data;
opa_wr_we_reg = 1'b1;
end
CTRL_SUB:
begin
opa_wr_data_reg = sub_data;
opa_wr_we_reg = 1'b1;
end
CTRL_SHL:
begin
opa_wr_data_reg = shl_data;
opa_wr_we_reg = 1'b1;
end
default:
begin
opa_wr_data_reg = 32'h0;
opa_wr_we_reg = 1'b0;
end
endcase
end
//----------------------------------------------------------------
// reader process. reads from new value because it occurs one
// cycle earlier than the writer.
//----------------------------------------------------------------
always @*
begin : reader_process
opa_rd_addr_reg = word_index_new;
opm_addr_reg = word_index_new;
end
//----------------------------------------------------------------
// carry process. "Ripple carry awesomeness!"
//----------------------------------------------------------------
always @*
begin : carry_process
case (residue_ctrl_reg)
CTRL_COMPARE:
sub_carry_in_new = sub_carry_out;
CTRL_SUB:
sub_carry_in_new = sub_carry_out;
default:
sub_carry_in_new = 1'b1;
endcase
case (residue_ctrl_reg)
CTRL_SHL:
shl_carry_in_new = shl_carry_out;
default:
shl_carry_in_new = 1'b0;
endcase
end
//----------------------------------------------------------------
// Nr = 00...01 ; Nr = 1 == 2**(2N-2N)
//----------------------------------------------------------------
always @*
begin : one_process
one_data = 32'h0;
if (residue_ctrl_reg == CTRL_INIT)
if (word_index_reg == length_m1_reg)
one_data = {{(OPW - 1){1'b0}}, 1'b1};
end
//----------------------------------------------------------------
// residue_ctrl
//
// Control FSM for residue
//----------------------------------------------------------------
always @*
begin : residue_ctrl
ready_new = 1'b0;
ready_we = 1'b0;
reset_word_index = 1'b0;
reset_n_counter = 1'b0;
length_m1_new = length - 1'b1;
length_m1_we = 1'b0;
nn_we = 1'b0;
residue_ctrl_new = CTRL_IDLE;
residue_ctrl_we = 1'b0;
case (residue_ctrl_reg)
CTRL_IDLE:
if (calculate)
begin
ready_new = 1'b0;
ready_we = 1'b1;
reset_word_index = 1'b1;
length_m1_we = 1'b1;
nn_we = 1'b1;
residue_ctrl_new = CTRL_INIT;
residue_ctrl_we = 1'b1;
end
// Nr = 00...01 ; Nr = 1 == 2**(2N-2N)
CTRL_INIT:
if (word_index_reg == 0)
begin
residue_ctrl_new = CTRL_INIT_STALL;
residue_ctrl_we = 1'b1;
end
CTRL_INIT_STALL:
begin
reset_word_index = 1'b1;
reset_n_counter = 1'b1;
residue_ctrl_new = CTRL_SHL;
residue_ctrl_we = 1'b1;
end
// Nr = Nr shift left 1
CTRL_SHL:
begin
if (word_index_reg == 0)
begin
residue_ctrl_new = CTRL_SHL_STALL;
residue_ctrl_we = 1'b1;
end
end
CTRL_SHL_STALL:
begin
reset_word_index = 1'b1;
residue_ctrl_new = CTRL_COMPARE;
residue_ctrl_we = 1'b1;
end
//if (Nr less than M) continue
CTRL_COMPARE:
if (word_index_reg == 0)
begin
residue_ctrl_new = CTRL_COMPARE_STALL;
residue_ctrl_we = 1'b1;
end
CTRL_COMPARE_STALL:
begin
reset_word_index = 1'b1;
residue_ctrl_we = 1'b1;
if (sub_carry_in_reg == 1'b1)
//TODO: Bug! detect CF to detect less than, but no detect ZF to detect equal to.
residue_ctrl_new = CTRL_SUB;
else
residue_ctrl_new = CTRL_LOOP;
end
//Nr = Nr - M
CTRL_SUB:
if (word_index_reg == 0)
begin
residue_ctrl_new = CTRL_SUB_STALL;
residue_ctrl_we = 1'b1;
end
CTRL_SUB_STALL:
begin
residue_ctrl_new = CTRL_LOOP;
residue_ctrl_we = 1'b1;
end
//for (int i = 0; i < 2 * N; i++)
CTRL_LOOP:
begin
if (loop_counter_1_to_nn_reg == nn_reg)
begin
ready_new = 1'b1;
ready_we = 1'b1;
residue_ctrl_new = CTRL_IDLE;
residue_ctrl_we = 1'b1;
end
else
begin
reset_word_index = 1'b1;
residue_ctrl_new = CTRL_SHL;
residue_ctrl_we = 1'b1;
end
end
default:
begin
end
endcase
end
endmodule // residue
//======================================================================
// EOF residue.v
//======================================================================
|
//======================================================================
//
// shl.v
// -----
// One bit left shift of words with carry in and carry out. Used in
// the residue module of the modexp core.
//
//
// Author: Peter Magnusson, Joachim Strömbergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module shl #(parameter OPW = 32)
(
input wire [(OPW - 1) : 0] a,
input wire carry_in,
output wire [(OPW - 1) : 0] amul2,
output wire carry_out
);
assign amul2 = {a[(OPW - 2) : 0], carry_in};
assign carry_out = a[(OPW - 1)];
endmodule // shl
//======================================================================
// EOF shl.v
//======================================================================
|
//======================================================================
//
// shr32.v
// -------
// One bit right shift with carry in and carry out.
// Used in the montprod module of the modexp core.
//
//
// Author: Peter Magnusson, Joachim Strömbergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module shr #(parameter OPW = 32)
(
input wire [(OPW - 1) : 0] a,
input wire carry_in,
output wire [(OPW - 1) : 0] adiv2,
output wire carry_out
);
assign adiv2 = {carry_in, a[(OPW - 1) : 1]};
assign carry_out = a[0];
endmodule // shr
//======================================================================
// EOF shr.v
//======================================================================
|
//======================================================================
//
// sha256_core.v
// -------------
// Verilog 2001 implementation of the SHA-256 hash function.
// This is the internal core with wide interfaces.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2013, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
// Modified by Matthew Hicks:
// Convert to synchronous, positive level reset
// Fix at 256-bit mode
module sha256(
input wire clk,
input wire rst,
input wire init,
input wire next,
input wire [511 : 0] block,
output wire ready,
output wire [255 : 0] digest,
output wire digest_valid
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter SHA256_H0_0 = 32'h6a09e667;
parameter SHA256_H0_1 = 32'hbb67ae85;
parameter SHA256_H0_2 = 32'h3c6ef372;
parameter SHA256_H0_3 = 32'ha54ff53a;
parameter SHA256_H0_4 = 32'h510e527f;
parameter SHA256_H0_5 = 32'h9b05688c;
parameter SHA256_H0_6 = 32'h1f83d9ab;
parameter SHA256_H0_7 = 32'h5be0cd19;
parameter SHA256_ROUNDS = 63;
parameter CTRL_IDLE = 0;
parameter CTRL_ROUNDS = 1;
parameter CTRL_DONE = 2;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] a_reg;
reg [31 : 0] a_new;
reg [31 : 0] b_reg;
reg [31 : 0] b_new;
reg [31 : 0] c_reg;
reg [31 : 0] c_new;
reg [31 : 0] d_reg;
reg [31 : 0] d_new;
reg [31 : 0] e_reg;
reg [31 : 0] e_new;
reg [31 : 0] f_reg;
reg [31 : 0] f_new;
reg [31 : 0] g_reg;
reg [31 : 0] g_new;
reg [31 : 0] h_reg;
reg [31 : 0] h_new;
reg a_h_we;
reg [31 : 0] H0_reg;
reg [31 : 0] H0_new;
reg [31 : 0] H1_reg;
reg [31 : 0] H1_new;
reg [31 : 0] H2_reg;
reg [31 : 0] H2_new;
reg [31 : 0] H3_reg;
reg [31 : 0] H3_new;
reg [31 : 0] H4_reg;
reg [31 : 0] H4_new;
reg [31 : 0] H5_reg;
reg [31 : 0] H5_new;
reg [31 : 0] H6_reg;
reg [31 : 0] H6_new;
reg [31 : 0] H7_reg;
reg [31 : 0] H7_new;
reg H_we;
reg [5 : 0] t_ctr_reg;
reg [5 : 0] t_ctr_new;
reg t_ctr_we;
reg t_ctr_inc;
reg t_ctr_rst;
reg digest_valid_reg;
reg digest_valid_new;
reg digest_valid_we;
reg [1 : 0] sha256_ctrl_reg;
reg [1 : 0] sha256_ctrl_new;
reg sha256_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg digest_init;
reg digest_update;
reg state_init;
reg state_update;
reg first_block;
reg ready_flag;
reg [31 : 0] t1;
reg [31 : 0] t2;
wire [31 : 0] k_data;
reg w_init;
reg w_next;
wire [31 : 0] w_data;
//----------------------------------------------------------------
// Module instantiantions.
//----------------------------------------------------------------
sha256_k_constants k_constants_inst(
.addr(t_ctr_reg),
.K(k_data)
);
sha256_w_mem w_mem_inst(
.clk(clk),
.rst(rst),
.block(block),
.init(w_init),
.next(w_next),
.w(w_data)
);
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign ready = ready_flag;
assign digest = {H0_reg, H1_reg, H2_reg, H3_reg,
H4_reg, H5_reg, H6_reg, H7_reg};
assign digest_valid = digest_valid_reg;
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
if (rst)
begin
a_reg <= 32'h0;
b_reg <= 32'h0;
c_reg <= 32'h0;
d_reg <= 32'h0;
e_reg <= 32'h0;
f_reg <= 32'h0;
g_reg <= 32'h0;
h_reg <= 32'h0;
H0_reg <= 32'h0;
H1_reg <= 32'h0;
H2_reg <= 32'h0;
H3_reg <= 32'h0;
H4_reg <= 32'h0;
H5_reg <= 32'h0;
H6_reg <= 32'h0;
H7_reg <= 32'h0;
digest_valid_reg <= 0;
t_ctr_reg <= 6'h0;
sha256_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (a_h_we)
begin
a_reg <= a_new;
b_reg <= b_new;
c_reg <= c_new;
d_reg <= d_new;
e_reg <= e_new;
f_reg <= f_new;
g_reg <= g_new;
h_reg <= h_new;
end
if (H_we)
begin
H0_reg <= H0_new;
H1_reg <= H1_new;
H2_reg <= H2_new;
H3_reg <= H3_new;
H4_reg <= H4_new;
H5_reg <= H5_new;
H6_reg <= H6_new;
H7_reg <= H7_new;
end
if (t_ctr_we)
t_ctr_reg <= t_ctr_new;
if (digest_valid_we)
digest_valid_reg <= digest_valid_new;
if (sha256_ctrl_we)
sha256_ctrl_reg <= sha256_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// digest_logic
//
// The logic needed to init as well as update the digest.
//----------------------------------------------------------------
always @*
begin : digest_logic
H0_new = 32'h0;
H1_new = 32'h0;
H2_new = 32'h0;
H3_new = 32'h0;
H4_new = 32'h0;
H5_new = 32'h0;
H6_new = 32'h0;
H7_new = 32'h0;
H_we = 0;
if (digest_init)
begin
H_we = 1;
H0_new = SHA256_H0_0;
H1_new = SHA256_H0_1;
H2_new = SHA256_H0_2;
H3_new = SHA256_H0_3;
H4_new = SHA256_H0_4;
H5_new = SHA256_H0_5;
H6_new = SHA256_H0_6;
H7_new = SHA256_H0_7;
end
if (digest_update)
begin
H0_new = H0_reg + a_reg;
H1_new = H1_reg + b_reg;
H2_new = H2_reg + c_reg;
H3_new = H3_reg + d_reg;
H4_new = H4_reg + e_reg;
H5_new = H5_reg + f_reg;
H6_new = H6_reg + g_reg;
H7_new = H7_reg + h_reg;
H_we = 1;
end
end // digest_logic
//----------------------------------------------------------------
// t1_logic
//
// The logic for the T1 function.
//----------------------------------------------------------------
always @*
begin : t1_logic
reg [31 : 0] sum1;
reg [31 : 0] ch;
sum1 = {e_reg[5 : 0], e_reg[31 : 6]} ^
{e_reg[10 : 0], e_reg[31 : 11]} ^
{e_reg[24 : 0], e_reg[31 : 25]};
ch = (e_reg & f_reg) ^ ((~e_reg) & g_reg);
t1 = h_reg + sum1 + ch + w_data + k_data;
end // t1_logic
//----------------------------------------------------------------
// t2_logic
//
// The logic for the T2 function
//----------------------------------------------------------------
always @*
begin : t2_logic
reg [31 : 0] sum0;
reg [31 : 0] maj;
sum0 = {a_reg[1 : 0], a_reg[31 : 2]} ^
{a_reg[12 : 0], a_reg[31 : 13]} ^
{a_reg[21 : 0], a_reg[31 : 22]};
maj = (a_reg & b_reg) ^ (a_reg & c_reg) ^ (b_reg & c_reg);
t2 = sum0 + maj;
end // t2_logic
//----------------------------------------------------------------
// state_logic
//
// The logic needed to init as well as update the state during
// round processing.
//----------------------------------------------------------------
always @*
begin : state_logic
a_new = 32'h0;
b_new = 32'h0;
c_new = 32'h0;
d_new = 32'h0;
e_new = 32'h0;
f_new = 32'h0;
g_new = 32'h0;
h_new = 32'h0;
a_h_we = 0;
if (state_init)
begin
a_h_we = 1;
if (first_block)
begin
a_new = SHA256_H0_0;
b_new = SHA256_H0_1;
c_new = SHA256_H0_2;
d_new = SHA256_H0_3;
e_new = SHA256_H0_4;
f_new = SHA256_H0_5;
g_new = SHA256_H0_6;
h_new = SHA256_H0_7;
end
else
begin
a_new = H0_reg;
b_new = H1_reg;
c_new = H2_reg;
d_new = H3_reg;
e_new = H4_reg;
f_new = H5_reg;
g_new = H6_reg;
h_new = H7_reg;
end
end
if (state_update)
begin
a_new = t1 + t2;
b_new = a_reg;
c_new = b_reg;
d_new = c_reg;
e_new = d_reg + t1;
f_new = e_reg;
g_new = f_reg;
h_new = g_reg;
a_h_we = 1;
end
end // state_logic
//----------------------------------------------------------------
// t_ctr
//
// Update logic for the round counter, a monotonically
// increasing counter with reset.
//----------------------------------------------------------------
always @*
begin : t_ctr
t_ctr_new = 0;
t_ctr_we = 0;
if (t_ctr_rst)
begin
t_ctr_new = 0;
t_ctr_we = 1;
end
if (t_ctr_inc)
begin
t_ctr_new = t_ctr_reg + 1'b1;
t_ctr_we = 1;
end
end // t_ctr
//----------------------------------------------------------------
// sha256_ctrl_fsm
//
// Logic for the state machine controlling the core behaviour.
//----------------------------------------------------------------
always @*
begin : sha256_ctrl_fsm
digest_init = 0;
digest_update = 0;
state_init = 0;
state_update = 0;
first_block = 0;
ready_flag = 0;
w_init = 0;
w_next = 0;
t_ctr_inc = 0;
t_ctr_rst = 0;
digest_valid_new = 0;
digest_valid_we = 0;
sha256_ctrl_new = CTRL_IDLE;
sha256_ctrl_we = 0;
case (sha256_ctrl_reg)
CTRL_IDLE:
begin
ready_flag = 1;
if (init)
begin
digest_init = 1;
w_init = 1;
state_init = 1;
first_block = 1;
t_ctr_rst = 1;
digest_valid_new = 0;
digest_valid_we = 1;
sha256_ctrl_new = CTRL_ROUNDS;
sha256_ctrl_we = 1;
end
if (next)
begin
t_ctr_rst = 1;
w_init = 1;
state_init = 1;
digest_valid_new = 0;
digest_valid_we = 1;
sha256_ctrl_new = CTRL_ROUNDS;
sha256_ctrl_we = 1;
end
end
CTRL_ROUNDS:
begin
w_next = 1;
state_update = 1;
t_ctr_inc = 1;
if (t_ctr_reg == SHA256_ROUNDS)
begin
sha256_ctrl_new = CTRL_DONE;
sha256_ctrl_we = 1;
end
end
CTRL_DONE:
begin
digest_update = 1;
digest_valid_new = 1;
digest_valid_we = 1;
sha256_ctrl_new = CTRL_IDLE;
sha256_ctrl_we = 1;
end
endcase // case (sha256_ctrl_reg)
end // sha256_ctrl_fsm
endmodule // sha256_core
//======================================================================
// EOF sha256_core.v
//======================================================================
|
//======================================================================
//
// sha256_k_constants.v
// --------------------
// The table K with constants in the SHA-256 hash function.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2013, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module sha256_k_constants(
input wire [5 : 0] addr,
output wire [31 : 0] K
);
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_K;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign K = tmp_K;
//----------------------------------------------------------------
// addr_mux
//----------------------------------------------------------------
always @*
begin : addr_mux
case(addr)
00:
tmp_K = 32'h428a2f98;
01:
tmp_K = 32'h71374491;
02:
tmp_K = 32'hb5c0fbcf;
03:
tmp_K = 32'he9b5dba5;
04:
tmp_K = 32'h3956c25b;
05:
tmp_K = 32'h59f111f1;
06:
tmp_K = 32'h923f82a4;
07:
tmp_K = 32'hab1c5ed5;
08:
tmp_K = 32'hd807aa98;
09:
tmp_K = 32'h12835b01;
10:
tmp_K = 32'h243185be;
11:
tmp_K = 32'h550c7dc3;
12:
tmp_K = 32'h72be5d74;
13:
tmp_K = 32'h80deb1fe;
14:
tmp_K = 32'h9bdc06a7;
15:
tmp_K = 32'hc19bf174;
16:
tmp_K = 32'he49b69c1;
17:
tmp_K = 32'hefbe4786;
18:
tmp_K = 32'h0fc19dc6;
19:
tmp_K = 32'h240ca1cc;
20:
tmp_K = 32'h2de92c6f;
21:
tmp_K = 32'h4a7484aa;
22:
tmp_K = 32'h5cb0a9dc;
23:
tmp_K = 32'h76f988da;
24:
tmp_K = 32'h983e5152;
25:
tmp_K = 32'ha831c66d;
26:
tmp_K = 32'hb00327c8;
27:
tmp_K = 32'hbf597fc7;
28:
tmp_K = 32'hc6e00bf3;
29:
tmp_K = 32'hd5a79147;
30:
tmp_K = 32'h06ca6351;
31:
tmp_K = 32'h14292967;
32:
tmp_K = 32'h27b70a85;
33:
tmp_K = 32'h2e1b2138;
34:
tmp_K = 32'h4d2c6dfc;
35:
tmp_K = 32'h53380d13;
36:
tmp_K = 32'h650a7354;
37:
tmp_K = 32'h766a0abb;
38:
tmp_K = 32'h81c2c92e;
39:
tmp_K = 32'h92722c85;
40:
tmp_K = 32'ha2bfe8a1;
41:
tmp_K = 32'ha81a664b;
42:
tmp_K = 32'hc24b8b70;
43:
tmp_K = 32'hc76c51a3;
44:
tmp_K = 32'hd192e819;
45:
tmp_K = 32'hd6990624;
46:
tmp_K = 32'hf40e3585;
47:
tmp_K = 32'h106aa070;
48:
tmp_K = 32'h19a4c116;
49:
tmp_K = 32'h1e376c08;
50:
tmp_K = 32'h2748774c;
51:
tmp_K = 32'h34b0bcb5;
52:
tmp_K = 32'h391c0cb3;
53:
tmp_K = 32'h4ed8aa4a;
54:
tmp_K = 32'h5b9cca4f;
55:
tmp_K = 32'h682e6ff3;
56:
tmp_K = 32'h748f82ee;
57:
tmp_K = 32'h78a5636f;
58:
tmp_K = 32'h84c87814;
59:
tmp_K = 32'h8cc70208;
60:
tmp_K = 32'h90befffa;
61:
tmp_K = 32'ha4506ceb;
62:
tmp_K = 32'hbef9a3f7;
63:
tmp_K = 32'hc67178f2;
endcase // case (addr)
end // block: addr_mux
endmodule // sha256_k_constants
//======================================================================
// sha256_k_constants.v
//======================================================================
|
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : sha256_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-SHA256 core
//
module sha256_top(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
wb_ack_o, wb_err_o, wb_dat_o,
wb_clk_i, wb_rst_i, int_o
);
parameter dw = 32;
parameter aw = 32;
input [aw-1:0] wb_adr_i;
input wb_cyc_i;
input [dw-1:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_stb_i;
input wb_we_i;
output wb_ack_o;
output wb_err_o;
output reg [dw-1:0] wb_dat_o;
output int_o;
input wb_clk_i;
input wb_rst_i;
assign wb_ack_o = 1'b1;
assign wb_err_o = 1'b0;
assign int_o = 1'b0;
// Internal registers
reg startHash, startHash_r;
reg newMessage, newMessage_r;
reg [31:0] data [0:15];
wire [511:0] bigData = {data[15], data[14], data[13], data[12], data[11], data[10], data[9], data[8], data[7], data[6], data[5], data[4], data[3], data[2], data[1], data[0]};
wire [255:0] hash;
wire ready;
wire hashValid;
// Implement SHA256 I/O memory map interface
// Write side
always @(posedge wb_clk_i)
begin
if(wb_rst_i)
begin
startHash <= 0;
startHash_r <= 0;
newMessage <= 0;
newMessage_r <= 0;
data[0] <= 0;
data[1] <= 0;
data[2] <= 0;
data[3] <= 0;
data[4] <= 0;
data[5] <= 0;
data[6] <= 0;
data[7] <= 0;
data[8] <= 0;
data[9] <= 0;
data[10] <= 0;
data[11] <= 0;
data[12] <= 0;
data[13] <= 0;
data[14] <= 0;
data[15] <= 0;
end
else begin
// Generate a registered versions of startHash and newMessage
startHash_r <= startHash;
newMessage_r <= newMessage;
// Perform a write
if(wb_stb_i & wb_we_i) begin
case(wb_adr_i[6:2])
0: begin
startHash <= wb_dat_i[0];
newMessage <= wb_dat_i[1];
end
1: data[0] <= wb_dat_i;
2: data[1] <= wb_dat_i;
3: data[2] <= wb_dat_i;
4: data[3] <= wb_dat_i;
5: data[4] <= wb_dat_i;
6: data[5] <= wb_dat_i;
7: data[6] <= wb_dat_i;
8: data[7] <= wb_dat_i;
9: data[8] <= wb_dat_i;
10: data[9] <= wb_dat_i;
11: data[10] <= wb_dat_i;
12: data[11] <= wb_dat_i;
13: data[12] <= wb_dat_i;
14: data[13] <= wb_dat_i;
15: data[14] <= wb_dat_i;
16: data[15] <= wb_dat_i;
default:
;
endcase
end else begin
startHash <= 1'b0;
newMessage <= 1'b0;
end // end else
end
end // end always
// Implement SHA256 I/O memory map interface
// Read side
always @(*)
begin
case(wb_adr_i[6:2])
0: wb_dat_o = {31'b0, ready};
1: wb_dat_o = data[0];
2: wb_dat_o = data[1];
3: wb_dat_o = data[2];
4: wb_dat_o = data[3];
5: wb_dat_o = data[4];
6: wb_dat_o = data[5];
7: wb_dat_o = data[6];
8: wb_dat_o = data[7];
9: wb_dat_o = data[8];
10: wb_dat_o = data[9];
11: wb_dat_o = data[10];
12: wb_dat_o = data[11];
13: wb_dat_o = data[12];
14: wb_dat_o = data[13];
15: wb_dat_o = data[14];
16: wb_dat_o = data[15];
17: wb_dat_o = {31'b0, hashValid};
18: wb_dat_o = hash[31:0];
19: wb_dat_o = hash[63:32];
20: wb_dat_o = hash[95:64];
21: wb_dat_o = hash[127:96];
22: wb_dat_o = hash[159:128];
23: wb_dat_o = hash[191:160];
24: wb_dat_o = hash[223:192];
25: wb_dat_o = hash[255:224];
default:
wb_dat_o = 32'b0;
endcase
end
sha256 sha256(
.clk(wb_clk_i),
.rst(wb_rst_i),
.init(startHash && ~startHash_r),
.next(newMessage && ~newMessage_r),
.block(bigData),
.digest(hash),
.digest_valid(hashValid),
.ready(ready)
);
endmodule
|
//======================================================================
//
// sha256_w_mem_regs.v
// -------------------
// The W memory. This version uses 16 32-bit registers as a sliding
// window to generate the 64 words.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2013, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module sha256_w_mem(
input wire clk,
input wire rst,
input wire [511 : 0] block,
input wire init,
input wire next,
output wire [31 : 0] w
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter CTRL_IDLE = 0;
parameter CTRL_UPDATE = 1;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] w_mem [0 : 15];
reg [31 : 0] w_mem00_new;
reg [31 : 0] w_mem01_new;
reg [31 : 0] w_mem02_new;
reg [31 : 0] w_mem03_new;
reg [31 : 0] w_mem04_new;
reg [31 : 0] w_mem05_new;
reg [31 : 0] w_mem06_new;
reg [31 : 0] w_mem07_new;
reg [31 : 0] w_mem08_new;
reg [31 : 0] w_mem09_new;
reg [31 : 0] w_mem10_new;
reg [31 : 0] w_mem11_new;
reg [31 : 0] w_mem12_new;
reg [31 : 0] w_mem13_new;
reg [31 : 0] w_mem14_new;
reg [31 : 0] w_mem15_new;
reg w_mem_we;
reg [5 : 0] w_ctr_reg;
reg [5 : 0] w_ctr_new;
reg w_ctr_we;
reg w_ctr_inc;
reg w_ctr_rst;
reg [1 : 0] sha256_w_mem_ctrl_reg;
reg [1 : 0] sha256_w_mem_ctrl_new;
reg sha256_w_mem_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] w_tmp;
reg [31 : 0] w_new;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign w = w_tmp;
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
if (rst)
begin
w_mem[00] <= 32'h0;
w_mem[01] <= 32'h0;
w_mem[02] <= 32'h0;
w_mem[03] <= 32'h0;
w_mem[04] <= 32'h0;
w_mem[05] <= 32'h0;
w_mem[06] <= 32'h0;
w_mem[07] <= 32'h0;
w_mem[08] <= 32'h0;
w_mem[09] <= 32'h0;
w_mem[10] <= 32'h0;
w_mem[11] <= 32'h0;
w_mem[12] <= 32'h0;
w_mem[13] <= 32'h0;
w_mem[14] <= 32'h0;
w_mem[15] <= 32'h0;
w_ctr_reg <= 6'h00;
sha256_w_mem_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (w_mem_we)
begin
w_mem[00] <= w_mem00_new;
w_mem[01] <= w_mem01_new;
w_mem[02] <= w_mem02_new;
w_mem[03] <= w_mem03_new;
w_mem[04] <= w_mem04_new;
w_mem[05] <= w_mem05_new;
w_mem[06] <= w_mem06_new;
w_mem[07] <= w_mem07_new;
w_mem[08] <= w_mem08_new;
w_mem[09] <= w_mem09_new;
w_mem[10] <= w_mem10_new;
w_mem[11] <= w_mem11_new;
w_mem[12] <= w_mem12_new;
w_mem[13] <= w_mem13_new;
w_mem[14] <= w_mem14_new;
w_mem[15] <= w_mem15_new;
end
if (w_ctr_we)
w_ctr_reg <= w_ctr_new;
if (sha256_w_mem_ctrl_we)
sha256_w_mem_ctrl_reg <= sha256_w_mem_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// select_w
//
// Mux for the external read operation. This is where we exract
// the W variable.
//----------------------------------------------------------------
always @*
begin : select_w
if (w_ctr_reg < 16)
begin
w_tmp = w_mem[w_ctr_reg[3 : 0]];
end
else
begin
w_tmp = w_new;
end
end // select_w
//----------------------------------------------------------------
// w_new_logic
//
// Logic that calculates the next value to be inserted into
// the sliding window of the memory.
//----------------------------------------------------------------
always @*
begin : w_mem_update_logic
reg [31 : 0] w_0;
reg [31 : 0] w_1;
reg [31 : 0] w_9;
reg [31 : 0] w_14;
reg [31 : 0] d0;
reg [31 : 0] d1;
w_mem00_new = 32'h0;
w_mem01_new = 32'h0;
w_mem02_new = 32'h0;
w_mem03_new = 32'h0;
w_mem04_new = 32'h0;
w_mem05_new = 32'h0;
w_mem06_new = 32'h0;
w_mem07_new = 32'h0;
w_mem08_new = 32'h0;
w_mem09_new = 32'h0;
w_mem10_new = 32'h0;
w_mem11_new = 32'h0;
w_mem12_new = 32'h0;
w_mem13_new = 32'h0;
w_mem14_new = 32'h0;
w_mem15_new = 32'h0;
w_mem_we = 0;
w_0 = w_mem[0];
w_1 = w_mem[1];
w_9 = w_mem[9];
w_14 = w_mem[14];
d0 = {w_1[6 : 0], w_1[31 : 7]} ^
{w_1[17 : 0], w_1[31 : 18]} ^
{3'b000, w_1[31 : 3]};
d1 = {w_14[16 : 0], w_14[31 : 17]} ^
{w_14[18 : 0], w_14[31 : 19]} ^
{10'b0000000000, w_14[31 : 10]};
w_new = d1 + w_9 + d0 + w_0;
if (init)
begin
w_mem00_new = block[511 : 480];
w_mem01_new = block[479 : 448];
w_mem02_new = block[447 : 416];
w_mem03_new = block[415 : 384];
w_mem04_new = block[383 : 352];
w_mem05_new = block[351 : 320];
w_mem06_new = block[319 : 288];
w_mem07_new = block[287 : 256];
w_mem08_new = block[255 : 224];
w_mem09_new = block[223 : 192];
w_mem10_new = block[191 : 160];
w_mem11_new = block[159 : 128];
w_mem12_new = block[127 : 96];
w_mem13_new = block[95 : 64];
w_mem14_new = block[63 : 32];
w_mem15_new = block[31 : 0];
w_mem_we = 1;
end
else if (w_ctr_reg > 15)
begin
w_mem00_new = w_mem[01];
w_mem01_new = w_mem[02];
w_mem02_new = w_mem[03];
w_mem03_new = w_mem[04];
w_mem04_new = w_mem[05];
w_mem05_new = w_mem[06];
w_mem06_new = w_mem[07];
w_mem07_new = w_mem[08];
w_mem08_new = w_mem[09];
w_mem09_new = w_mem[10];
w_mem10_new = w_mem[11];
w_mem11_new = w_mem[12];
w_mem12_new = w_mem[13];
w_mem13_new = w_mem[14];
w_mem14_new = w_mem[15];
w_mem15_new = w_new;
w_mem_we = 1;
end
end // w_mem_update_logic
//----------------------------------------------------------------
// w_ctr
// W schedule adress counter. Counts from 0x10 to 0x3f and
// is used to expand the block into words.
//----------------------------------------------------------------
always @*
begin : w_ctr
w_ctr_new = 0;
w_ctr_we = 0;
if (w_ctr_rst)
begin
w_ctr_new = 6'h00;
w_ctr_we = 1;
end
if (w_ctr_inc)
begin
w_ctr_new = w_ctr_reg + 6'h01;
w_ctr_we = 1;
end
end // w_ctr
//----------------------------------------------------------------
// sha256_w_mem_fsm
// Logic for the w shedule FSM.
//----------------------------------------------------------------
always @*
begin : sha256_w_mem_fsm
w_ctr_rst = 0;
w_ctr_inc = 0;
sha256_w_mem_ctrl_new = CTRL_IDLE;
sha256_w_mem_ctrl_we = 0;
case (sha256_w_mem_ctrl_reg)
CTRL_IDLE:
begin
if (init)
begin
w_ctr_rst = 1;
sha256_w_mem_ctrl_new = CTRL_UPDATE;
sha256_w_mem_ctrl_we = 1;
end
end
CTRL_UPDATE:
begin
if (next)
begin
w_ctr_inc = 1;
end
if (w_ctr_reg == 6'h3f)
begin
sha256_w_mem_ctrl_new = CTRL_IDLE;
sha256_w_mem_ctrl_we = 1;
end
end
endcase // case (sha256_ctrl_reg)
end // sha256_ctrl_fsm
endmodule // sha256_w_mem
//======================================================================
// sha256_w_mem.v
//======================================================================
|
/* Copyright (c) 2012-2013 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* ============================================================================
*
* Global defines for the whole debug system
*
* Author(s):
* Philipp Wagner <[email protected]>
*/
/*
* Width of a timestamp provided by the Global Timestamp Provider (GTP)
* The timestamp increments every clock cycle of the fastest clock in the system
* and should be big enough to be unique until the data reaches the host PC.
* Note: Changing this parameter requires changes in the flit packaging
* logic as well (e.g. in itm_dbgnoc_if.v)!
* TODO: We still need to find a proper width for this timestamp
*/
`define DBG_TIMESTAMP_WIDTH 32
/*
* Delay in clock cycles between a local (outgoing) and a remote (incoming)
* trigger event.
*
* This delays all trace data for the given number of cycles before deciding
* if it should be used or not, e.g. if the trigger matches or not.
* Consider a simple example with one register between CTM and the debug module
* on both directions:
* ITM generates trigger event -> 1 T delay -> CTM (comb.) -> 1 T delay ->
* ITM registers incoming trigger event
* This means only after two cycles it's clear if the captured data should be
* used. So we delay the capatured data for two cycles by using a shift register
* and make sure to delay all trigger signals by this same (fixed) time as well
* before we decide to use the data or not.
*
* Make this buffer as big as the longest latency between the CTM and a debug
* module, and make sure to delay all internally generated triggers by this
* time as well.
*/
`define DBG_TRIGGER_DELAY 2
/*
* Router addresses of predefined modules
*/
// Address of the external interface, connecting the Debug NoC to the host PC
`define DBG_NOC_ADDR_EXTERNALIF 5'd0
// Address of the Trace Controller Module (TCM)
`define DBG_NOC_ADDR_TCM 5'd1
// Begin of the dynamic address range
`define DBG_NOC_ADDR_DYN_START 5'd2
// note: the max. address is 2^DBG_NOC_PH_DEST_WIDTH-1, currently set to 31
// register read request
`define DBG_NOC_CLASS_REG_READ_REQ 3'b000
// register read response
`define DBG_NOC_CLASS_REG_READ_RESP 3'b001
// register write request
`define DBG_NOC_CLASS_REG_WRITE_REQ 3'b010
// software trace data (from STM)
`define DBG_NOC_CLASS_SOFT_TRACE_DATA 3'b011
// instruction trace data (from ITM)
`define DBG_NOC_CLASS_TRACE_DATA 3'b100
// network router statistics (from NRM)
`define DBG_NOC_CLASS_NRM_DATA 3'b101
// encapsulated lisnoc32 packets
`define DBG_NOC_CLASS_NCM 3'b111
/*
* Maximum length of packets (number of flits, including the header flit) that
* can be sent from the Debug NoC to the USB interface.
*
* The currently used protocol requires a limit like this (even though the
* size is arbitrary, it only defines a FIFO depth).
* XXX: Enhance the Debug Noc -> USB protocol to remove this restriction.
*/
`define MAX_DBGNOC_TO_USB_PACKET_LENGTH 32
/*
* This is the execution traceport in a single signal
*
* Bit 102: enable
* Bit 101-70: program counter
* Bit 69-38: instruction
* Bit 37: writeback enable
* Bit 36-32: writeback register
* Bit 31-0: writeback data
*/
`define DEBUG_TRACE_EXEC_WIDTH 103
`define DEBUG_TRACE_EXEC_ENABLE_MSB 102
`define DEBUG_TRACE_EXEC_ENABLE_LSB 102
`define DEBUG_TRACE_EXEC_PC_MSB 101
`define DEBUG_TRACE_EXEC_PC_LSB 70
`define DEBUG_TRACE_EXEC_INSN_MSB 69
`define DEBUG_TRACE_EXEC_INSN_LSB 38
`define DEBUG_TRACE_EXEC_WBEN_MSB 37
`define DEBUG_TRACE_EXEC_WBEN_LSB 37
`define DEBUG_TRACE_EXEC_WBREG_MSB 36
`define DEBUG_TRACE_EXEC_WBREG_LSB 32
`define DEBUG_TRACE_EXEC_WBDATA_MSB 31
`define DEBUG_TRACE_EXEC_WBDATA_LSB 0
|
// Copyright 2016 by the authors
//
// Copyright and related rights are licensed under the Solderpad
// Hardware License, Version 0.51 (the "License"); you may not use
// this file except in compliance with the License. You may obtain a
// copy of the License at http://solderpad.org/licenses/SHL-0.51.
// Unless required by applicable law or agreed to in writing,
// software, hardware and materials distributed under this License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
// OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the
// License.
//
// Authors:
// Wei Song <[email protected]>
// Stefan Wallentowitz <[email protected]>
package dii_package;
typedef struct packed unsigned {
logic valid;
logic last;
logic [15:0] data;
} dii_flit;
function dii_flit
dii_flit_assemble(
input logic m_valid,
input logic m_last,
input logic [15:0] m_data
);
return dii_flit'{m_valid, m_last, m_data};
endfunction
endpackage // dii_package
|
// Copyright 2016 by the authors
//
// Copyright and related rights are licensed under the Solderpad
// Hardware License, Version 0.51 (the "License"); you may not use
// this file except in compliance with the License. You may obtain a
// copy of the License at http://solderpad.org/licenses/SHL-0.51.
// Unless required by applicable law or agreed to in writing,
// software, hardware and materials distributed under this License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
// OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the
// License.
//
// Authors:
// Stefan Wallentowitz <[email protected]>
package opensocdebug;
typedef struct packed {
logic [31:0] insn;
logic [31:0] pc;
logic jb;
logic jal;
logic jr;
logic [31:0] jbtarget;
logic valid;
logic [31:0] wbdata;
logic [4:0] wbreg;
logic wben;
} mor1kx_trace_exec;
endpackage // opensocdebug
|
/*
* This source file contains a Verilog description of an IP core
* automatically generated by the SPIRAL HDL Generator.
*
* This product includes a hardware design developed by Carnegie Mellon University.
*
* Copyright (c) 2005-2011 by Peter A. Milder for the SPIRAL Project,
* Carnegie Mellon University
*
* For more information, see the SPIRAL project website at:
* http://www.spiral.net
*
* This design is provided for internal, non-commercial research use only
* and is not for redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
// Input/output stream: 2 complex words per cycle
// Throughput: one transform every 32 cycles
// Latency: 332 cycles
// Resources required:
// 20 multipliers (16 x 16 bit)
// 34 adders (16 x 16 bit)
// 4 RAMs (16 words, 32 bits per word)
// 4 RAMs (8 words, 32 bits per word)
// 12 RAMs (64 words, 32 bits per word)
// 4 RAMs (32 words, 32 bits per word)
// 2 ROMs (32 words, 16 bits per word)
// 2 ROMs (8 words, 16 bits per word)
// 12 ROMs (32 words, 5 bits per word)
// 2 ROMs (16 words, 16 bits per word)
// Generated on Tue Sep 04 00:43:02 EDT 2018
// Latency: 332 clock cycles
// Throughput: 1 transform every 32 cycles
// We use an interleaved complex data format. X0 represents the
// real portion of the first input, and X1 represents the imaginary
// portion. The X variables are system inputs and the Y variables
// are system outputs.
// The design uses a system of flag signals to indicate the
// beginning of the input and output data streams. The 'next'
// input (asserted high), is used to instruct the system that the
// input stream will begin on the following cycle.
// This system has a 'gap' of 32 cycles. This means that
// 32 cycles must elapse between the beginning of the input
// vectors.
// The output signal 'next_out' (also asserted high) indicates
// that the output vector will begin streaming out of the system
// on the following cycle.
// The system has a latency of 332 cycles. This means that
// the 'next_out' will be asserted 332 cycles after the user
// asserts 'next'.
// The simple testbench below will demonstrate the timing for loading
// and unloading data vectors.
// The system reset signal is asserted high.
// Please note: when simulating floating point code, you must include
// Xilinx's DSP slice simulation module.
// Latency: 332
// Gap: 32
// module_name_is:dft_top
module dft_top(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [15:0] t0_0;
wire [15:0] t0_1;
wire [15:0] t0_2;
wire [15:0] t0_3;
wire next_0;
wire [15:0] t1_0;
wire [15:0] t1_1;
wire [15:0] t1_2;
wire [15:0] t1_3;
wire next_1;
wire [15:0] t2_0;
wire [15:0] t2_1;
wire [15:0] t2_2;
wire [15:0] t2_3;
wire next_2;
wire [15:0] t3_0;
wire [15:0] t3_1;
wire [15:0] t3_2;
wire [15:0] t3_3;
wire next_3;
wire [15:0] t4_0;
wire [15:0] t4_1;
wire [15:0] t4_2;
wire [15:0] t4_3;
wire next_4;
wire [15:0] t5_0;
wire [15:0] t5_1;
wire [15:0] t5_2;
wire [15:0] t5_3;
wire next_5;
wire [15:0] t6_0;
wire [15:0] t6_1;
wire [15:0] t6_2;
wire [15:0] t6_3;
wire next_6;
wire [15:0] t7_0;
wire [15:0] t7_1;
wire [15:0] t7_2;
wire [15:0] t7_3;
wire next_7;
wire [15:0] t8_0;
wire [15:0] t8_1;
wire [15:0] t8_2;
wire [15:0] t8_3;
wire next_8;
wire [15:0] t9_0;
wire [15:0] t9_1;
wire [15:0] t9_2;
wire [15:0] t9_3;
wire next_9;
wire [15:0] t10_0;
wire [15:0] t10_1;
wire [15:0] t10_2;
wire [15:0] t10_3;
wire next_10;
wire [15:0] t11_0;
wire [15:0] t11_1;
wire [15:0] t11_2;
wire [15:0] t11_3;
wire next_11;
wire [15:0] t12_0;
wire [15:0] t12_1;
wire [15:0] t12_2;
wire [15:0] t12_3;
wire next_12;
wire [15:0] t13_0;
wire [15:0] t13_1;
wire [15:0] t13_2;
wire [15:0] t13_3;
wire next_13;
wire [15:0] t14_0;
wire [15:0] t14_1;
wire [15:0] t14_2;
wire [15:0] t14_3;
wire next_14;
wire [15:0] t15_0;
wire [15:0] t15_1;
wire [15:0] t15_2;
wire [15:0] t15_3;
wire next_15;
wire [15:0] t16_0;
wire [15:0] t16_1;
wire [15:0] t16_2;
wire [15:0] t16_3;
wire next_16;
wire [15:0] t17_0;
wire [15:0] t17_1;
wire [15:0] t17_2;
wire [15:0] t17_3;
wire next_17;
wire [15:0] t18_0;
wire [15:0] t18_1;
wire [15:0] t18_2;
wire [15:0] t18_3;
wire next_18;
assign t0_0 = X0;
assign Y0 = t18_0;
assign t0_1 = X1;
assign Y1 = t18_1;
assign t0_2 = X2;
assign Y2 = t18_2;
assign t0_3 = X3;
assign Y3 = t18_3;
assign next_0 = next;
assign next_out = next_18;
// latency=68, gap=32
rc82445 stage0(.clk(clk), .reset(reset), .next(next_0), .next_out(next_1),
.X0(t0_0), .Y0(t1_0),
.X1(t0_1), .Y1(t1_1),
.X2(t0_2), .Y2(t1_2),
.X3(t0_3), .Y3(t1_3));
// latency=2, gap=32
codeBlock82447 stage1(.clk(clk), .reset(reset), .next_in(next_1), .next_out(next_2),
.X0_in(t1_0), .Y0(t2_0),
.X1_in(t1_1), .Y1(t2_1),
.X2_in(t1_2), .Y2(t2_2),
.X3_in(t1_3), .Y3(t2_3));
// latency=8, gap=32
rc82529 stage2(.clk(clk), .reset(reset), .next(next_2), .next_out(next_3),
.X0(t2_0), .Y0(t3_0),
.X1(t2_1), .Y1(t3_1),
.X2(t2_2), .Y2(t3_2),
.X3(t2_3), .Y3(t3_3));
// latency=8, gap=32
DirSum_82710 stage3(.next(next_3), .clk(clk), .reset(reset), .next_out(next_4),
.X0(t3_0), .Y0(t4_0),
.X1(t3_1), .Y1(t4_1),
.X2(t3_2), .Y2(t4_2),
.X3(t3_3), .Y3(t4_3));
// latency=2, gap=32
codeBlock82713 stage4(.clk(clk), .reset(reset), .next_in(next_4), .next_out(next_5),
.X0_in(t4_0), .Y0(t5_0),
.X1_in(t4_1), .Y1(t5_1),
.X2_in(t4_2), .Y2(t5_2),
.X3_in(t4_3), .Y3(t5_3));
// latency=12, gap=32
rc82795 stage5(.clk(clk), .reset(reset), .next(next_5), .next_out(next_6),
.X0(t5_0), .Y0(t6_0),
.X1(t5_1), .Y1(t6_1),
.X2(t5_2), .Y2(t6_2),
.X3(t5_3), .Y3(t6_3));
// latency=8, gap=32
DirSum_82984 stage6(.next(next_6), .clk(clk), .reset(reset), .next_out(next_7),
.X0(t6_0), .Y0(t7_0),
.X1(t6_1), .Y1(t7_1),
.X2(t6_2), .Y2(t7_2),
.X3(t6_3), .Y3(t7_3));
// latency=2, gap=32
codeBlock82987 stage7(.clk(clk), .reset(reset), .next_in(next_7), .next_out(next_8),
.X0_in(t7_0), .Y0(t8_0),
.X1_in(t7_1), .Y1(t8_1),
.X2_in(t7_2), .Y2(t8_2),
.X3_in(t7_3), .Y3(t8_3));
// latency=20, gap=32
rc83069 stage8(.clk(clk), .reset(reset), .next(next_8), .next_out(next_9),
.X0(t8_0), .Y0(t9_0),
.X1(t8_1), .Y1(t9_1),
.X2(t8_2), .Y2(t9_2),
.X3(t8_3), .Y3(t9_3));
// latency=8, gap=32
DirSum_83274 stage9(.next(next_9), .clk(clk), .reset(reset), .next_out(next_10),
.X0(t9_0), .Y0(t10_0),
.X1(t9_1), .Y1(t10_1),
.X2(t9_2), .Y2(t10_2),
.X3(t9_3), .Y3(t10_3));
// latency=2, gap=32
codeBlock83277 stage10(.clk(clk), .reset(reset), .next_in(next_10), .next_out(next_11),
.X0_in(t10_0), .Y0(t11_0),
.X1_in(t10_1), .Y1(t11_1),
.X2_in(t10_2), .Y2(t11_2),
.X3_in(t10_3), .Y3(t11_3));
// latency=36, gap=32
rc83359 stage11(.clk(clk), .reset(reset), .next(next_11), .next_out(next_12),
.X0(t11_0), .Y0(t12_0),
.X1(t11_1), .Y1(t12_1),
.X2(t11_2), .Y2(t12_2),
.X3(t11_3), .Y3(t12_3));
// latency=8, gap=32
DirSum_83596 stage12(.next(next_12), .clk(clk), .reset(reset), .next_out(next_13),
.X0(t12_0), .Y0(t13_0),
.X1(t12_1), .Y1(t13_1),
.X2(t12_2), .Y2(t13_2),
.X3(t12_3), .Y3(t13_3));
// latency=2, gap=32
codeBlock83599 stage13(.clk(clk), .reset(reset), .next_in(next_13), .next_out(next_14),
.X0_in(t13_0), .Y0(t14_0),
.X1_in(t13_1), .Y1(t14_1),
.X2_in(t13_2), .Y2(t14_2),
.X3_in(t13_3), .Y3(t14_3));
// latency=68, gap=32
rc83681 stage14(.clk(clk), .reset(reset), .next(next_14), .next_out(next_15),
.X0(t14_0), .Y0(t15_0),
.X1(t14_1), .Y1(t15_1),
.X2(t14_2), .Y2(t15_2),
.X3(t14_3), .Y3(t15_3));
// latency=8, gap=32
DirSum_83981 stage15(.next(next_15), .clk(clk), .reset(reset), .next_out(next_16),
.X0(t15_0), .Y0(t16_0),
.X1(t15_1), .Y1(t16_1),
.X2(t15_2), .Y2(t16_2),
.X3(t15_3), .Y3(t16_3));
// latency=2, gap=32
codeBlock83984 stage16(.clk(clk), .reset(reset), .next_in(next_16), .next_out(next_17),
.X0_in(t16_0), .Y0(t17_0),
.X1_in(t16_1), .Y1(t17_1),
.X2_in(t16_2), .Y2(t17_2),
.X3_in(t16_3), .Y3(t17_3));
// latency=68, gap=32
rc84066 stage17(.clk(clk), .reset(reset), .next(next_17), .next_out(next_18),
.X0(t17_0), .Y0(t18_0),
.X1(t17_1), .Y1(t18_1),
.X2(t17_2), .Y2(t18_2),
.X3(t17_3), .Y3(t18_3));
endmodule
// Latency: 68
// Gap: 32
module rc82445(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm82443 instPerm85011(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet82443(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [4:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
5'd0: control <= 1'b1;
5'd1: control <= 1'b1;
5'd2: control <= 1'b1;
5'd3: control <= 1'b1;
5'd4: control <= 1'b1;
5'd5: control <= 1'b1;
5'd6: control <= 1'b1;
5'd7: control <= 1'b1;
5'd8: control <= 1'b1;
5'd9: control <= 1'b1;
5'd10: control <= 1'b1;
5'd11: control <= 1'b1;
5'd12: control <= 1'b1;
5'd13: control <= 1'b1;
5'd14: control <= 1'b1;
5'd15: control <= 1'b1;
5'd16: control <= 1'b0;
5'd17: control <= 1'b0;
5'd18: control <= 1'b0;
5'd19: control <= 1'b0;
5'd20: control <= 1'b0;
5'd21: control <= 1'b0;
5'd22: control <= 1'b0;
5'd23: control <= 1'b0;
5'd24: control <= 1'b0;
5'd25: control <= 1'b0;
5'd26: control <= 1'b0;
5'd27: control <= 1'b0;
5'd28: control <= 1'b0;
5'd29: control <= 1'b0;
5'd30: control <= 1'b0;
5'd31: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 68
// Gap: 32
module perm82443(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 32;
parameter addrbits = 5;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm0;
assign tm0 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_85016(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85017(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
nextReg #(31, 5) nextReg_85028(.X(next), .Y(next2), .reset(reset), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_85029(.X(next2), .Y(next3), .clk(clk));
nextReg #(32, 5) nextReg_85032(.X(next3), .Y(next4), .reset(reset), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85033(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(31, 1) shiftFIFO_85036(.X(tm0), .Y(tm0_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_85039(.X(tm0_d), .Y(tm0_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 5) shiftFIFO_85044(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm0_d, s1rdloc})
{1'd0, 5'd0}: s1rd0 <= 16;
{1'd0, 5'd1}: s1rd0 <= 24;
{1'd0, 5'd2}: s1rd0 <= 20;
{1'd0, 5'd3}: s1rd0 <= 28;
{1'd0, 5'd4}: s1rd0 <= 18;
{1'd0, 5'd5}: s1rd0 <= 26;
{1'd0, 5'd6}: s1rd0 <= 22;
{1'd0, 5'd7}: s1rd0 <= 30;
{1'd0, 5'd8}: s1rd0 <= 17;
{1'd0, 5'd9}: s1rd0 <= 25;
{1'd0, 5'd10}: s1rd0 <= 21;
{1'd0, 5'd11}: s1rd0 <= 29;
{1'd0, 5'd12}: s1rd0 <= 19;
{1'd0, 5'd13}: s1rd0 <= 27;
{1'd0, 5'd14}: s1rd0 <= 23;
{1'd0, 5'd15}: s1rd0 <= 31;
{1'd0, 5'd16}: s1rd0 <= 0;
{1'd0, 5'd17}: s1rd0 <= 8;
{1'd0, 5'd18}: s1rd0 <= 4;
{1'd0, 5'd19}: s1rd0 <= 12;
{1'd0, 5'd20}: s1rd0 <= 2;
{1'd0, 5'd21}: s1rd0 <= 10;
{1'd0, 5'd22}: s1rd0 <= 6;
{1'd0, 5'd23}: s1rd0 <= 14;
{1'd0, 5'd24}: s1rd0 <= 1;
{1'd0, 5'd25}: s1rd0 <= 9;
{1'd0, 5'd26}: s1rd0 <= 5;
{1'd0, 5'd27}: s1rd0 <= 13;
{1'd0, 5'd28}: s1rd0 <= 3;
{1'd0, 5'd29}: s1rd0 <= 11;
{1'd0, 5'd30}: s1rd0 <= 7;
{1'd0, 5'd31}: s1rd0 <= 15;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm0_d, s1rdloc})
{1'd0, 5'd0}: s1rd1 <= 0;
{1'd0, 5'd1}: s1rd1 <= 8;
{1'd0, 5'd2}: s1rd1 <= 4;
{1'd0, 5'd3}: s1rd1 <= 12;
{1'd0, 5'd4}: s1rd1 <= 2;
{1'd0, 5'd5}: s1rd1 <= 10;
{1'd0, 5'd6}: s1rd1 <= 6;
{1'd0, 5'd7}: s1rd1 <= 14;
{1'd0, 5'd8}: s1rd1 <= 1;
{1'd0, 5'd9}: s1rd1 <= 9;
{1'd0, 5'd10}: s1rd1 <= 5;
{1'd0, 5'd11}: s1rd1 <= 13;
{1'd0, 5'd12}: s1rd1 <= 3;
{1'd0, 5'd13}: s1rd1 <= 11;
{1'd0, 5'd14}: s1rd1 <= 7;
{1'd0, 5'd15}: s1rd1 <= 15;
{1'd0, 5'd16}: s1rd1 <= 16;
{1'd0, 5'd17}: s1rd1 <= 24;
{1'd0, 5'd18}: s1rd1 <= 20;
{1'd0, 5'd19}: s1rd1 <= 28;
{1'd0, 5'd20}: s1rd1 <= 18;
{1'd0, 5'd21}: s1rd1 <= 26;
{1'd0, 5'd22}: s1rd1 <= 22;
{1'd0, 5'd23}: s1rd1 <= 30;
{1'd0, 5'd24}: s1rd1 <= 17;
{1'd0, 5'd25}: s1rd1 <= 25;
{1'd0, 5'd26}: s1rd1 <= 21;
{1'd0, 5'd27}: s1rd1 <= 29;
{1'd0, 5'd28}: s1rd1 <= 19;
{1'd0, 5'd29}: s1rd1 <= 27;
{1'd0, 5'd30}: s1rd1 <= 23;
{1'd0, 5'd31}: s1rd1 <= 31;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet82443 sw(tm0_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm0_dd, writeCycle})
{1'd0, 5'd0}: s2wr0 <= 16;
{1'd0, 5'd1}: s2wr0 <= 17;
{1'd0, 5'd2}: s2wr0 <= 18;
{1'd0, 5'd3}: s2wr0 <= 19;
{1'd0, 5'd4}: s2wr0 <= 20;
{1'd0, 5'd5}: s2wr0 <= 21;
{1'd0, 5'd6}: s2wr0 <= 22;
{1'd0, 5'd7}: s2wr0 <= 23;
{1'd0, 5'd8}: s2wr0 <= 24;
{1'd0, 5'd9}: s2wr0 <= 25;
{1'd0, 5'd10}: s2wr0 <= 26;
{1'd0, 5'd11}: s2wr0 <= 27;
{1'd0, 5'd12}: s2wr0 <= 28;
{1'd0, 5'd13}: s2wr0 <= 29;
{1'd0, 5'd14}: s2wr0 <= 30;
{1'd0, 5'd15}: s2wr0 <= 31;
{1'd0, 5'd16}: s2wr0 <= 0;
{1'd0, 5'd17}: s2wr0 <= 1;
{1'd0, 5'd18}: s2wr0 <= 2;
{1'd0, 5'd19}: s2wr0 <= 3;
{1'd0, 5'd20}: s2wr0 <= 4;
{1'd0, 5'd21}: s2wr0 <= 5;
{1'd0, 5'd22}: s2wr0 <= 6;
{1'd0, 5'd23}: s2wr0 <= 7;
{1'd0, 5'd24}: s2wr0 <= 8;
{1'd0, 5'd25}: s2wr0 <= 9;
{1'd0, 5'd26}: s2wr0 <= 10;
{1'd0, 5'd27}: s2wr0 <= 11;
{1'd0, 5'd28}: s2wr0 <= 12;
{1'd0, 5'd29}: s2wr0 <= 13;
{1'd0, 5'd30}: s2wr0 <= 14;
{1'd0, 5'd31}: s2wr0 <= 15;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm0_dd, writeCycle})
{1'd0, 5'd0}: s2wr1 <= 0;
{1'd0, 5'd1}: s2wr1 <= 1;
{1'd0, 5'd2}: s2wr1 <= 2;
{1'd0, 5'd3}: s2wr1 <= 3;
{1'd0, 5'd4}: s2wr1 <= 4;
{1'd0, 5'd5}: s2wr1 <= 5;
{1'd0, 5'd6}: s2wr1 <= 6;
{1'd0, 5'd7}: s2wr1 <= 7;
{1'd0, 5'd8}: s2wr1 <= 8;
{1'd0, 5'd9}: s2wr1 <= 9;
{1'd0, 5'd10}: s2wr1 <= 10;
{1'd0, 5'd11}: s2wr1 <= 11;
{1'd0, 5'd12}: s2wr1 <= 12;
{1'd0, 5'd13}: s2wr1 <= 13;
{1'd0, 5'd14}: s2wr1 <= 14;
{1'd0, 5'd15}: s2wr1 <= 15;
{1'd0, 5'd16}: s2wr1 <= 16;
{1'd0, 5'd17}: s2wr1 <= 17;
{1'd0, 5'd18}: s2wr1 <= 18;
{1'd0, 5'd19}: s2wr1 <= 19;
{1'd0, 5'd20}: s2wr1 <= 20;
{1'd0, 5'd21}: s2wr1 <= 21;
{1'd0, 5'd22}: s2wr1 <= 22;
{1'd0, 5'd23}: s2wr1 <= 23;
{1'd0, 5'd24}: s2wr1 <= 24;
{1'd0, 5'd25}: s2wr1 <= 25;
{1'd0, 5'd26}: s2wr1 <= 26;
{1'd0, 5'd27}: s2wr1 <= 27;
{1'd0, 5'd28}: s2wr1 <= 28;
{1'd0, 5'd29}: s2wr1 <= 29;
{1'd0, 5'd30}: s2wr1 <= 30;
{1'd0, 5'd31}: s2wr1 <= 31;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
module memMod(in, out, inAddr, outAddr, writeSel, clk);
parameter depth=1024, width=16, logDepth=10;
input [width-1:0] in;
input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of mem is block
reg [width-1:0] mem[depth-1:0];
always @(posedge clk) begin
out <= mem[outAddr];
if (writeSel)
mem[inAddr] <= in;
end
endmodule
module memMod_dist(in, out, inAddr, outAddr, writeSel, clk);
parameter depth=1024, width=16, logDepth=10;
input [width-1:0] in;
input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of mem is distributed
reg [width-1:0] mem[depth-1:0];
always @(posedge clk) begin
out <= mem[outAddr];
if (writeSel)
mem[inAddr] <= in;
end
endmodule
module shiftRegFIFO(X, Y, clk);
parameter depth=1, width=1;
output [width-1:0] Y;
input [width-1:0] X;
input clk;
reg [width-1:0] mem [depth-1:0];
integer index;
assign Y = mem[depth-1];
always @ (posedge clk) begin
for(index=1;index<depth;index=index+1) begin
mem[index] <= mem[index-1];
end
mem[0]<=X;
end
endmodule
module nextReg(X, Y, reset, clk);
parameter depth=2, logDepth=1;
output Y;
input X;
input clk, reset;
reg [logDepth:0] count;
reg active;
assign Y = (count == depth) ? 1 : 0;
always @ (posedge clk) begin
if (reset == 1) begin
count <= 0;
active <= 0;
end
else if (X == 1) begin
active <= 1;
count <= 1;
end
else if (count == depth) begin
count <= 0;
active <= 0;
end
else if (active)
count <= count+1;
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock82447(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_85051(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a309;
wire signed [15:0] a310;
wire signed [15:0] a311;
wire signed [15:0] a312;
wire signed [15:0] t141;
wire signed [15:0] t142;
wire signed [15:0] t143;
wire signed [15:0] t144;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a309 = X0;
assign a310 = X2;
assign a311 = X1;
assign a312 = X3;
assign Y0 = t141;
assign Y1 = t142;
assign Y2 = t143;
assign Y3 = t144;
addfxp #(16, 1) add82459(.a(a309), .b(a310), .clk(clk), .q(t141)); // 0
addfxp #(16, 1) add82474(.a(a311), .b(a312), .clk(clk), .q(t142)); // 0
subfxp #(16, 1) sub82489(.a(a309), .b(a310), .clk(clk), .q(t143)); // 0
subfxp #(16, 1) sub82504(.a(a311), .b(a312), .clk(clk), .q(t144)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 8
// Gap: 2
module rc82529(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm82527 instPerm85052(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet82527(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [0:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
1'd0: control <= 1'b1;
1'd1: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 8
// Gap: 2
module perm82527(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 2;
parameter addrbits = 1;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm1;
assign tm1 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_85057(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85058(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
shiftRegFIFO #(1, 1) shiftFIFO_85067(.X(next), .Y(next2), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_85068(.X(next2), .Y(next3), .clk(clk));
shiftRegFIFO #(2, 1) shiftFIFO_85069(.X(next3), .Y(next4), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85070(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85073(.X(tm1), .Y(tm1_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_85076(.X(tm1_d), .Y(tm1_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 1) shiftFIFO_85081(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm1_d, s1rdloc})
{1'd0, 1'd0}: s1rd0 <= 1;
{1'd0, 1'd1}: s1rd0 <= 0;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm1_d, s1rdloc})
{1'd0, 1'd0}: s1rd1 <= 0;
{1'd0, 1'd1}: s1rd1 <= 1;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet82527 sw(tm1_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm1_dd, writeCycle})
{1'd0, 1'd0}: s2wr0 <= 1;
{1'd0, 1'd1}: s2wr0 <= 0;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm1_dd, writeCycle})
{1'd0, 1'd0}: s2wr1 <= 0;
{1'd0, 1'd1}: s2wr1 <= 1;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 2
module DirSum_82710(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [0:0] i5;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i5 <= 0;
end
else begin
if (next == 1)
i5 <= 0;
else if (i5 == 1)
i5 <= 0;
else
i5 <= i5 + 1;
end
end
codeBlock82532 codeBlockIsnt85082(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i5_in(i5),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D18_82700(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [0:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h0;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D20_82708(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [0:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'hc000;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock82532(clk, reset, next_in, next_out,
i5_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [0:0] i5_in;
reg [0:0] i5;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(7, 1) shiftFIFO_85085(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a293;
wire signed [15:0] a282;
wire signed [15:0] a296;
wire signed [15:0] a286;
wire signed [15:0] a297;
wire signed [15:0] a298;
reg signed [15:0] tm137;
reg signed [15:0] tm141;
reg signed [15:0] tm153;
reg signed [15:0] tm160;
reg signed [15:0] tm138;
reg signed [15:0] tm142;
reg signed [15:0] tm154;
reg signed [15:0] tm161;
wire signed [15:0] tm4;
wire signed [15:0] a287;
wire signed [15:0] tm5;
wire signed [15:0] a289;
reg signed [15:0] tm139;
reg signed [15:0] tm143;
reg signed [15:0] tm155;
reg signed [15:0] tm162;
reg signed [15:0] tm31;
reg signed [15:0] tm32;
reg signed [15:0] tm140;
reg signed [15:0] tm144;
reg signed [15:0] tm156;
reg signed [15:0] tm163;
reg signed [15:0] tm157;
reg signed [15:0] tm164;
wire signed [15:0] a288;
wire signed [15:0] a290;
wire signed [15:0] a291;
wire signed [15:0] a292;
reg signed [15:0] tm158;
reg signed [15:0] tm165;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
reg signed [15:0] tm159;
reg signed [15:0] tm166;
assign a293 = X0;
assign a282 = a293;
assign a296 = X1;
assign a286 = a296;
assign a297 = X2;
assign a298 = X3;
assign a287 = tm4;
assign a289 = tm5;
assign Y0 = tm159;
assign Y1 = tm166;
D18_82700 instD18inst0_82700(.addr(i5[0:0]), .out(tm4), .clk(clk));
D20_82708 instD20inst0_82708(.addr(i5[0:0]), .out(tm5), .clk(clk));
multfix #(16, 2) m82631(.a(tm31), .b(tm140), .clk(clk), .q_sc(a288), .q_unsc(), .rst(reset));
multfix #(16, 2) m82653(.a(tm32), .b(tm144), .clk(clk), .q_sc(a290), .q_unsc(), .rst(reset));
multfix #(16, 2) m82671(.a(tm32), .b(tm140), .clk(clk), .q_sc(a291), .q_unsc(), .rst(reset));
multfix #(16, 2) m82682(.a(tm31), .b(tm144), .clk(clk), .q_sc(a292), .q_unsc(), .rst(reset));
subfxp #(16, 1) sub82660(.a(a288), .b(a290), .clk(clk), .q(Y2)); // 6
addfxp #(16, 1) add82689(.a(a291), .b(a292), .clk(clk), .q(Y3)); // 6
always @(posedge clk) begin
if (reset == 1) begin
tm31 <= 0;
tm140 <= 0;
tm32 <= 0;
tm144 <= 0;
tm32 <= 0;
tm140 <= 0;
tm31 <= 0;
tm144 <= 0;
end
else begin
i5 <= i5_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm137 <= a297;
tm141 <= a298;
tm153 <= a282;
tm160 <= a286;
tm138 <= tm137;
tm142 <= tm141;
tm154 <= tm153;
tm161 <= tm160;
tm139 <= tm138;
tm143 <= tm142;
tm155 <= tm154;
tm162 <= tm161;
tm31 <= a287;
tm32 <= a289;
tm140 <= tm139;
tm144 <= tm143;
tm156 <= tm155;
tm163 <= tm162;
tm157 <= tm156;
tm164 <= tm163;
tm158 <= tm157;
tm165 <= tm164;
tm159 <= tm158;
tm166 <= tm165;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock82713(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_85088(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a249;
wire signed [15:0] a250;
wire signed [15:0] a251;
wire signed [15:0] a252;
wire signed [15:0] t117;
wire signed [15:0] t118;
wire signed [15:0] t119;
wire signed [15:0] t120;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a249 = X0;
assign a250 = X2;
assign a251 = X1;
assign a252 = X3;
assign Y0 = t117;
assign Y1 = t118;
assign Y2 = t119;
assign Y3 = t120;
addfxp #(16, 1) add82725(.a(a249), .b(a250), .clk(clk), .q(t117)); // 0
addfxp #(16, 1) add82740(.a(a251), .b(a252), .clk(clk), .q(t118)); // 0
subfxp #(16, 1) sub82755(.a(a249), .b(a250), .clk(clk), .q(t119)); // 0
subfxp #(16, 1) sub82770(.a(a251), .b(a252), .clk(clk), .q(t120)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 12
// Gap: 4
module rc82795(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm82793 instPerm85089(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet82793(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [1:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
2'd0: control <= 1'b1;
2'd1: control <= 1'b1;
2'd2: control <= 1'b0;
2'd3: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 12
// Gap: 4
module perm82793(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 4;
parameter addrbits = 2;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm6;
assign tm6 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_85094(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85095(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
shiftRegFIFO #(3, 1) shiftFIFO_85104(.X(next), .Y(next2), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_85105(.X(next2), .Y(next3), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_85106(.X(next3), .Y(next4), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85107(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_85110(.X(tm6), .Y(tm6_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_85113(.X(tm6_d), .Y(tm6_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 2) shiftFIFO_85118(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm6_d, s1rdloc})
{1'd0, 2'd0}: s1rd0 <= 2;
{1'd0, 2'd1}: s1rd0 <= 3;
{1'd0, 2'd2}: s1rd0 <= 0;
{1'd0, 2'd3}: s1rd0 <= 1;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm6_d, s1rdloc})
{1'd0, 2'd0}: s1rd1 <= 0;
{1'd0, 2'd1}: s1rd1 <= 1;
{1'd0, 2'd2}: s1rd1 <= 2;
{1'd0, 2'd3}: s1rd1 <= 3;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet82793 sw(tm6_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm6_dd, writeCycle})
{1'd0, 2'd0}: s2wr0 <= 2;
{1'd0, 2'd1}: s2wr0 <= 3;
{1'd0, 2'd2}: s2wr0 <= 0;
{1'd0, 2'd3}: s2wr0 <= 1;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm6_dd, writeCycle})
{1'd0, 2'd0}: s2wr1 <= 0;
{1'd0, 2'd1}: s2wr1 <= 1;
{1'd0, 2'd2}: s2wr1 <= 2;
{1'd0, 2'd3}: s2wr1 <= 3;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 4
module DirSum_82984(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [1:0] i4;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i4 <= 0;
end
else begin
if (next == 1)
i4 <= 0;
else if (i4 == 3)
i4 <= 0;
else
i4 <= i4 + 1;
end
end
codeBlock82798 codeBlockIsnt85119(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i4_in(i4),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D14_82970(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [1:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h2d41;
2: out3 <= 16'h0;
3: out3 <= 16'hd2bf;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D16_82982(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [1:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'hd2bf;
2: out3 <= 16'hc000;
3: out3 <= 16'hd2bf;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock82798(clk, reset, next_in, next_out,
i4_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [1:0] i4_in;
reg [1:0] i4;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(7, 1) shiftFIFO_85122(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a233;
wire signed [15:0] a222;
wire signed [15:0] a236;
wire signed [15:0] a226;
wire signed [15:0] a237;
wire signed [15:0] a238;
reg signed [15:0] tm167;
reg signed [15:0] tm171;
reg signed [15:0] tm183;
reg signed [15:0] tm190;
reg signed [15:0] tm168;
reg signed [15:0] tm172;
reg signed [15:0] tm184;
reg signed [15:0] tm191;
wire signed [15:0] tm9;
wire signed [15:0] a227;
wire signed [15:0] tm10;
wire signed [15:0] a229;
reg signed [15:0] tm169;
reg signed [15:0] tm173;
reg signed [15:0] tm185;
reg signed [15:0] tm192;
reg signed [15:0] tm39;
reg signed [15:0] tm40;
reg signed [15:0] tm170;
reg signed [15:0] tm174;
reg signed [15:0] tm186;
reg signed [15:0] tm193;
reg signed [15:0] tm187;
reg signed [15:0] tm194;
wire signed [15:0] a228;
wire signed [15:0] a230;
wire signed [15:0] a231;
wire signed [15:0] a232;
reg signed [15:0] tm188;
reg signed [15:0] tm195;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
reg signed [15:0] tm189;
reg signed [15:0] tm196;
assign a233 = X0;
assign a222 = a233;
assign a236 = X1;
assign a226 = a236;
assign a237 = X2;
assign a238 = X3;
assign a227 = tm9;
assign a229 = tm10;
assign Y0 = tm189;
assign Y1 = tm196;
D14_82970 instD14inst0_82970(.addr(i4[1:0]), .out(tm9), .clk(clk));
D16_82982 instD16inst0_82982(.addr(i4[1:0]), .out(tm10), .clk(clk));
multfix #(16, 2) m82897(.a(tm39), .b(tm170), .clk(clk), .q_sc(a228), .q_unsc(), .rst(reset));
multfix #(16, 2) m82919(.a(tm40), .b(tm174), .clk(clk), .q_sc(a230), .q_unsc(), .rst(reset));
multfix #(16, 2) m82937(.a(tm40), .b(tm170), .clk(clk), .q_sc(a231), .q_unsc(), .rst(reset));
multfix #(16, 2) m82948(.a(tm39), .b(tm174), .clk(clk), .q_sc(a232), .q_unsc(), .rst(reset));
subfxp #(16, 1) sub82926(.a(a228), .b(a230), .clk(clk), .q(Y2)); // 6
addfxp #(16, 1) add82955(.a(a231), .b(a232), .clk(clk), .q(Y3)); // 6
always @(posedge clk) begin
if (reset == 1) begin
tm39 <= 0;
tm170 <= 0;
tm40 <= 0;
tm174 <= 0;
tm40 <= 0;
tm170 <= 0;
tm39 <= 0;
tm174 <= 0;
end
else begin
i4 <= i4_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm167 <= a237;
tm171 <= a238;
tm183 <= a222;
tm190 <= a226;
tm168 <= tm167;
tm172 <= tm171;
tm184 <= tm183;
tm191 <= tm190;
tm169 <= tm168;
tm173 <= tm172;
tm185 <= tm184;
tm192 <= tm191;
tm39 <= a227;
tm40 <= a229;
tm170 <= tm169;
tm174 <= tm173;
tm186 <= tm185;
tm193 <= tm192;
tm187 <= tm186;
tm194 <= tm193;
tm188 <= tm187;
tm195 <= tm194;
tm189 <= tm188;
tm196 <= tm195;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock82987(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_85125(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a189;
wire signed [15:0] a190;
wire signed [15:0] a191;
wire signed [15:0] a192;
wire signed [15:0] t93;
wire signed [15:0] t94;
wire signed [15:0] t95;
wire signed [15:0] t96;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a189 = X0;
assign a190 = X2;
assign a191 = X1;
assign a192 = X3;
assign Y0 = t93;
assign Y1 = t94;
assign Y2 = t95;
assign Y3 = t96;
addfxp #(16, 1) add82999(.a(a189), .b(a190), .clk(clk), .q(t93)); // 0
addfxp #(16, 1) add83014(.a(a191), .b(a192), .clk(clk), .q(t94)); // 0
subfxp #(16, 1) sub83029(.a(a189), .b(a190), .clk(clk), .q(t95)); // 0
subfxp #(16, 1) sub83044(.a(a191), .b(a192), .clk(clk), .q(t96)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 20
// Gap: 8
module rc83069(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm83067 instPerm85126(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet83067(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [2:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
3'd0: control <= 1'b1;
3'd1: control <= 1'b1;
3'd2: control <= 1'b1;
3'd3: control <= 1'b1;
3'd4: control <= 1'b0;
3'd5: control <= 1'b0;
3'd6: control <= 1'b0;
3'd7: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 20
// Gap: 8
module perm83067(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 8;
parameter addrbits = 3;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm11;
assign tm11 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_85131(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85132(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
shiftRegFIFO #(7, 1) shiftFIFO_85141(.X(next), .Y(next2), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_85142(.X(next2), .Y(next3), .clk(clk));
shiftRegFIFO #(8, 1) shiftFIFO_85143(.X(next3), .Y(next4), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85144(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(7, 1) shiftFIFO_85147(.X(tm11), .Y(tm11_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_85150(.X(tm11_d), .Y(tm11_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 3) shiftFIFO_85155(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm11_d, s1rdloc})
{1'd0, 3'd0}: s1rd0 <= 4;
{1'd0, 3'd1}: s1rd0 <= 5;
{1'd0, 3'd2}: s1rd0 <= 6;
{1'd0, 3'd3}: s1rd0 <= 7;
{1'd0, 3'd4}: s1rd0 <= 0;
{1'd0, 3'd5}: s1rd0 <= 1;
{1'd0, 3'd6}: s1rd0 <= 2;
{1'd0, 3'd7}: s1rd0 <= 3;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm11_d, s1rdloc})
{1'd0, 3'd0}: s1rd1 <= 0;
{1'd0, 3'd1}: s1rd1 <= 1;
{1'd0, 3'd2}: s1rd1 <= 2;
{1'd0, 3'd3}: s1rd1 <= 3;
{1'd0, 3'd4}: s1rd1 <= 4;
{1'd0, 3'd5}: s1rd1 <= 5;
{1'd0, 3'd6}: s1rd1 <= 6;
{1'd0, 3'd7}: s1rd1 <= 7;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet83067 sw(tm11_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm11_dd, writeCycle})
{1'd0, 3'd0}: s2wr0 <= 4;
{1'd0, 3'd1}: s2wr0 <= 5;
{1'd0, 3'd2}: s2wr0 <= 6;
{1'd0, 3'd3}: s2wr0 <= 7;
{1'd0, 3'd4}: s2wr0 <= 0;
{1'd0, 3'd5}: s2wr0 <= 1;
{1'd0, 3'd6}: s2wr0 <= 2;
{1'd0, 3'd7}: s2wr0 <= 3;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm11_dd, writeCycle})
{1'd0, 3'd0}: s2wr1 <= 0;
{1'd0, 3'd1}: s2wr1 <= 1;
{1'd0, 3'd2}: s2wr1 <= 2;
{1'd0, 3'd3}: s2wr1 <= 3;
{1'd0, 3'd4}: s2wr1 <= 4;
{1'd0, 3'd5}: s2wr1 <= 5;
{1'd0, 3'd6}: s2wr1 <= 6;
{1'd0, 3'd7}: s2wr1 <= 7;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 8
module DirSum_83274(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [2:0] i3;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i3 <= 0;
end
else begin
if (next == 1)
i3 <= 0;
else if (i3 == 7)
i3 <= 0;
else
i3 <= i3 + 1;
end
end
codeBlock83072 codeBlockIsnt85156(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i3_in(i3),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D10_83252(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [2:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h3b21;
2: out3 <= 16'h2d41;
3: out3 <= 16'h187e;
4: out3 <= 16'h0;
5: out3 <= 16'he782;
6: out3 <= 16'hd2bf;
7: out3 <= 16'hc4df;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D12_83272(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [2:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'he782;
2: out3 <= 16'hd2bf;
3: out3 <= 16'hc4df;
4: out3 <= 16'hc000;
5: out3 <= 16'hc4df;
6: out3 <= 16'hd2bf;
7: out3 <= 16'he782;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock83072(clk, reset, next_in, next_out,
i3_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [2:0] i3_in;
reg [2:0] i3;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(7, 1) shiftFIFO_85159(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a173;
wire signed [15:0] a162;
wire signed [15:0] a176;
wire signed [15:0] a166;
wire signed [15:0] a177;
wire signed [15:0] a178;
reg signed [15:0] tm197;
reg signed [15:0] tm201;
reg signed [15:0] tm213;
reg signed [15:0] tm220;
reg signed [15:0] tm198;
reg signed [15:0] tm202;
reg signed [15:0] tm214;
reg signed [15:0] tm221;
wire signed [15:0] tm14;
wire signed [15:0] a167;
wire signed [15:0] tm15;
wire signed [15:0] a169;
reg signed [15:0] tm199;
reg signed [15:0] tm203;
reg signed [15:0] tm215;
reg signed [15:0] tm222;
reg signed [15:0] tm47;
reg signed [15:0] tm48;
reg signed [15:0] tm200;
reg signed [15:0] tm204;
reg signed [15:0] tm216;
reg signed [15:0] tm223;
reg signed [15:0] tm217;
reg signed [15:0] tm224;
wire signed [15:0] a168;
wire signed [15:0] a170;
wire signed [15:0] a171;
wire signed [15:0] a172;
reg signed [15:0] tm218;
reg signed [15:0] tm225;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
reg signed [15:0] tm219;
reg signed [15:0] tm226;
assign a173 = X0;
assign a162 = a173;
assign a176 = X1;
assign a166 = a176;
assign a177 = X2;
assign a178 = X3;
assign a167 = tm14;
assign a169 = tm15;
assign Y0 = tm219;
assign Y1 = tm226;
D10_83252 instD10inst0_83252(.addr(i3[2:0]), .out(tm14), .clk(clk));
D12_83272 instD12inst0_83272(.addr(i3[2:0]), .out(tm15), .clk(clk));
multfix #(16, 2) m83171(.a(tm47), .b(tm200), .clk(clk), .q_sc(a168), .q_unsc(), .rst(reset));
multfix #(16, 2) m83193(.a(tm48), .b(tm204), .clk(clk), .q_sc(a170), .q_unsc(), .rst(reset));
multfix #(16, 2) m83211(.a(tm48), .b(tm200), .clk(clk), .q_sc(a171), .q_unsc(), .rst(reset));
multfix #(16, 2) m83222(.a(tm47), .b(tm204), .clk(clk), .q_sc(a172), .q_unsc(), .rst(reset));
subfxp #(16, 1) sub83200(.a(a168), .b(a170), .clk(clk), .q(Y2)); // 6
addfxp #(16, 1) add83229(.a(a171), .b(a172), .clk(clk), .q(Y3)); // 6
always @(posedge clk) begin
if (reset == 1) begin
tm47 <= 0;
tm200 <= 0;
tm48 <= 0;
tm204 <= 0;
tm48 <= 0;
tm200 <= 0;
tm47 <= 0;
tm204 <= 0;
end
else begin
i3 <= i3_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm197 <= a177;
tm201 <= a178;
tm213 <= a162;
tm220 <= a166;
tm198 <= tm197;
tm202 <= tm201;
tm214 <= tm213;
tm221 <= tm220;
tm199 <= tm198;
tm203 <= tm202;
tm215 <= tm214;
tm222 <= tm221;
tm47 <= a167;
tm48 <= a169;
tm200 <= tm199;
tm204 <= tm203;
tm216 <= tm215;
tm223 <= tm222;
tm217 <= tm216;
tm224 <= tm223;
tm218 <= tm217;
tm225 <= tm224;
tm219 <= tm218;
tm226 <= tm225;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock83277(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_85162(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a129;
wire signed [15:0] a130;
wire signed [15:0] a131;
wire signed [15:0] a132;
wire signed [15:0] t69;
wire signed [15:0] t70;
wire signed [15:0] t71;
wire signed [15:0] t72;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a129 = X0;
assign a130 = X2;
assign a131 = X1;
assign a132 = X3;
assign Y0 = t69;
assign Y1 = t70;
assign Y2 = t71;
assign Y3 = t72;
addfxp #(16, 1) add83289(.a(a129), .b(a130), .clk(clk), .q(t69)); // 0
addfxp #(16, 1) add83304(.a(a131), .b(a132), .clk(clk), .q(t70)); // 0
subfxp #(16, 1) sub83319(.a(a129), .b(a130), .clk(clk), .q(t71)); // 0
subfxp #(16, 1) sub83334(.a(a131), .b(a132), .clk(clk), .q(t72)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 36
// Gap: 16
module rc83359(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm83357 instPerm85163(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet83357(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [3:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
4'd0: control <= 1'b1;
4'd1: control <= 1'b1;
4'd2: control <= 1'b1;
4'd3: control <= 1'b1;
4'd4: control <= 1'b1;
4'd5: control <= 1'b1;
4'd6: control <= 1'b1;
4'd7: control <= 1'b1;
4'd8: control <= 1'b0;
4'd9: control <= 1'b0;
4'd10: control <= 1'b0;
4'd11: control <= 1'b0;
4'd12: control <= 1'b0;
4'd13: control <= 1'b0;
4'd14: control <= 1'b0;
4'd15: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 36
// Gap: 16
module perm83357(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 16;
parameter addrbits = 4;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm16;
assign tm16 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_85168(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85169(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
nextReg #(15, 4) nextReg_85180(.X(next), .Y(next2), .reset(reset), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_85181(.X(next2), .Y(next3), .clk(clk));
nextReg #(16, 4) nextReg_85184(.X(next3), .Y(next4), .reset(reset), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85185(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(15, 1) shiftFIFO_85188(.X(tm16), .Y(tm16_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_85191(.X(tm16_d), .Y(tm16_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 4) shiftFIFO_85196(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm16_d, s1rdloc})
{1'd0, 4'd0}: s1rd0 <= 8;
{1'd0, 4'd1}: s1rd0 <= 9;
{1'd0, 4'd2}: s1rd0 <= 10;
{1'd0, 4'd3}: s1rd0 <= 11;
{1'd0, 4'd4}: s1rd0 <= 12;
{1'd0, 4'd5}: s1rd0 <= 13;
{1'd0, 4'd6}: s1rd0 <= 14;
{1'd0, 4'd7}: s1rd0 <= 15;
{1'd0, 4'd8}: s1rd0 <= 0;
{1'd0, 4'd9}: s1rd0 <= 1;
{1'd0, 4'd10}: s1rd0 <= 2;
{1'd0, 4'd11}: s1rd0 <= 3;
{1'd0, 4'd12}: s1rd0 <= 4;
{1'd0, 4'd13}: s1rd0 <= 5;
{1'd0, 4'd14}: s1rd0 <= 6;
{1'd0, 4'd15}: s1rd0 <= 7;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm16_d, s1rdloc})
{1'd0, 4'd0}: s1rd1 <= 0;
{1'd0, 4'd1}: s1rd1 <= 1;
{1'd0, 4'd2}: s1rd1 <= 2;
{1'd0, 4'd3}: s1rd1 <= 3;
{1'd0, 4'd4}: s1rd1 <= 4;
{1'd0, 4'd5}: s1rd1 <= 5;
{1'd0, 4'd6}: s1rd1 <= 6;
{1'd0, 4'd7}: s1rd1 <= 7;
{1'd0, 4'd8}: s1rd1 <= 8;
{1'd0, 4'd9}: s1rd1 <= 9;
{1'd0, 4'd10}: s1rd1 <= 10;
{1'd0, 4'd11}: s1rd1 <= 11;
{1'd0, 4'd12}: s1rd1 <= 12;
{1'd0, 4'd13}: s1rd1 <= 13;
{1'd0, 4'd14}: s1rd1 <= 14;
{1'd0, 4'd15}: s1rd1 <= 15;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet83357 sw(tm16_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm16_dd, writeCycle})
{1'd0, 4'd0}: s2wr0 <= 8;
{1'd0, 4'd1}: s2wr0 <= 9;
{1'd0, 4'd2}: s2wr0 <= 10;
{1'd0, 4'd3}: s2wr0 <= 11;
{1'd0, 4'd4}: s2wr0 <= 12;
{1'd0, 4'd5}: s2wr0 <= 13;
{1'd0, 4'd6}: s2wr0 <= 14;
{1'd0, 4'd7}: s2wr0 <= 15;
{1'd0, 4'd8}: s2wr0 <= 0;
{1'd0, 4'd9}: s2wr0 <= 1;
{1'd0, 4'd10}: s2wr0 <= 2;
{1'd0, 4'd11}: s2wr0 <= 3;
{1'd0, 4'd12}: s2wr0 <= 4;
{1'd0, 4'd13}: s2wr0 <= 5;
{1'd0, 4'd14}: s2wr0 <= 6;
{1'd0, 4'd15}: s2wr0 <= 7;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm16_dd, writeCycle})
{1'd0, 4'd0}: s2wr1 <= 0;
{1'd0, 4'd1}: s2wr1 <= 1;
{1'd0, 4'd2}: s2wr1 <= 2;
{1'd0, 4'd3}: s2wr1 <= 3;
{1'd0, 4'd4}: s2wr1 <= 4;
{1'd0, 4'd5}: s2wr1 <= 5;
{1'd0, 4'd6}: s2wr1 <= 6;
{1'd0, 4'd7}: s2wr1 <= 7;
{1'd0, 4'd8}: s2wr1 <= 8;
{1'd0, 4'd9}: s2wr1 <= 9;
{1'd0, 4'd10}: s2wr1 <= 10;
{1'd0, 4'd11}: s2wr1 <= 11;
{1'd0, 4'd12}: s2wr1 <= 12;
{1'd0, 4'd13}: s2wr1 <= 13;
{1'd0, 4'd14}: s2wr1 <= 14;
{1'd0, 4'd15}: s2wr1 <= 15;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 16
module DirSum_83596(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [3:0] i2;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i2 <= 0;
end
else begin
if (next == 1)
i2 <= 0;
else if (i2 == 15)
i2 <= 0;
else
i2 <= i2 + 1;
end
end
codeBlock83362 codeBlockIsnt85201(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i2_in(i2),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D6_83558(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [3:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h3ec5;
2: out3 <= 16'h3b21;
3: out3 <= 16'h3537;
4: out3 <= 16'h2d41;
5: out3 <= 16'h238e;
6: out3 <= 16'h187e;
7: out3 <= 16'hc7c;
8: out3 <= 16'h0;
9: out3 <= 16'hf384;
10: out3 <= 16'he782;
11: out3 <= 16'hdc72;
12: out3 <= 16'hd2bf;
13: out3 <= 16'hcac9;
14: out3 <= 16'hc4df;
15: out3 <= 16'hc13b;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D8_83594(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [3:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'hf384;
2: out3 <= 16'he782;
3: out3 <= 16'hdc72;
4: out3 <= 16'hd2bf;
5: out3 <= 16'hcac9;
6: out3 <= 16'hc4df;
7: out3 <= 16'hc13b;
8: out3 <= 16'hc000;
9: out3 <= 16'hc13b;
10: out3 <= 16'hc4df;
11: out3 <= 16'hcac9;
12: out3 <= 16'hd2bf;
13: out3 <= 16'hdc72;
14: out3 <= 16'he782;
15: out3 <= 16'hf384;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock83362(clk, reset, next_in, next_out,
i2_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [3:0] i2_in;
reg [3:0] i2;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(7, 1) shiftFIFO_85204(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a113;
wire signed [15:0] a102;
wire signed [15:0] a116;
wire signed [15:0] a106;
wire signed [15:0] a117;
wire signed [15:0] a118;
reg signed [15:0] tm227;
reg signed [15:0] tm231;
reg signed [15:0] tm243;
reg signed [15:0] tm250;
reg signed [15:0] tm228;
reg signed [15:0] tm232;
reg signed [15:0] tm244;
reg signed [15:0] tm251;
wire signed [15:0] tm19;
wire signed [15:0] a107;
wire signed [15:0] tm20;
wire signed [15:0] a109;
reg signed [15:0] tm229;
reg signed [15:0] tm233;
reg signed [15:0] tm245;
reg signed [15:0] tm252;
reg signed [15:0] tm55;
reg signed [15:0] tm56;
reg signed [15:0] tm230;
reg signed [15:0] tm234;
reg signed [15:0] tm246;
reg signed [15:0] tm253;
reg signed [15:0] tm247;
reg signed [15:0] tm254;
wire signed [15:0] a108;
wire signed [15:0] a110;
wire signed [15:0] a111;
wire signed [15:0] a112;
reg signed [15:0] tm248;
reg signed [15:0] tm255;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
reg signed [15:0] tm249;
reg signed [15:0] tm256;
assign a113 = X0;
assign a102 = a113;
assign a116 = X1;
assign a106 = a116;
assign a117 = X2;
assign a118 = X3;
assign a107 = tm19;
assign a109 = tm20;
assign Y0 = tm249;
assign Y1 = tm256;
D6_83558 instD6inst0_83558(.addr(i2[3:0]), .out(tm19), .clk(clk));
D8_83594 instD8inst0_83594(.addr(i2[3:0]), .out(tm20), .clk(clk));
multfix #(16, 2) m83461(.a(tm55), .b(tm230), .clk(clk), .q_sc(a108), .q_unsc(), .rst(reset));
multfix #(16, 2) m83483(.a(tm56), .b(tm234), .clk(clk), .q_sc(a110), .q_unsc(), .rst(reset));
multfix #(16, 2) m83501(.a(tm56), .b(tm230), .clk(clk), .q_sc(a111), .q_unsc(), .rst(reset));
multfix #(16, 2) m83512(.a(tm55), .b(tm234), .clk(clk), .q_sc(a112), .q_unsc(), .rst(reset));
subfxp #(16, 1) sub83490(.a(a108), .b(a110), .clk(clk), .q(Y2)); // 6
addfxp #(16, 1) add83519(.a(a111), .b(a112), .clk(clk), .q(Y3)); // 6
always @(posedge clk) begin
if (reset == 1) begin
tm55 <= 0;
tm230 <= 0;
tm56 <= 0;
tm234 <= 0;
tm56 <= 0;
tm230 <= 0;
tm55 <= 0;
tm234 <= 0;
end
else begin
i2 <= i2_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm227 <= a117;
tm231 <= a118;
tm243 <= a102;
tm250 <= a106;
tm228 <= tm227;
tm232 <= tm231;
tm244 <= tm243;
tm251 <= tm250;
tm229 <= tm228;
tm233 <= tm232;
tm245 <= tm244;
tm252 <= tm251;
tm55 <= a107;
tm56 <= a109;
tm230 <= tm229;
tm234 <= tm233;
tm246 <= tm245;
tm253 <= tm252;
tm247 <= tm246;
tm254 <= tm253;
tm248 <= tm247;
tm255 <= tm254;
tm249 <= tm248;
tm256 <= tm255;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock83599(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_85207(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a69;
wire signed [15:0] a70;
wire signed [15:0] a71;
wire signed [15:0] a72;
wire signed [15:0] t45;
wire signed [15:0] t46;
wire signed [15:0] t47;
wire signed [15:0] t48;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a69 = X0;
assign a70 = X2;
assign a71 = X1;
assign a72 = X3;
assign Y0 = t45;
assign Y1 = t46;
assign Y2 = t47;
assign Y3 = t48;
addfxp #(16, 1) add83611(.a(a69), .b(a70), .clk(clk), .q(t45)); // 0
addfxp #(16, 1) add83626(.a(a71), .b(a72), .clk(clk), .q(t46)); // 0
subfxp #(16, 1) sub83641(.a(a69), .b(a70), .clk(clk), .q(t47)); // 0
subfxp #(16, 1) sub83656(.a(a71), .b(a72), .clk(clk), .q(t48)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 68
// Gap: 32
module rc83681(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm83679 instPerm85208(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet83679(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [4:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
5'd0: control <= 1'b1;
5'd1: control <= 1'b1;
5'd2: control <= 1'b1;
5'd3: control <= 1'b1;
5'd4: control <= 1'b1;
5'd5: control <= 1'b1;
5'd6: control <= 1'b1;
5'd7: control <= 1'b1;
5'd8: control <= 1'b1;
5'd9: control <= 1'b1;
5'd10: control <= 1'b1;
5'd11: control <= 1'b1;
5'd12: control <= 1'b1;
5'd13: control <= 1'b1;
5'd14: control <= 1'b1;
5'd15: control <= 1'b1;
5'd16: control <= 1'b0;
5'd17: control <= 1'b0;
5'd18: control <= 1'b0;
5'd19: control <= 1'b0;
5'd20: control <= 1'b0;
5'd21: control <= 1'b0;
5'd22: control <= 1'b0;
5'd23: control <= 1'b0;
5'd24: control <= 1'b0;
5'd25: control <= 1'b0;
5'd26: control <= 1'b0;
5'd27: control <= 1'b0;
5'd28: control <= 1'b0;
5'd29: control <= 1'b0;
5'd30: control <= 1'b0;
5'd31: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 68
// Gap: 32
module perm83679(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 32;
parameter addrbits = 5;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm21;
assign tm21 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_85213(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85214(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
nextReg #(31, 5) nextReg_85225(.X(next), .Y(next2), .reset(reset), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_85226(.X(next2), .Y(next3), .clk(clk));
nextReg #(32, 5) nextReg_85229(.X(next3), .Y(next4), .reset(reset), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85230(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(31, 1) shiftFIFO_85233(.X(tm21), .Y(tm21_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_85236(.X(tm21_d), .Y(tm21_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 5) shiftFIFO_85241(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm21_d, s1rdloc})
{1'd0, 5'd0}: s1rd0 <= 16;
{1'd0, 5'd1}: s1rd0 <= 17;
{1'd0, 5'd2}: s1rd0 <= 18;
{1'd0, 5'd3}: s1rd0 <= 19;
{1'd0, 5'd4}: s1rd0 <= 20;
{1'd0, 5'd5}: s1rd0 <= 21;
{1'd0, 5'd6}: s1rd0 <= 22;
{1'd0, 5'd7}: s1rd0 <= 23;
{1'd0, 5'd8}: s1rd0 <= 24;
{1'd0, 5'd9}: s1rd0 <= 25;
{1'd0, 5'd10}: s1rd0 <= 26;
{1'd0, 5'd11}: s1rd0 <= 27;
{1'd0, 5'd12}: s1rd0 <= 28;
{1'd0, 5'd13}: s1rd0 <= 29;
{1'd0, 5'd14}: s1rd0 <= 30;
{1'd0, 5'd15}: s1rd0 <= 31;
{1'd0, 5'd16}: s1rd0 <= 0;
{1'd0, 5'd17}: s1rd0 <= 1;
{1'd0, 5'd18}: s1rd0 <= 2;
{1'd0, 5'd19}: s1rd0 <= 3;
{1'd0, 5'd20}: s1rd0 <= 4;
{1'd0, 5'd21}: s1rd0 <= 5;
{1'd0, 5'd22}: s1rd0 <= 6;
{1'd0, 5'd23}: s1rd0 <= 7;
{1'd0, 5'd24}: s1rd0 <= 8;
{1'd0, 5'd25}: s1rd0 <= 9;
{1'd0, 5'd26}: s1rd0 <= 10;
{1'd0, 5'd27}: s1rd0 <= 11;
{1'd0, 5'd28}: s1rd0 <= 12;
{1'd0, 5'd29}: s1rd0 <= 13;
{1'd0, 5'd30}: s1rd0 <= 14;
{1'd0, 5'd31}: s1rd0 <= 15;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm21_d, s1rdloc})
{1'd0, 5'd0}: s1rd1 <= 0;
{1'd0, 5'd1}: s1rd1 <= 1;
{1'd0, 5'd2}: s1rd1 <= 2;
{1'd0, 5'd3}: s1rd1 <= 3;
{1'd0, 5'd4}: s1rd1 <= 4;
{1'd0, 5'd5}: s1rd1 <= 5;
{1'd0, 5'd6}: s1rd1 <= 6;
{1'd0, 5'd7}: s1rd1 <= 7;
{1'd0, 5'd8}: s1rd1 <= 8;
{1'd0, 5'd9}: s1rd1 <= 9;
{1'd0, 5'd10}: s1rd1 <= 10;
{1'd0, 5'd11}: s1rd1 <= 11;
{1'd0, 5'd12}: s1rd1 <= 12;
{1'd0, 5'd13}: s1rd1 <= 13;
{1'd0, 5'd14}: s1rd1 <= 14;
{1'd0, 5'd15}: s1rd1 <= 15;
{1'd0, 5'd16}: s1rd1 <= 16;
{1'd0, 5'd17}: s1rd1 <= 17;
{1'd0, 5'd18}: s1rd1 <= 18;
{1'd0, 5'd19}: s1rd1 <= 19;
{1'd0, 5'd20}: s1rd1 <= 20;
{1'd0, 5'd21}: s1rd1 <= 21;
{1'd0, 5'd22}: s1rd1 <= 22;
{1'd0, 5'd23}: s1rd1 <= 23;
{1'd0, 5'd24}: s1rd1 <= 24;
{1'd0, 5'd25}: s1rd1 <= 25;
{1'd0, 5'd26}: s1rd1 <= 26;
{1'd0, 5'd27}: s1rd1 <= 27;
{1'd0, 5'd28}: s1rd1 <= 28;
{1'd0, 5'd29}: s1rd1 <= 29;
{1'd0, 5'd30}: s1rd1 <= 30;
{1'd0, 5'd31}: s1rd1 <= 31;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet83679 sw(tm21_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm21_dd, writeCycle})
{1'd0, 5'd0}: s2wr0 <= 16;
{1'd0, 5'd1}: s2wr0 <= 17;
{1'd0, 5'd2}: s2wr0 <= 18;
{1'd0, 5'd3}: s2wr0 <= 19;
{1'd0, 5'd4}: s2wr0 <= 20;
{1'd0, 5'd5}: s2wr0 <= 21;
{1'd0, 5'd6}: s2wr0 <= 22;
{1'd0, 5'd7}: s2wr0 <= 23;
{1'd0, 5'd8}: s2wr0 <= 24;
{1'd0, 5'd9}: s2wr0 <= 25;
{1'd0, 5'd10}: s2wr0 <= 26;
{1'd0, 5'd11}: s2wr0 <= 27;
{1'd0, 5'd12}: s2wr0 <= 28;
{1'd0, 5'd13}: s2wr0 <= 29;
{1'd0, 5'd14}: s2wr0 <= 30;
{1'd0, 5'd15}: s2wr0 <= 31;
{1'd0, 5'd16}: s2wr0 <= 0;
{1'd0, 5'd17}: s2wr0 <= 1;
{1'd0, 5'd18}: s2wr0 <= 2;
{1'd0, 5'd19}: s2wr0 <= 3;
{1'd0, 5'd20}: s2wr0 <= 4;
{1'd0, 5'd21}: s2wr0 <= 5;
{1'd0, 5'd22}: s2wr0 <= 6;
{1'd0, 5'd23}: s2wr0 <= 7;
{1'd0, 5'd24}: s2wr0 <= 8;
{1'd0, 5'd25}: s2wr0 <= 9;
{1'd0, 5'd26}: s2wr0 <= 10;
{1'd0, 5'd27}: s2wr0 <= 11;
{1'd0, 5'd28}: s2wr0 <= 12;
{1'd0, 5'd29}: s2wr0 <= 13;
{1'd0, 5'd30}: s2wr0 <= 14;
{1'd0, 5'd31}: s2wr0 <= 15;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm21_dd, writeCycle})
{1'd0, 5'd0}: s2wr1 <= 0;
{1'd0, 5'd1}: s2wr1 <= 1;
{1'd0, 5'd2}: s2wr1 <= 2;
{1'd0, 5'd3}: s2wr1 <= 3;
{1'd0, 5'd4}: s2wr1 <= 4;
{1'd0, 5'd5}: s2wr1 <= 5;
{1'd0, 5'd6}: s2wr1 <= 6;
{1'd0, 5'd7}: s2wr1 <= 7;
{1'd0, 5'd8}: s2wr1 <= 8;
{1'd0, 5'd9}: s2wr1 <= 9;
{1'd0, 5'd10}: s2wr1 <= 10;
{1'd0, 5'd11}: s2wr1 <= 11;
{1'd0, 5'd12}: s2wr1 <= 12;
{1'd0, 5'd13}: s2wr1 <= 13;
{1'd0, 5'd14}: s2wr1 <= 14;
{1'd0, 5'd15}: s2wr1 <= 15;
{1'd0, 5'd16}: s2wr1 <= 16;
{1'd0, 5'd17}: s2wr1 <= 17;
{1'd0, 5'd18}: s2wr1 <= 18;
{1'd0, 5'd19}: s2wr1 <= 19;
{1'd0, 5'd20}: s2wr1 <= 20;
{1'd0, 5'd21}: s2wr1 <= 21;
{1'd0, 5'd22}: s2wr1 <= 22;
{1'd0, 5'd23}: s2wr1 <= 23;
{1'd0, 5'd24}: s2wr1 <= 24;
{1'd0, 5'd25}: s2wr1 <= 25;
{1'd0, 5'd26}: s2wr1 <= 26;
{1'd0, 5'd27}: s2wr1 <= 27;
{1'd0, 5'd28}: s2wr1 <= 28;
{1'd0, 5'd29}: s2wr1 <= 29;
{1'd0, 5'd30}: s2wr1 <= 30;
{1'd0, 5'd31}: s2wr1 <= 31;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 32
module DirSum_83981(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [4:0] i1;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i1 <= 0;
end
else begin
if (next == 1)
i1 <= 0;
else if (i1 == 31)
i1 <= 0;
else
i1 <= i1 + 1;
end
end
codeBlock83683 codeBlockIsnt85246(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i1_in(i1),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D2_83911(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [4:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h3fb1;
2: out3 <= 16'h3ec5;
3: out3 <= 16'h3d3f;
4: out3 <= 16'h3b21;
5: out3 <= 16'h3871;
6: out3 <= 16'h3537;
7: out3 <= 16'h3179;
8: out3 <= 16'h2d41;
9: out3 <= 16'h289a;
10: out3 <= 16'h238e;
11: out3 <= 16'h1e2b;
12: out3 <= 16'h187e;
13: out3 <= 16'h1294;
14: out3 <= 16'hc7c;
15: out3 <= 16'h646;
16: out3 <= 16'h0;
17: out3 <= 16'hf9ba;
18: out3 <= 16'hf384;
19: out3 <= 16'hed6c;
20: out3 <= 16'he782;
21: out3 <= 16'he1d5;
22: out3 <= 16'hdc72;
23: out3 <= 16'hd766;
24: out3 <= 16'hd2bf;
25: out3 <= 16'hce87;
26: out3 <= 16'hcac9;
27: out3 <= 16'hc78f;
28: out3 <= 16'hc4df;
29: out3 <= 16'hc2c1;
30: out3 <= 16'hc13b;
31: out3 <= 16'hc04f;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D4_83979(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [4:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'hf9ba;
2: out3 <= 16'hf384;
3: out3 <= 16'hed6c;
4: out3 <= 16'he782;
5: out3 <= 16'he1d5;
6: out3 <= 16'hdc72;
7: out3 <= 16'hd766;
8: out3 <= 16'hd2bf;
9: out3 <= 16'hce87;
10: out3 <= 16'hcac9;
11: out3 <= 16'hc78f;
12: out3 <= 16'hc4df;
13: out3 <= 16'hc2c1;
14: out3 <= 16'hc13b;
15: out3 <= 16'hc04f;
16: out3 <= 16'hc000;
17: out3 <= 16'hc04f;
18: out3 <= 16'hc13b;
19: out3 <= 16'hc2c1;
20: out3 <= 16'hc4df;
21: out3 <= 16'hc78f;
22: out3 <= 16'hcac9;
23: out3 <= 16'hce87;
24: out3 <= 16'hd2bf;
25: out3 <= 16'hd766;
26: out3 <= 16'hdc72;
27: out3 <= 16'he1d5;
28: out3 <= 16'he782;
29: out3 <= 16'hed6c;
30: out3 <= 16'hf384;
31: out3 <= 16'hf9ba;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock83683(clk, reset, next_in, next_out,
i1_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [4:0] i1_in;
reg [4:0] i1;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(7, 1) shiftFIFO_85249(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a53;
wire signed [15:0] a42;
wire signed [15:0] a56;
wire signed [15:0] a46;
wire signed [15:0] a57;
wire signed [15:0] a58;
reg signed [15:0] tm257;
reg signed [15:0] tm261;
reg signed [15:0] tm273;
reg signed [15:0] tm280;
reg signed [15:0] tm258;
reg signed [15:0] tm262;
reg signed [15:0] tm274;
reg signed [15:0] tm281;
wire signed [15:0] tm24;
wire signed [15:0] a47;
wire signed [15:0] tm25;
wire signed [15:0] a49;
reg signed [15:0] tm259;
reg signed [15:0] tm263;
reg signed [15:0] tm275;
reg signed [15:0] tm282;
reg signed [15:0] tm63;
reg signed [15:0] tm64;
reg signed [15:0] tm260;
reg signed [15:0] tm264;
reg signed [15:0] tm276;
reg signed [15:0] tm283;
reg signed [15:0] tm277;
reg signed [15:0] tm284;
wire signed [15:0] a48;
wire signed [15:0] a50;
wire signed [15:0] a51;
wire signed [15:0] a52;
reg signed [15:0] tm278;
reg signed [15:0] tm285;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
reg signed [15:0] tm279;
reg signed [15:0] tm286;
assign a53 = X0;
assign a42 = a53;
assign a56 = X1;
assign a46 = a56;
assign a57 = X2;
assign a58 = X3;
assign a47 = tm24;
assign a49 = tm25;
assign Y0 = tm279;
assign Y1 = tm286;
D2_83911 instD2inst0_83911(.addr(i1[4:0]), .out(tm24), .clk(clk));
D4_83979 instD4inst0_83979(.addr(i1[4:0]), .out(tm25), .clk(clk));
multfix #(16, 2) m83782(.a(tm63), .b(tm260), .clk(clk), .q_sc(a48), .q_unsc(), .rst(reset));
multfix #(16, 2) m83804(.a(tm64), .b(tm264), .clk(clk), .q_sc(a50), .q_unsc(), .rst(reset));
multfix #(16, 2) m83822(.a(tm64), .b(tm260), .clk(clk), .q_sc(a51), .q_unsc(), .rst(reset));
multfix #(16, 2) m83833(.a(tm63), .b(tm264), .clk(clk), .q_sc(a52), .q_unsc(), .rst(reset));
subfxp #(16, 1) sub83811(.a(a48), .b(a50), .clk(clk), .q(Y2)); // 6
addfxp #(16, 1) add83840(.a(a51), .b(a52), .clk(clk), .q(Y3)); // 6
always @(posedge clk) begin
if (reset == 1) begin
tm63 <= 0;
tm260 <= 0;
tm64 <= 0;
tm264 <= 0;
tm64 <= 0;
tm260 <= 0;
tm63 <= 0;
tm264 <= 0;
end
else begin
i1 <= i1_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm257 <= a57;
tm261 <= a58;
tm273 <= a42;
tm280 <= a46;
tm258 <= tm257;
tm262 <= tm261;
tm274 <= tm273;
tm281 <= tm280;
tm259 <= tm258;
tm263 <= tm262;
tm275 <= tm274;
tm282 <= tm281;
tm63 <= a47;
tm64 <= a49;
tm260 <= tm259;
tm264 <= tm263;
tm276 <= tm275;
tm283 <= tm282;
tm277 <= tm276;
tm284 <= tm283;
tm278 <= tm277;
tm285 <= tm284;
tm279 <= tm278;
tm286 <= tm285;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock83984(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_85252(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a9;
wire signed [15:0] a10;
wire signed [15:0] a11;
wire signed [15:0] a12;
wire signed [15:0] t21;
wire signed [15:0] t22;
wire signed [15:0] t23;
wire signed [15:0] t24;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a9 = X0;
assign a10 = X2;
assign a11 = X1;
assign a12 = X3;
assign Y0 = t21;
assign Y1 = t22;
assign Y2 = t23;
assign Y3 = t24;
addfxp #(16, 1) add83996(.a(a9), .b(a10), .clk(clk), .q(t21)); // 0
addfxp #(16, 1) add84011(.a(a11), .b(a12), .clk(clk), .q(t22)); // 0
subfxp #(16, 1) sub84026(.a(a9), .b(a10), .clk(clk), .q(t23)); // 0
subfxp #(16, 1) sub84041(.a(a11), .b(a12), .clk(clk), .q(t24)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 68
// Gap: 32
module rc84066(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm84064 instPerm85253(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet84064(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [4:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
5'd0: control <= 1'b1;
5'd1: control <= 1'b1;
5'd2: control <= 1'b1;
5'd3: control <= 1'b1;
5'd4: control <= 1'b1;
5'd5: control <= 1'b1;
5'd6: control <= 1'b1;
5'd7: control <= 1'b1;
5'd8: control <= 1'b1;
5'd9: control <= 1'b1;
5'd10: control <= 1'b1;
5'd11: control <= 1'b1;
5'd12: control <= 1'b1;
5'd13: control <= 1'b1;
5'd14: control <= 1'b1;
5'd15: control <= 1'b1;
5'd16: control <= 1'b0;
5'd17: control <= 1'b0;
5'd18: control <= 1'b0;
5'd19: control <= 1'b0;
5'd20: control <= 1'b0;
5'd21: control <= 1'b0;
5'd22: control <= 1'b0;
5'd23: control <= 1'b0;
5'd24: control <= 1'b0;
5'd25: control <= 1'b0;
5'd26: control <= 1'b0;
5'd27: control <= 1'b0;
5'd28: control <= 1'b0;
5'd29: control <= 1'b0;
5'd30: control <= 1'b0;
5'd31: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 68
// Gap: 32
module perm84064(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 32;
parameter addrbits = 5;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm26;
assign tm26 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_85258(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85259(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
nextReg #(31, 5) nextReg_85270(.X(next), .Y(next2), .reset(reset), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_85271(.X(next2), .Y(next3), .clk(clk));
nextReg #(32, 5) nextReg_85274(.X(next3), .Y(next4), .reset(reset), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85275(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(31, 1) shiftFIFO_85278(.X(tm26), .Y(tm26_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_85281(.X(tm26_d), .Y(tm26_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 5) shiftFIFO_85286(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm26_d, s1rdloc})
{1'd0, 5'd0}: s1rd0 <= 1;
{1'd0, 5'd1}: s1rd0 <= 3;
{1'd0, 5'd2}: s1rd0 <= 5;
{1'd0, 5'd3}: s1rd0 <= 7;
{1'd0, 5'd4}: s1rd0 <= 9;
{1'd0, 5'd5}: s1rd0 <= 11;
{1'd0, 5'd6}: s1rd0 <= 13;
{1'd0, 5'd7}: s1rd0 <= 15;
{1'd0, 5'd8}: s1rd0 <= 17;
{1'd0, 5'd9}: s1rd0 <= 19;
{1'd0, 5'd10}: s1rd0 <= 21;
{1'd0, 5'd11}: s1rd0 <= 23;
{1'd0, 5'd12}: s1rd0 <= 25;
{1'd0, 5'd13}: s1rd0 <= 27;
{1'd0, 5'd14}: s1rd0 <= 29;
{1'd0, 5'd15}: s1rd0 <= 31;
{1'd0, 5'd16}: s1rd0 <= 0;
{1'd0, 5'd17}: s1rd0 <= 2;
{1'd0, 5'd18}: s1rd0 <= 4;
{1'd0, 5'd19}: s1rd0 <= 6;
{1'd0, 5'd20}: s1rd0 <= 8;
{1'd0, 5'd21}: s1rd0 <= 10;
{1'd0, 5'd22}: s1rd0 <= 12;
{1'd0, 5'd23}: s1rd0 <= 14;
{1'd0, 5'd24}: s1rd0 <= 16;
{1'd0, 5'd25}: s1rd0 <= 18;
{1'd0, 5'd26}: s1rd0 <= 20;
{1'd0, 5'd27}: s1rd0 <= 22;
{1'd0, 5'd28}: s1rd0 <= 24;
{1'd0, 5'd29}: s1rd0 <= 26;
{1'd0, 5'd30}: s1rd0 <= 28;
{1'd0, 5'd31}: s1rd0 <= 30;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm26_d, s1rdloc})
{1'd0, 5'd0}: s1rd1 <= 0;
{1'd0, 5'd1}: s1rd1 <= 2;
{1'd0, 5'd2}: s1rd1 <= 4;
{1'd0, 5'd3}: s1rd1 <= 6;
{1'd0, 5'd4}: s1rd1 <= 8;
{1'd0, 5'd5}: s1rd1 <= 10;
{1'd0, 5'd6}: s1rd1 <= 12;
{1'd0, 5'd7}: s1rd1 <= 14;
{1'd0, 5'd8}: s1rd1 <= 16;
{1'd0, 5'd9}: s1rd1 <= 18;
{1'd0, 5'd10}: s1rd1 <= 20;
{1'd0, 5'd11}: s1rd1 <= 22;
{1'd0, 5'd12}: s1rd1 <= 24;
{1'd0, 5'd13}: s1rd1 <= 26;
{1'd0, 5'd14}: s1rd1 <= 28;
{1'd0, 5'd15}: s1rd1 <= 30;
{1'd0, 5'd16}: s1rd1 <= 1;
{1'd0, 5'd17}: s1rd1 <= 3;
{1'd0, 5'd18}: s1rd1 <= 5;
{1'd0, 5'd19}: s1rd1 <= 7;
{1'd0, 5'd20}: s1rd1 <= 9;
{1'd0, 5'd21}: s1rd1 <= 11;
{1'd0, 5'd22}: s1rd1 <= 13;
{1'd0, 5'd23}: s1rd1 <= 15;
{1'd0, 5'd24}: s1rd1 <= 17;
{1'd0, 5'd25}: s1rd1 <= 19;
{1'd0, 5'd26}: s1rd1 <= 21;
{1'd0, 5'd27}: s1rd1 <= 23;
{1'd0, 5'd28}: s1rd1 <= 25;
{1'd0, 5'd29}: s1rd1 <= 27;
{1'd0, 5'd30}: s1rd1 <= 29;
{1'd0, 5'd31}: s1rd1 <= 31;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet84064 sw(tm26_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm26_dd, writeCycle})
{1'd0, 5'd0}: s2wr0 <= 16;
{1'd0, 5'd1}: s2wr0 <= 17;
{1'd0, 5'd2}: s2wr0 <= 18;
{1'd0, 5'd3}: s2wr0 <= 19;
{1'd0, 5'd4}: s2wr0 <= 20;
{1'd0, 5'd5}: s2wr0 <= 21;
{1'd0, 5'd6}: s2wr0 <= 22;
{1'd0, 5'd7}: s2wr0 <= 23;
{1'd0, 5'd8}: s2wr0 <= 24;
{1'd0, 5'd9}: s2wr0 <= 25;
{1'd0, 5'd10}: s2wr0 <= 26;
{1'd0, 5'd11}: s2wr0 <= 27;
{1'd0, 5'd12}: s2wr0 <= 28;
{1'd0, 5'd13}: s2wr0 <= 29;
{1'd0, 5'd14}: s2wr0 <= 30;
{1'd0, 5'd15}: s2wr0 <= 31;
{1'd0, 5'd16}: s2wr0 <= 0;
{1'd0, 5'd17}: s2wr0 <= 1;
{1'd0, 5'd18}: s2wr0 <= 2;
{1'd0, 5'd19}: s2wr0 <= 3;
{1'd0, 5'd20}: s2wr0 <= 4;
{1'd0, 5'd21}: s2wr0 <= 5;
{1'd0, 5'd22}: s2wr0 <= 6;
{1'd0, 5'd23}: s2wr0 <= 7;
{1'd0, 5'd24}: s2wr0 <= 8;
{1'd0, 5'd25}: s2wr0 <= 9;
{1'd0, 5'd26}: s2wr0 <= 10;
{1'd0, 5'd27}: s2wr0 <= 11;
{1'd0, 5'd28}: s2wr0 <= 12;
{1'd0, 5'd29}: s2wr0 <= 13;
{1'd0, 5'd30}: s2wr0 <= 14;
{1'd0, 5'd31}: s2wr0 <= 15;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm26_dd, writeCycle})
{1'd0, 5'd0}: s2wr1 <= 0;
{1'd0, 5'd1}: s2wr1 <= 1;
{1'd0, 5'd2}: s2wr1 <= 2;
{1'd0, 5'd3}: s2wr1 <= 3;
{1'd0, 5'd4}: s2wr1 <= 4;
{1'd0, 5'd5}: s2wr1 <= 5;
{1'd0, 5'd6}: s2wr1 <= 6;
{1'd0, 5'd7}: s2wr1 <= 7;
{1'd0, 5'd8}: s2wr1 <= 8;
{1'd0, 5'd9}: s2wr1 <= 9;
{1'd0, 5'd10}: s2wr1 <= 10;
{1'd0, 5'd11}: s2wr1 <= 11;
{1'd0, 5'd12}: s2wr1 <= 12;
{1'd0, 5'd13}: s2wr1 <= 13;
{1'd0, 5'd14}: s2wr1 <= 14;
{1'd0, 5'd15}: s2wr1 <= 15;
{1'd0, 5'd16}: s2wr1 <= 16;
{1'd0, 5'd17}: s2wr1 <= 17;
{1'd0, 5'd18}: s2wr1 <= 18;
{1'd0, 5'd19}: s2wr1 <= 19;
{1'd0, 5'd20}: s2wr1 <= 20;
{1'd0, 5'd21}: s2wr1 <= 21;
{1'd0, 5'd22}: s2wr1 <= 22;
{1'd0, 5'd23}: s2wr1 <= 23;
{1'd0, 5'd24}: s2wr1 <= 24;
{1'd0, 5'd25}: s2wr1 <= 25;
{1'd0, 5'd26}: s2wr1 <= 26;
{1'd0, 5'd27}: s2wr1 <= 27;
{1'd0, 5'd28}: s2wr1 <= 28;
{1'd0, 5'd29}: s2wr1 <= 29;
{1'd0, 5'd30}: s2wr1 <= 30;
{1'd0, 5'd31}: s2wr1 <= 31;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
module multfix(clk, rst, a, b, q_sc, q_unsc);
parameter WIDTH=35, CYCLES=6;
input signed [WIDTH-1:0] a,b;
output [WIDTH-1:0] q_sc;
output [WIDTH-1:0] q_unsc;
input clk, rst;
reg signed [2*WIDTH-1:0] q[CYCLES-1:0];
wire signed [2*WIDTH-1:0] res;
integer i;
assign res = q[CYCLES-1];
assign q_unsc = res[WIDTH-1:0];
assign q_sc = {res[2*WIDTH-1], res[2*WIDTH-4:WIDTH-2]};
always @(posedge clk) begin
q[0] <= a * b;
for (i = 1; i < CYCLES; i=i+1) begin
q[i] <= q[i-1];
end
end
endmodule
module addfxp(a, b, q, clk);
parameter width = 16, cycles=1;
input signed [width-1:0] a, b;
input clk;
output signed [width-1:0] q;
reg signed [width-1:0] res[cycles-1:0];
assign q = res[cycles-1];
integer i;
always @(posedge clk) begin
res[0] <= a+b;
for (i=1; i < cycles; i = i+1)
res[i] <= res[i-1];
end
endmodule
module subfxp(a, b, q, clk);
parameter width = 16, cycles=1;
input signed [width-1:0] a, b;
input clk;
output signed [width-1:0] q;
reg signed [width-1:0] res[cycles-1:0];
assign q = res[cycles-1];
integer i;
always @(posedge clk) begin
res[0] <= a-b;
for (i=1; i < cycles; i = i+1)
res[i] <= res[i-1];
end
endmodule |
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : dft_top_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-DFT core
//
module dft_top_top(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
wb_ack_o, wb_err_o, wb_dat_o,
wb_clk_i, wb_rst_i, int_o
);
parameter dw = 32;
parameter aw = 32;
input [aw-1:0] wb_adr_i;
input wb_cyc_i;
input [dw-1:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_stb_i;
input wb_we_i;
output wb_ack_o;
output wb_err_o;
output reg [dw-1:0] wb_dat_o;
output int_o;
input wb_clk_i;
input wb_rst_i;
assign wb_ack_o = 1'b1;
assign wb_err_o = 1'b0;
assign int_o = 1'b0;
// Internal registers
reg next;
reg [63:0] dataX [0:31];
reg [63:0] dataY [0:31];
reg [5:0] xSel;
reg [5:0] ySel;
wire [63:0] dataIn, dataOut, dataR_Out;
reg [63:0] data_In_data, data_In_addr, data_Out_addr;
reg data_valid, data_In_write;
wire next_out, next_posedge;
// Implement MD5 I/O memory map interface
// Write side
always @(posedge wb_clk_i)
begin
if(wb_rst_i)
begin
next <= 0;
data_In_write <= 0;
data_In_addr <= 0;
data_In_data[31:0] <= 0;
data_In_data[63:32]<= 0;
end
else if(wb_stb_i & wb_we_i)
case(wb_adr_i[5:2])
0:
next <= wb_dat_i[0];
1:
data_In_write <= wb_dat_i[0];
2:
data_In_addr <= wb_dat_i;
3:
data_In_data[31:0] <= wb_dat_i;
4:
data_In_data[63:32]<= wb_dat_i;
5:
data_Out_addr <= wb_dat_i;
default:
;
endcase
end // always @ (posedge wb_clk_i)
// Implement MD5 I/O memory map interface
// Read side
always @(*)
begin
case(wb_adr_i[5:2])
0:
wb_dat_o = {31'b0, next};
1:
wb_dat_o = {31'b0, data_In_write};
2:
wb_dat_o = data_In_addr;
3:
wb_dat_o = data_In_data[31:0];
4:
wb_dat_o = data_In_data[63:32];
5:
wb_dat_o = data_Out_addr;
6:
wb_dat_o = dataR_Out[31:0];
7:
wb_dat_o = dataR_Out[63:32];
8:
wb_dat_o = {31'b0, data_valid};
default:
wb_dat_o = 32'b0;
endcase
end // always @ (*)
dft_top dft_top(
.clk(wb_clk_i),
.reset(wb_rst_i),
.next(next_posedge),
.next_out(next_out),
.X0(dataIn[15:0]),
.X1(dataIn[31:16]),
.X2(dataIn[47:32]),
.X3(dataIn[63:48]),
.Y0(dataOut[15:0]),
.Y1(dataOut[31:16]),
.Y2(dataOut[47:32]),
.Y3(dataOut[63:48]));
reg data_In_write_r;
always @(posedge wb_clk_i)
begin
data_In_write_r <= data_In_write;
end
wire data_In_write_posedge = data_In_write & ~data_In_write_r;
always @ (posedge wb_clk_i)
begin
if(data_In_write_posedge)
begin
dataX[data_In_addr] <= data_In_data;
end
end
assign dataR_Out=dataY[data_Out_addr];
reg next_r;
always @(posedge wb_clk_i)
begin
next_r <= next;
end
assign next_posedge = next & ~next_r;
always @ (posedge wb_clk_i)
begin
if(next_posedge)
begin
xSel <= 6'h00;
end
else if(xSel<6'b100000)
begin
xSel <= xSel +1;
end
end
assign dataIn = dataX[xSel];
reg next_out_r;
always @(posedge wb_clk_i)
begin
next_out_r <= next_out;
end
wire next_out_posedge = next_out & ~next_out_r;
always @ (posedge wb_clk_i)
begin
if(next_out_posedge)
begin
ySel <= 6'h00;
end
else if(ySel<6'b100000)
begin
ySel <= ySel +1;
dataY[ySel] = dataOut;
end
end
always @ (posedge wb_clk_i)
begin
if(next_posedge)
begin
data_valid <= 0;
end
else if(next_out_posedge)
begin
data_valid <= 1;
end
end
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral IIR Filter Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./iirGen.pl -A 256 0 378 0 179 0 32 0 2 0 0 0 -B 0 -4 22 -68 136 -191 191 -136 68 -22 4 0 -moduleName FIR_filter -fractionalBits 8 -bitWidth 32 -inData inData -inReg -outReg -outData outData -clk clk -reset reset -reset_edge negedge -filterForm 1 -debug -outFile ../outputs/filter_1536037053.v */
/* Warning: zero-valued filter taps have been optimized away. */
module FIR_filter (
inData,
clk,
outData,
reset
);
// Port mode declarations:
input [31:0] inData;
input clk;
output [31:0] outData;
input reset;
//registerIn
reg [31:0] inData_in;
always@(posedge clk or negedge reset) begin
if(~reset) begin
inData_in <= 32'h00000000;
end else begin
inData_in <= inData;
end
end
//registerOut
reg [31:0] outData;
wire [31:0] outData_in;
always@(posedge clk or negedge reset) begin
if(~reset) begin
outData <= 32'h00000000;
end else begin
outData <= outData_in;
end
end
wire [31:0] leftOut, rightOut;
FIR_filter_firBlock_left my_FIR_filter_firBlock_left(
.X(inData_in),
.Y(leftOut),
.clk(clk),
.reset(reset)
);
FIR_filter_firBlock_right my_FIR_filter_firBlock_right(
.X(outData_in),
.Y(rightOut),
.clk(clk),
.reset(reset)
);
assign outData_in = leftOut + rightOut; // adder(32)
//FIR_filter area estimate = 113925.875962894;
endmodule //FIR_filter
module FIR_filter_firBlock_left_MultiplyBlock (
X,
Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8,
Y9,
Y10,
Y11
);
// Port mode declarations:
input signed [31:0] X;
output signed [31:0]
Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8,
Y9,
Y10,
Y11;
wire [31:0] Y [0:10];
assign Y1 = Y[0];
assign Y2 = Y[1];
assign Y3 = Y[2];
assign Y4 = Y[3];
assign Y5 = Y[4];
assign Y6 = Y[5];
assign Y7 = Y[6];
assign Y8 = Y[7];
assign Y9 = Y[8];
assign Y10 = Y[9];
assign Y11 = Y[10];
//Multipliers:
wire signed [39:0]
w1,
w0,
w16,
w17,
w4,
w3,
w8,
w11,
w192,
w191,
w22,
w22_,
w68,
w136,
w136_,
w191_,
w68_,
w4_;
assign w1 = X;
assign w0 = 0;
assign w11 = w3 + w8; //2195.42405790882 = adderArea(3,34)
assign w136 = w17 << 3; //shl(3,39)
assign w136_ = -1 * w136; //1669.85284613971 = negArea(3,39)
assign w16 = w1 << 4; //shl(4,35)
assign w17 = w1 + w16; //2195.42405790882 = adderArea(4,35)
assign w191 = w192 - w1; //2561.32791574853 = subArea(6,39)
assign w191_ = -1 * w191; //1809.56165059559 = negArea(0,39)
assign w192 = w3 << 6; //shl(6,39)
assign w22 = w11 << 1; //shl(1,36)
assign w22_ = -1 * w22; //1623.28324465441 = negArea(1,36)
assign w3 = w4 - w1; //2408.3135227603 = subArea(2,33)
assign w4 = w1 << 2; //shl(2,33)
assign w4_ = -1 * w4; //1437.00483871323 = negArea(2,33)
assign w68 = w17 << 2; //shl(2,38)
assign w68_ = -1 * w68; //1669.85284613971 = negArea(2,38)
assign w8 = w1 << 3; //shl(3,34)
assign Y[0] = w4[39:8]; //BitwidthUsed(0, 25)
assign Y[1] = w22_[39:8]; //BitwidthUsed(0, 28)
assign Y[2] = w68[39:8]; //BitwidthUsed(0, 30)
assign Y[3] = w136_[39:8]; //BitwidthUsed(0, 31)
assign Y[4] = w191[39:8]; //BitwidthUsed(0, 31)
assign Y[5] = w191_[39:8]; //BitwidthUsed(0, 31)
assign Y[6] = w136[39:8]; //BitwidthUsed(0, 31)
assign Y[7] = w68_[39:8]; //BitwidthUsed(0, 30)
assign Y[8] = w22[39:8]; //BitwidthUsed(0, 28)
assign Y[9] = w4_[39:8]; //BitwidthUsed(0, 25)
assign Y[10] = w0[39:8]; //BitwidthUsed(none)
//FIR_filter_firBlock_left_MultiplyBlock area estimate = 17570.0449805691;
endmodule //FIR_filter_firBlock_left_MultiplyBlock
module FIR_filter_firBlock_left (
X,
clk,
Y,
reset
);
// Port mode declarations:
input [31:0] X;
input clk;
output [31:0] Y;
input reset;
//registerOut
reg [31:0] Y;
wire [31:0] Y_in;
always@(posedge clk or negedge reset) begin
if(~reset) begin
Y <= 32'h00000000;
end else begin
Y <= Y_in;
end
end
wire [31:0] multProducts [0:10];
FIR_filter_firBlock_left_MultiplyBlock my_FIR_filter_firBlock_left_MultiplyBlock(
.X(X),
.Y1(multProducts[0]),
.Y2(multProducts[1]),
.Y3(multProducts[2]),
.Y4(multProducts[3]),
.Y5(multProducts[4]),
.Y6(multProducts[5]),
.Y7(multProducts[6]),
.Y8(multProducts[7]),
.Y9(multProducts[8]),
.Y10(multProducts[9]),
.Y11(multProducts[10])
);
reg [31:0] firStep[0:9];
always@(posedge clk or negedge reset) begin
if(~reset) begin
firStep[0] <= 32'h00000000;
firStep[1] <= 32'h00000000;
firStep[2] <= 32'h00000000;
firStep[3] <= 32'h00000000;
firStep[4] <= 32'h00000000;
firStep[5] <= 32'h00000000;
firStep[6] <= 32'h00000000;
firStep[7] <= 32'h00000000;
firStep[8] <= 32'h00000000;
firStep[9] <= 32'h00000000;
end
else begin
firStep[0] <= multProducts[0]; // 2448.23046908235 = flop(0, 31)
firStep[1] <= firStep[0] + multProducts[1]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[2] <= firStep[1] + multProducts[2]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[3] <= firStep[2] + multProducts[3]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[4] <= firStep[3] + multProducts[4]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[5] <= firStep[4] + multProducts[5]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[6] <= firStep[5] + multProducts[6]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[7] <= firStep[6] + multProducts[7]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[8] <= firStep[7] + multProducts[8]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[9] <= firStep[8] + multProducts[9]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
end
end
assign Y_in = firStep[9]+ multProducts[10];// 0 = adder(none)
//FIR_filter_firBlock_left area estimate = 64259.3966616544;
endmodule //FIR_filter_firBlock_left
/* Warning: zero-valued filter taps have been optimized away. */
module FIR_filter_firBlock_right_MultiplyBlock (
X,
Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8
);
// Port mode declarations:
input signed [31:0] X;
output signed [31:0]
Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8;
wire [31:0] Y [0:7];
assign Y1 = Y[0];
assign Y2 = Y[1];
assign Y3 = Y[2];
assign Y4 = Y[3];
assign Y5 = Y[4];
assign Y6 = Y[5];
assign Y7 = Y[6];
assign Y8 = Y[7];
//Multipliers:
wire signed [39:0]
w1,
w0,
w4,
w3,
w192,
w189,
w5,
w10,
w179,
w2,
w2_,
w32,
w32_,
w179_,
w378,
w378_;
assign w1 = X;
assign w0 = 0;
assign w10 = w5 << 1; //shl(1,35)
assign w179 = w189 - w10; //2943.86389821912 = subArea(1,39)
assign w179_ = -1 * w179; //1809.56165059559 = negArea(0,39)
assign w189 = w192 - w3; //2484.82071925441 = subArea(6,38)
assign w192 = w3 << 6; //shl(6,38)
assign w2 = w1 << 1; //shl(1,32)
assign w2_ = -1 * w2; //1437.00483871323 = negArea(1,32)
assign w3 = w4 - w1; //2331.80632626618 = subArea(2,32)
assign w32 = w1 << 5; //shl(5,36)
assign w32_ = -1 * w32; //1437.00483871323 = negArea(5,36)
assign w378 = w189 << 1; //shl(1,39)
assign w378_ = -1 * w378; //1762.99204911029 = negArea(1,39)
assign w4 = w1 << 2; //shl(2,32)
assign w5 = w1 + w4; //2195.42405790882 = adderArea(2,33)
assign Y[0] = w2_[39:8]; //BitwidthUsed(0, 24)
assign Y[1] = w0[39:8]; //BitwidthUsed(none)
assign Y[2] = w32_[39:8]; //BitwidthUsed(0, 28)
assign Y[3] = w0[39:8]; //BitwidthUsed(none)
assign Y[4] = w179_[39:8]; //BitwidthUsed(0, 31)
assign Y[5] = w0[39:8]; //BitwidthUsed(none)
assign Y[6] = w378_[39:8]; //BitwidthUsed(0, 31)
assign Y[7] = w0[39:8]; //BitwidthUsed(none)
//FIR_filter_firBlock_right_MultiplyBlock area estimate = 16402.4783787809;
endmodule //FIR_filter_firBlock_right_MultiplyBlock
module FIR_filter_firBlock_right (
X,
clk,
Y,
reset
);
// Port mode declarations:
input [31:0] X;
input clk;
output [31:0] Y;
input reset;
//registerOut
reg [31:0] Y;
wire [31:0] Y_in;
always@(posedge clk or negedge reset) begin
if(~reset) begin
Y <= 32'h00000000;
end else begin
Y <= Y_in;
end
end
wire [31:0] multProducts [0:7];
FIR_filter_firBlock_right_MultiplyBlock my_FIR_filter_firBlock_right_MultiplyBlock(
.X(X),
.Y1(multProducts[0]),
.Y2(multProducts[1]),
.Y3(multProducts[2]),
.Y4(multProducts[3]),
.Y5(multProducts[4]),
.Y6(multProducts[5]),
.Y7(multProducts[6]),
.Y8(multProducts[7])
);
reg [31:0] firStep[0:6];
always@(posedge clk or negedge reset) begin
if(~reset) begin
firStep[0] <= 32'h00000000;
firStep[1] <= 32'h00000000;
firStep[2] <= 32'h00000000;
firStep[3] <= 32'h00000000;
firStep[4] <= 32'h00000000;
firStep[5] <= 32'h00000000;
firStep[6] <= 32'h00000000;
end
else begin
firStep[0] <= multProducts[0]; // 2448.23046908235 = flop(0, 31)
firStep[1] <= firStep[0] + multProducts[1]; // 2448.23046908235 = flop(0, 31) + adder(none)
firStep[2] <= firStep[1] + multProducts[2]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[3] <= firStep[2] + multProducts[3]; // 2448.23046908235 = flop(0, 31) + adder(none)
firStep[4] <= firStep[3] + multProducts[4]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[5] <= firStep[4] + multProducts[5]; // 2448.23046908235 = flop(0, 31) + adder(none)
firStep[6] <= firStep[5] + multProducts[6]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
end
end
assign Y_in = firStep[6]+ multProducts[7];// 0 = adder(none)
//FIR_filter_firBlock_right area estimate = 42574.5943051662;
endmodule //FIR_filter_firBlock_right
|
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : fir_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-FIR core
//
module fir_top(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
wb_ack_o, wb_err_o, wb_dat_o,
wb_clk_i, wb_rst_i, int_o
);
parameter dw = 32;
parameter aw = 32;
input [aw-1:0] wb_adr_i;
input wb_cyc_i;
input [dw-1:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_stb_i;
input wb_we_i;
output wb_ack_o;
output wb_err_o;
output reg [dw-1:0] wb_dat_o;
output int_o;
input wb_clk_i;
input wb_rst_i;
assign wb_ack_o = 1'b1;
assign wb_err_o = 1'b0;
assign int_o = 1'b0;
// Internal registers
reg next;
reg [31:0] dataX [0:31];
reg [31:0] dataY [0:31];
reg [5:0] xSel=6'b0;
reg [5:0] ySel=6'b0;
reg [5:0] count;
wire [31:0] dataIn, dataOut, data_Out;
reg [31:0] data_In_data, data_In_addr, data_Out_addr;
reg data_valid, data_In_write;
wire next_out;
// Implement MD5 I/O memory map interface
// Write side
always @(posedge wb_clk_i)
begin
if(wb_rst_i)
begin
next <= 0;
data_In_write <= 0;
data_In_addr <= 0;
data_In_data <= 0;
end
else if(wb_stb_i & wb_we_i)
case(wb_adr_i[5:2])
0:
next <= wb_dat_i[0];
1:
data_In_write <= wb_dat_i[0];
2:
data_In_addr <= wb_dat_i;
3:
data_In_data <= wb_dat_i;
4:
data_Out_addr <= wb_dat_i;
default:
;
endcase
end // always @ (posedge wb_clk_i)
// Implement MD5 I/O memory map interface
// Read side
always @(*)
begin
case(wb_adr_i[5:2])
0:
wb_dat_o = {31'b0, next};
1:
wb_dat_o = {31'b0, data_In_write};
2:
wb_dat_o = data_In_addr;
3:
wb_dat_o = data_In_data;
4:
wb_dat_o = data_Out_addr;
5:
wb_dat_o = data_Out;
6:
wb_dat_o = {31'b0, data_valid};
default:
wb_dat_o = 32'b0;
endcase
end // always @ (*)
FIR_filter FIR_filter(
.clk(wb_clk_i),
.reset(~wb_rst_i),
.inData(dataIn),
.outData(dataOut));
reg data_In_write_r;
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
data_In_write_r <= 0;
else
data_In_write_r <= data_In_write;
end
wire data_In_write_posedge = data_In_write & ~data_In_write_r;
reg [15:0] i;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
for (i = 0; i < 32; i = i + 1)
dataX[i] <= 0;
else
dataX[data_In_addr] <= data_In_data;
end
assign data_Out = dataY[data_Out_addr];
reg next_r;
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
next_r <= 0;
else
next_r <= next;
end
wire next_posedge = next & ~next_r;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
xSel <= 0;
else if(next_posedge)
xSel <= 6'h00;
else if(xSel<6'b100000)
xSel <= xSel + 1;
end
assign dataIn = (xSel<6'b100000) ? dataX[xSel] : 32'b0;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
count <= 0;
else if(next_posedge)
begin
count <= 6'h00;
end
else if(xSel<4'b1010)
begin
count <= count +1;
end
end
assign next_out = (count == 4'b1000);
reg next_out_r;
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
next_out_r <= 0;
else
next_out_r <= next_out;
end
wire next_out_posedge = next_out & ~next_out_r;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i) begin
ySel <= 0;
for (i = 0; i < 32; i = i + 1)
dataY[i] <= 0;
end else if(next_out_posedge)
begin
ySel <= 6'h00;
end
else if(ySel<6'b100000)
begin
ySel <= ySel +1;
dataY[ySel] = dataOut;
end
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
data_valid <= 0;
else if(next_posedge)
begin
data_valid <= 0;
end
else if(next_out_posedge)
begin
data_valid <= 1;
end
end
endmodule
|
/*
* This source file contains a Verilog description of an IP core
* automatically generated by the SPIRAL HDL Generator.
*
* This product includes a hardware design developed by Carnegie Mellon University.
*
* Copyright (c) 2005-2011 by Peter A. Milder for the SPIRAL Project,
* Carnegie Mellon University
*
* For more information, see the SPIRAL project website at:
* http://www.spiral.net
*
* This design is provided for internal, non-commercial research use only
* and is not for redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
// Input/output stream: 2 complex words per cycle
// Throughput: one transform every 32 cycles
// Latency: 332 cycles
// Resources required:
// 20 multipliers (16 x 16 bit)
// 34 adders (16 x 16 bit)
// 4 RAMs (16 words, 32 bits per word)
// 4 RAMs (8 words, 32 bits per word)
// 12 RAMs (64 words, 32 bits per word)
// 4 RAMs (32 words, 32 bits per word)
// 2 ROMs (32 words, 16 bits per word)
// 2 ROMs (8 words, 16 bits per word)
// 12 ROMs (32 words, 5 bits per word)
// 2 ROMs (16 words, 16 bits per word)
// Generated on Tue Sep 04 00:36:47 EDT 2018
// Latency: 332 clock cycles
// Throughput: 1 transform every 32 cycles
// We use an interleaved complex data format. X0 represents the
// real portion of the first input, and X1 represents the imaginary
// portion. The X variables are system inputs and the Y variables
// are system outputs.
// The design uses a system of flag signals to indicate the
// beginning of the input and output data streams. The 'next'
// input (asserted high), is used to instruct the system that the
// input stream will begin on the following cycle.
// This system has a 'gap' of 32 cycles. This means that
// 32 cycles must elapse between the beginning of the input
// vectors.
// The output signal 'next_out' (also asserted high) indicates
// that the output vector will begin streaming out of the system
// on the following cycle.
// The system has a latency of 332 cycles. This means that
// the 'next_out' will be asserted 332 cycles after the user
// asserts 'next'.
// The simple testbench below will demonstrate the timing for loading
// and unloading data vectors.
// The system reset signal is asserted high.
// Please note: when simulating floating point code, you must include
// Xilinx's DSP slice simulation module.
// Latency: 332
// Gap: 32
// module_name_is:dft_top
module idft_top(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [15:0] t0_0;
wire [15:0] t0_1;
wire [15:0] t0_2;
wire [15:0] t0_3;
wire next_0;
wire [15:0] t1_0;
wire [15:0] t1_1;
wire [15:0] t1_2;
wire [15:0] t1_3;
wire next_1;
wire [15:0] t2_0;
wire [15:0] t2_1;
wire [15:0] t2_2;
wire [15:0] t2_3;
wire next_2;
wire [15:0] t3_0;
wire [15:0] t3_1;
wire [15:0] t3_2;
wire [15:0] t3_3;
wire next_3;
wire [15:0] t4_0;
wire [15:0] t4_1;
wire [15:0] t4_2;
wire [15:0] t4_3;
wire next_4;
wire [15:0] t5_0;
wire [15:0] t5_1;
wire [15:0] t5_2;
wire [15:0] t5_3;
wire next_5;
wire [15:0] t6_0;
wire [15:0] t6_1;
wire [15:0] t6_2;
wire [15:0] t6_3;
wire next_6;
wire [15:0] t7_0;
wire [15:0] t7_1;
wire [15:0] t7_2;
wire [15:0] t7_3;
wire next_7;
wire [15:0] t8_0;
wire [15:0] t8_1;
wire [15:0] t8_2;
wire [15:0] t8_3;
wire next_8;
wire [15:0] t9_0;
wire [15:0] t9_1;
wire [15:0] t9_2;
wire [15:0] t9_3;
wire next_9;
wire [15:0] t10_0;
wire [15:0] t10_1;
wire [15:0] t10_2;
wire [15:0] t10_3;
wire next_10;
wire [15:0] t11_0;
wire [15:0] t11_1;
wire [15:0] t11_2;
wire [15:0] t11_3;
wire next_11;
wire [15:0] t12_0;
wire [15:0] t12_1;
wire [15:0] t12_2;
wire [15:0] t12_3;
wire next_12;
wire [15:0] t13_0;
wire [15:0] t13_1;
wire [15:0] t13_2;
wire [15:0] t13_3;
wire next_13;
wire [15:0] t14_0;
wire [15:0] t14_1;
wire [15:0] t14_2;
wire [15:0] t14_3;
wire next_14;
wire [15:0] t15_0;
wire [15:0] t15_1;
wire [15:0] t15_2;
wire [15:0] t15_3;
wire next_15;
wire [15:0] t16_0;
wire [15:0] t16_1;
wire [15:0] t16_2;
wire [15:0] t16_3;
wire next_16;
wire [15:0] t17_0;
wire [15:0] t17_1;
wire [15:0] t17_2;
wire [15:0] t17_3;
wire next_17;
wire [15:0] t18_0;
wire [15:0] t18_1;
wire [15:0] t18_2;
wire [15:0] t18_3;
wire next_18;
assign t0_0 = X0;
assign Y0 = t18_0;
assign t0_1 = X1;
assign Y1 = t18_1;
assign t0_2 = X2;
assign Y2 = t18_2;
assign t0_3 = X3;
assign Y3 = t18_3;
assign next_0 = next;
assign next_out = next_18;
// latency=68, gap=32
rc7079 stage0(.clk(clk), .reset(reset), .next(next_0), .next_out(next_1),
.X0(t0_0), .Y0(t1_0),
.X1(t0_1), .Y1(t1_1),
.X2(t0_2), .Y2(t1_2),
.X3(t0_3), .Y3(t1_3));
// latency=2, gap=32
codeBlock7081 stage1(.clk(clk), .reset(reset), .next_in(next_1), .next_out(next_2),
.X0_in(t1_0), .Y0(t2_0),
.X1_in(t1_1), .Y1(t2_1),
.X2_in(t1_2), .Y2(t2_2),
.X3_in(t1_3), .Y3(t2_3));
// latency=8, gap=32
rc7163 stage2(.clk(clk), .reset(reset), .next(next_2), .next_out(next_3),
.X0(t2_0), .Y0(t3_0),
.X1(t2_1), .Y1(t3_1),
.X2(t2_2), .Y2(t3_2),
.X3(t2_3), .Y3(t3_3));
// latency=8, gap=32
DirSum_7344 stage3(.next(next_3), .clk(clk), .reset(reset), .next_out(next_4),
.X0(t3_0), .Y0(t4_0),
.X1(t3_1), .Y1(t4_1),
.X2(t3_2), .Y2(t4_2),
.X3(t3_3), .Y3(t4_3));
// latency=2, gap=32
codeBlock7347 stage4(.clk(clk), .reset(reset), .next_in(next_4), .next_out(next_5),
.X0_in(t4_0), .Y0(t5_0),
.X1_in(t4_1), .Y1(t5_1),
.X2_in(t4_2), .Y2(t5_2),
.X3_in(t4_3), .Y3(t5_3));
// latency=12, gap=32
rc7429 stage5(.clk(clk), .reset(reset), .next(next_5), .next_out(next_6),
.X0(t5_0), .Y0(t6_0),
.X1(t5_1), .Y1(t6_1),
.X2(t5_2), .Y2(t6_2),
.X3(t5_3), .Y3(t6_3));
// latency=8, gap=32
DirSum_7618 stage6(.next(next_6), .clk(clk), .reset(reset), .next_out(next_7),
.X0(t6_0), .Y0(t7_0),
.X1(t6_1), .Y1(t7_1),
.X2(t6_2), .Y2(t7_2),
.X3(t6_3), .Y3(t7_3));
// latency=2, gap=32
codeBlock7621 stage7(.clk(clk), .reset(reset), .next_in(next_7), .next_out(next_8),
.X0_in(t7_0), .Y0(t8_0),
.X1_in(t7_1), .Y1(t8_1),
.X2_in(t7_2), .Y2(t8_2),
.X3_in(t7_3), .Y3(t8_3));
// latency=20, gap=32
rc7703 stage8(.clk(clk), .reset(reset), .next(next_8), .next_out(next_9),
.X0(t8_0), .Y0(t9_0),
.X1(t8_1), .Y1(t9_1),
.X2(t8_2), .Y2(t9_2),
.X3(t8_3), .Y3(t9_3));
// latency=8, gap=32
DirSum_7908 stage9(.next(next_9), .clk(clk), .reset(reset), .next_out(next_10),
.X0(t9_0), .Y0(t10_0),
.X1(t9_1), .Y1(t10_1),
.X2(t9_2), .Y2(t10_2),
.X3(t9_3), .Y3(t10_3));
// latency=2, gap=32
codeBlock7911 stage10(.clk(clk), .reset(reset), .next_in(next_10), .next_out(next_11),
.X0_in(t10_0), .Y0(t11_0),
.X1_in(t10_1), .Y1(t11_1),
.X2_in(t10_2), .Y2(t11_2),
.X3_in(t10_3), .Y3(t11_3));
// latency=36, gap=32
rc7993 stage11(.clk(clk), .reset(reset), .next(next_11), .next_out(next_12),
.X0(t11_0), .Y0(t12_0),
.X1(t11_1), .Y1(t12_1),
.X2(t11_2), .Y2(t12_2),
.X3(t11_3), .Y3(t12_3));
// latency=8, gap=32
DirSum_8230 stage12(.next(next_12), .clk(clk), .reset(reset), .next_out(next_13),
.X0(t12_0), .Y0(t13_0),
.X1(t12_1), .Y1(t13_1),
.X2(t12_2), .Y2(t13_2),
.X3(t12_3), .Y3(t13_3));
// latency=2, gap=32
codeBlock8233 stage13(.clk(clk), .reset(reset), .next_in(next_13), .next_out(next_14),
.X0_in(t13_0), .Y0(t14_0),
.X1_in(t13_1), .Y1(t14_1),
.X2_in(t13_2), .Y2(t14_2),
.X3_in(t13_3), .Y3(t14_3));
// latency=68, gap=32
rc8315 stage14(.clk(clk), .reset(reset), .next(next_14), .next_out(next_15),
.X0(t14_0), .Y0(t15_0),
.X1(t14_1), .Y1(t15_1),
.X2(t14_2), .Y2(t15_2),
.X3(t14_3), .Y3(t15_3));
// latency=8, gap=32
DirSum_8615 stage15(.next(next_15), .clk(clk), .reset(reset), .next_out(next_16),
.X0(t15_0), .Y0(t16_0),
.X1(t15_1), .Y1(t16_1),
.X2(t15_2), .Y2(t16_2),
.X3(t15_3), .Y3(t16_3));
// latency=2, gap=32
codeBlock8618 stage16(.clk(clk), .reset(reset), .next_in(next_16), .next_out(next_17),
.X0_in(t16_0), .Y0(t17_0),
.X1_in(t16_1), .Y1(t17_1),
.X2_in(t16_2), .Y2(t17_2),
.X3_in(t16_3), .Y3(t17_3));
// latency=68, gap=32
rc8700 stage17(.clk(clk), .reset(reset), .next(next_17), .next_out(next_18),
.X0(t17_0), .Y0(t18_0),
.X1(t17_1), .Y1(t18_1),
.X2(t17_2), .Y2(t18_2),
.X3(t17_3), .Y3(t18_3));
endmodule
// Latency: 68
// Gap: 32
module rc7079(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm7077 instPerm9645(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet7077(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [4:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
5'd0: control <= 1'b1;
5'd1: control <= 1'b1;
5'd2: control <= 1'b1;
5'd3: control <= 1'b1;
5'd4: control <= 1'b1;
5'd5: control <= 1'b1;
5'd6: control <= 1'b1;
5'd7: control <= 1'b1;
5'd8: control <= 1'b1;
5'd9: control <= 1'b1;
5'd10: control <= 1'b1;
5'd11: control <= 1'b1;
5'd12: control <= 1'b1;
5'd13: control <= 1'b1;
5'd14: control <= 1'b1;
5'd15: control <= 1'b1;
5'd16: control <= 1'b0;
5'd17: control <= 1'b0;
5'd18: control <= 1'b0;
5'd19: control <= 1'b0;
5'd20: control <= 1'b0;
5'd21: control <= 1'b0;
5'd22: control <= 1'b0;
5'd23: control <= 1'b0;
5'd24: control <= 1'b0;
5'd25: control <= 1'b0;
5'd26: control <= 1'b0;
5'd27: control <= 1'b0;
5'd28: control <= 1'b0;
5'd29: control <= 1'b0;
5'd30: control <= 1'b0;
5'd31: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 68
// Gap: 32
module perm7077(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 32;
parameter addrbits = 5;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm0;
assign tm0 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_9650(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9651(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
nextReg #(31, 5) nextReg_9662(.X(next), .Y(next2), .reset(reset), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_9663(.X(next2), .Y(next3), .clk(clk));
nextReg #(32, 5) nextReg_9666(.X(next3), .Y(next4), .reset(reset), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9667(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(31, 1) shiftFIFO_9670(.X(tm0), .Y(tm0_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_9673(.X(tm0_d), .Y(tm0_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 5) shiftFIFO_9678(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm0_d, s1rdloc})
{1'd0, 5'd0}: s1rd0 <= 16;
{1'd0, 5'd1}: s1rd0 <= 24;
{1'd0, 5'd2}: s1rd0 <= 20;
{1'd0, 5'd3}: s1rd0 <= 28;
{1'd0, 5'd4}: s1rd0 <= 18;
{1'd0, 5'd5}: s1rd0 <= 26;
{1'd0, 5'd6}: s1rd0 <= 22;
{1'd0, 5'd7}: s1rd0 <= 30;
{1'd0, 5'd8}: s1rd0 <= 17;
{1'd0, 5'd9}: s1rd0 <= 25;
{1'd0, 5'd10}: s1rd0 <= 21;
{1'd0, 5'd11}: s1rd0 <= 29;
{1'd0, 5'd12}: s1rd0 <= 19;
{1'd0, 5'd13}: s1rd0 <= 27;
{1'd0, 5'd14}: s1rd0 <= 23;
{1'd0, 5'd15}: s1rd0 <= 31;
{1'd0, 5'd16}: s1rd0 <= 0;
{1'd0, 5'd17}: s1rd0 <= 8;
{1'd0, 5'd18}: s1rd0 <= 4;
{1'd0, 5'd19}: s1rd0 <= 12;
{1'd0, 5'd20}: s1rd0 <= 2;
{1'd0, 5'd21}: s1rd0 <= 10;
{1'd0, 5'd22}: s1rd0 <= 6;
{1'd0, 5'd23}: s1rd0 <= 14;
{1'd0, 5'd24}: s1rd0 <= 1;
{1'd0, 5'd25}: s1rd0 <= 9;
{1'd0, 5'd26}: s1rd0 <= 5;
{1'd0, 5'd27}: s1rd0 <= 13;
{1'd0, 5'd28}: s1rd0 <= 3;
{1'd0, 5'd29}: s1rd0 <= 11;
{1'd0, 5'd30}: s1rd0 <= 7;
{1'd0, 5'd31}: s1rd0 <= 15;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm0_d, s1rdloc})
{1'd0, 5'd0}: s1rd1 <= 0;
{1'd0, 5'd1}: s1rd1 <= 8;
{1'd0, 5'd2}: s1rd1 <= 4;
{1'd0, 5'd3}: s1rd1 <= 12;
{1'd0, 5'd4}: s1rd1 <= 2;
{1'd0, 5'd5}: s1rd1 <= 10;
{1'd0, 5'd6}: s1rd1 <= 6;
{1'd0, 5'd7}: s1rd1 <= 14;
{1'd0, 5'd8}: s1rd1 <= 1;
{1'd0, 5'd9}: s1rd1 <= 9;
{1'd0, 5'd10}: s1rd1 <= 5;
{1'd0, 5'd11}: s1rd1 <= 13;
{1'd0, 5'd12}: s1rd1 <= 3;
{1'd0, 5'd13}: s1rd1 <= 11;
{1'd0, 5'd14}: s1rd1 <= 7;
{1'd0, 5'd15}: s1rd1 <= 15;
{1'd0, 5'd16}: s1rd1 <= 16;
{1'd0, 5'd17}: s1rd1 <= 24;
{1'd0, 5'd18}: s1rd1 <= 20;
{1'd0, 5'd19}: s1rd1 <= 28;
{1'd0, 5'd20}: s1rd1 <= 18;
{1'd0, 5'd21}: s1rd1 <= 26;
{1'd0, 5'd22}: s1rd1 <= 22;
{1'd0, 5'd23}: s1rd1 <= 30;
{1'd0, 5'd24}: s1rd1 <= 17;
{1'd0, 5'd25}: s1rd1 <= 25;
{1'd0, 5'd26}: s1rd1 <= 21;
{1'd0, 5'd27}: s1rd1 <= 29;
{1'd0, 5'd28}: s1rd1 <= 19;
{1'd0, 5'd29}: s1rd1 <= 27;
{1'd0, 5'd30}: s1rd1 <= 23;
{1'd0, 5'd31}: s1rd1 <= 31;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet7077 sw(tm0_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm0_dd, writeCycle})
{1'd0, 5'd0}: s2wr0 <= 16;
{1'd0, 5'd1}: s2wr0 <= 17;
{1'd0, 5'd2}: s2wr0 <= 18;
{1'd0, 5'd3}: s2wr0 <= 19;
{1'd0, 5'd4}: s2wr0 <= 20;
{1'd0, 5'd5}: s2wr0 <= 21;
{1'd0, 5'd6}: s2wr0 <= 22;
{1'd0, 5'd7}: s2wr0 <= 23;
{1'd0, 5'd8}: s2wr0 <= 24;
{1'd0, 5'd9}: s2wr0 <= 25;
{1'd0, 5'd10}: s2wr0 <= 26;
{1'd0, 5'd11}: s2wr0 <= 27;
{1'd0, 5'd12}: s2wr0 <= 28;
{1'd0, 5'd13}: s2wr0 <= 29;
{1'd0, 5'd14}: s2wr0 <= 30;
{1'd0, 5'd15}: s2wr0 <= 31;
{1'd0, 5'd16}: s2wr0 <= 0;
{1'd0, 5'd17}: s2wr0 <= 1;
{1'd0, 5'd18}: s2wr0 <= 2;
{1'd0, 5'd19}: s2wr0 <= 3;
{1'd0, 5'd20}: s2wr0 <= 4;
{1'd0, 5'd21}: s2wr0 <= 5;
{1'd0, 5'd22}: s2wr0 <= 6;
{1'd0, 5'd23}: s2wr0 <= 7;
{1'd0, 5'd24}: s2wr0 <= 8;
{1'd0, 5'd25}: s2wr0 <= 9;
{1'd0, 5'd26}: s2wr0 <= 10;
{1'd0, 5'd27}: s2wr0 <= 11;
{1'd0, 5'd28}: s2wr0 <= 12;
{1'd0, 5'd29}: s2wr0 <= 13;
{1'd0, 5'd30}: s2wr0 <= 14;
{1'd0, 5'd31}: s2wr0 <= 15;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm0_dd, writeCycle})
{1'd0, 5'd0}: s2wr1 <= 0;
{1'd0, 5'd1}: s2wr1 <= 1;
{1'd0, 5'd2}: s2wr1 <= 2;
{1'd0, 5'd3}: s2wr1 <= 3;
{1'd0, 5'd4}: s2wr1 <= 4;
{1'd0, 5'd5}: s2wr1 <= 5;
{1'd0, 5'd6}: s2wr1 <= 6;
{1'd0, 5'd7}: s2wr1 <= 7;
{1'd0, 5'd8}: s2wr1 <= 8;
{1'd0, 5'd9}: s2wr1 <= 9;
{1'd0, 5'd10}: s2wr1 <= 10;
{1'd0, 5'd11}: s2wr1 <= 11;
{1'd0, 5'd12}: s2wr1 <= 12;
{1'd0, 5'd13}: s2wr1 <= 13;
{1'd0, 5'd14}: s2wr1 <= 14;
{1'd0, 5'd15}: s2wr1 <= 15;
{1'd0, 5'd16}: s2wr1 <= 16;
{1'd0, 5'd17}: s2wr1 <= 17;
{1'd0, 5'd18}: s2wr1 <= 18;
{1'd0, 5'd19}: s2wr1 <= 19;
{1'd0, 5'd20}: s2wr1 <= 20;
{1'd0, 5'd21}: s2wr1 <= 21;
{1'd0, 5'd22}: s2wr1 <= 22;
{1'd0, 5'd23}: s2wr1 <= 23;
{1'd0, 5'd24}: s2wr1 <= 24;
{1'd0, 5'd25}: s2wr1 <= 25;
{1'd0, 5'd26}: s2wr1 <= 26;
{1'd0, 5'd27}: s2wr1 <= 27;
{1'd0, 5'd28}: s2wr1 <= 28;
{1'd0, 5'd29}: s2wr1 <= 29;
{1'd0, 5'd30}: s2wr1 <= 30;
{1'd0, 5'd31}: s2wr1 <= 31;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
module memMod(in, out, inAddr, outAddr, writeSel, clk);
parameter depth=1024, width=16, logDepth=10;
input [width-1:0] in;
input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of mem is block
reg [width-1:0] mem[depth-1:0];
always @(posedge clk) begin
out <= mem[outAddr];
if (writeSel)
mem[inAddr] <= in;
end
endmodule
module memMod_dist(in, out, inAddr, outAddr, writeSel, clk);
parameter depth=1024, width=16, logDepth=10;
input [width-1:0] in;
input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of mem is distributed
reg [width-1:0] mem[depth-1:0];
always @(posedge clk) begin
out <= mem[outAddr];
if (writeSel)
mem[inAddr] <= in;
end
endmodule
module shiftRegFIFO(X, Y, clk);
parameter depth=1, width=1;
output [width-1:0] Y;
input [width-1:0] X;
input clk;
reg [width-1:0] mem [depth-1:0];
integer index;
assign Y = mem[depth-1];
always @ (posedge clk) begin
for(index=1;index<depth;index=index+1) begin
mem[index] <= mem[index-1];
end
mem[0]<=X;
end
endmodule
module nextReg(X, Y, reset, clk);
parameter depth=2, logDepth=1;
output Y;
input X;
input clk, reset;
reg [logDepth:0] count;
reg active;
assign Y = (count == depth) ? 1 : 0;
always @ (posedge clk) begin
if (reset == 1) begin
count <= 0;
active <= 0;
end
else if (X == 1) begin
active <= 1;
count <= 1;
end
else if (count == depth) begin
count <= 0;
active <= 0;
end
else if (active)
count <= count+1;
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock7081(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_9685(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a309;
wire signed [15:0] a310;
wire signed [15:0] a311;
wire signed [15:0] a312;
wire signed [15:0] t141;
wire signed [15:0] t142;
wire signed [15:0] t143;
wire signed [15:0] t144;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a309 = X0;
assign a310 = X2;
assign a311 = X1;
assign a312 = X3;
assign Y0 = t141;
assign Y1 = t142;
assign Y2 = t143;
assign Y3 = t144;
addfxp #(16, 1) add7093(.a(a309), .b(a310), .clk(clk), .q(t141)); // 0
addfxp #(16, 1) add7108(.a(a311), .b(a312), .clk(clk), .q(t142)); // 0
subfxp #(16, 1) sub7123(.a(a309), .b(a310), .clk(clk), .q(t143)); // 0
subfxp #(16, 1) sub7138(.a(a311), .b(a312), .clk(clk), .q(t144)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 8
// Gap: 2
module rc7163(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm7161 instPerm9686(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet7161(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [0:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
1'd0: control <= 1'b1;
1'd1: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 8
// Gap: 2
module perm7161(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 2;
parameter addrbits = 1;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm1;
assign tm1 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_9691(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9692(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
shiftRegFIFO #(1, 1) shiftFIFO_9701(.X(next), .Y(next2), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_9702(.X(next2), .Y(next3), .clk(clk));
shiftRegFIFO #(2, 1) shiftFIFO_9703(.X(next3), .Y(next4), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9704(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9707(.X(tm1), .Y(tm1_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_9710(.X(tm1_d), .Y(tm1_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 1) shiftFIFO_9715(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm1_d, s1rdloc})
{1'd0, 1'd0}: s1rd0 <= 1;
{1'd0, 1'd1}: s1rd0 <= 0;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm1_d, s1rdloc})
{1'd0, 1'd0}: s1rd1 <= 0;
{1'd0, 1'd1}: s1rd1 <= 1;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet7161 sw(tm1_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm1_dd, writeCycle})
{1'd0, 1'd0}: s2wr0 <= 1;
{1'd0, 1'd1}: s2wr0 <= 0;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm1_dd, writeCycle})
{1'd0, 1'd0}: s2wr1 <= 0;
{1'd0, 1'd1}: s2wr1 <= 1;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 2
module DirSum_7344(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [0:0] i5;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i5 <= 0;
end
else begin
if (next == 1)
i5 <= 0;
else if (i5 == 1)
i5 <= 0;
else
i5 <= i5 + 1;
end
end
codeBlock7166 codeBlockIsnt9716(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i5_in(i5),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D18_7334(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [0:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h0;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D20_7342(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [0:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'h4000;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock7166(clk, reset, next_in, next_out,
i5_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [0:0] i5_in;
reg [0:0] i5;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(7, 1) shiftFIFO_9719(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a293;
wire signed [15:0] a282;
wire signed [15:0] a296;
wire signed [15:0] a286;
wire signed [15:0] a297;
wire signed [15:0] a298;
reg signed [15:0] tm137;
reg signed [15:0] tm141;
reg signed [15:0] tm153;
reg signed [15:0] tm160;
reg signed [15:0] tm138;
reg signed [15:0] tm142;
reg signed [15:0] tm154;
reg signed [15:0] tm161;
wire signed [15:0] tm4;
wire signed [15:0] a287;
wire signed [15:0] tm5;
wire signed [15:0] a289;
reg signed [15:0] tm139;
reg signed [15:0] tm143;
reg signed [15:0] tm155;
reg signed [15:0] tm162;
reg signed [15:0] tm31;
reg signed [15:0] tm32;
reg signed [15:0] tm140;
reg signed [15:0] tm144;
reg signed [15:0] tm156;
reg signed [15:0] tm163;
reg signed [15:0] tm157;
reg signed [15:0] tm164;
wire signed [15:0] a288;
wire signed [15:0] a290;
wire signed [15:0] a291;
wire signed [15:0] a292;
reg signed [15:0] tm158;
reg signed [15:0] tm165;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
reg signed [15:0] tm159;
reg signed [15:0] tm166;
assign a293 = X0;
assign a282 = a293;
assign a296 = X1;
assign a286 = a296;
assign a297 = X2;
assign a298 = X3;
assign a287 = tm4;
assign a289 = tm5;
assign Y0 = tm159;
assign Y1 = tm166;
D18_7334 instD18inst0_7334(.addr(i5[0:0]), .out(tm4), .clk(clk));
D20_7342 instD20inst0_7342(.addr(i5[0:0]), .out(tm5), .clk(clk));
multfix #(16, 2) m7265(.a(tm31), .b(tm140), .clk(clk), .q_sc(a288), .q_unsc(), .rst(reset));
multfix #(16, 2) m7287(.a(tm32), .b(tm144), .clk(clk), .q_sc(a290), .q_unsc(), .rst(reset));
multfix #(16, 2) m7305(.a(tm32), .b(tm140), .clk(clk), .q_sc(a291), .q_unsc(), .rst(reset));
multfix #(16, 2) m7316(.a(tm31), .b(tm144), .clk(clk), .q_sc(a292), .q_unsc(), .rst(reset));
subfxp #(16, 1) sub7294(.a(a288), .b(a290), .clk(clk), .q(Y2)); // 6
addfxp #(16, 1) add7323(.a(a291), .b(a292), .clk(clk), .q(Y3)); // 6
always @(posedge clk) begin
if (reset == 1) begin
tm31 <= 0;
tm140 <= 0;
tm32 <= 0;
tm144 <= 0;
tm32 <= 0;
tm140 <= 0;
tm31 <= 0;
tm144 <= 0;
end
else begin
i5 <= i5_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm137 <= a297;
tm141 <= a298;
tm153 <= a282;
tm160 <= a286;
tm138 <= tm137;
tm142 <= tm141;
tm154 <= tm153;
tm161 <= tm160;
tm139 <= tm138;
tm143 <= tm142;
tm155 <= tm154;
tm162 <= tm161;
tm31 <= a287;
tm32 <= a289;
tm140 <= tm139;
tm144 <= tm143;
tm156 <= tm155;
tm163 <= tm162;
tm157 <= tm156;
tm164 <= tm163;
tm158 <= tm157;
tm165 <= tm164;
tm159 <= tm158;
tm166 <= tm165;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock7347(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_9722(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a249;
wire signed [15:0] a250;
wire signed [15:0] a251;
wire signed [15:0] a252;
wire signed [15:0] t117;
wire signed [15:0] t118;
wire signed [15:0] t119;
wire signed [15:0] t120;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a249 = X0;
assign a250 = X2;
assign a251 = X1;
assign a252 = X3;
assign Y0 = t117;
assign Y1 = t118;
assign Y2 = t119;
assign Y3 = t120;
addfxp #(16, 1) add7359(.a(a249), .b(a250), .clk(clk), .q(t117)); // 0
addfxp #(16, 1) add7374(.a(a251), .b(a252), .clk(clk), .q(t118)); // 0
subfxp #(16, 1) sub7389(.a(a249), .b(a250), .clk(clk), .q(t119)); // 0
subfxp #(16, 1) sub7404(.a(a251), .b(a252), .clk(clk), .q(t120)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 12
// Gap: 4
module rc7429(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm7427 instPerm9723(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet7427(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [1:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
2'd0: control <= 1'b1;
2'd1: control <= 1'b1;
2'd2: control <= 1'b0;
2'd3: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 12
// Gap: 4
module perm7427(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 4;
parameter addrbits = 2;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm6;
assign tm6 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_9728(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9729(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
shiftRegFIFO #(3, 1) shiftFIFO_9738(.X(next), .Y(next2), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_9739(.X(next2), .Y(next3), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_9740(.X(next3), .Y(next4), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9741(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_9744(.X(tm6), .Y(tm6_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_9747(.X(tm6_d), .Y(tm6_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 2) shiftFIFO_9752(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm6_d, s1rdloc})
{1'd0, 2'd0}: s1rd0 <= 2;
{1'd0, 2'd1}: s1rd0 <= 3;
{1'd0, 2'd2}: s1rd0 <= 0;
{1'd0, 2'd3}: s1rd0 <= 1;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm6_d, s1rdloc})
{1'd0, 2'd0}: s1rd1 <= 0;
{1'd0, 2'd1}: s1rd1 <= 1;
{1'd0, 2'd2}: s1rd1 <= 2;
{1'd0, 2'd3}: s1rd1 <= 3;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet7427 sw(tm6_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm6_dd, writeCycle})
{1'd0, 2'd0}: s2wr0 <= 2;
{1'd0, 2'd1}: s2wr0 <= 3;
{1'd0, 2'd2}: s2wr0 <= 0;
{1'd0, 2'd3}: s2wr0 <= 1;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm6_dd, writeCycle})
{1'd0, 2'd0}: s2wr1 <= 0;
{1'd0, 2'd1}: s2wr1 <= 1;
{1'd0, 2'd2}: s2wr1 <= 2;
{1'd0, 2'd3}: s2wr1 <= 3;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 4
module DirSum_7618(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [1:0] i4;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i4 <= 0;
end
else begin
if (next == 1)
i4 <= 0;
else if (i4 == 3)
i4 <= 0;
else
i4 <= i4 + 1;
end
end
codeBlock7432 codeBlockIsnt9753(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i4_in(i4),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D14_7604(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [1:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h2d41;
2: out3 <= 16'h0;
3: out3 <= 16'hd2bf;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D16_7616(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [1:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'h2d41;
2: out3 <= 16'h4000;
3: out3 <= 16'h2d41;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock7432(clk, reset, next_in, next_out,
i4_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [1:0] i4_in;
reg [1:0] i4;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(7, 1) shiftFIFO_9756(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a233;
wire signed [15:0] a222;
wire signed [15:0] a236;
wire signed [15:0] a226;
wire signed [15:0] a237;
wire signed [15:0] a238;
reg signed [15:0] tm167;
reg signed [15:0] tm171;
reg signed [15:0] tm183;
reg signed [15:0] tm190;
reg signed [15:0] tm168;
reg signed [15:0] tm172;
reg signed [15:0] tm184;
reg signed [15:0] tm191;
wire signed [15:0] tm9;
wire signed [15:0] a227;
wire signed [15:0] tm10;
wire signed [15:0] a229;
reg signed [15:0] tm169;
reg signed [15:0] tm173;
reg signed [15:0] tm185;
reg signed [15:0] tm192;
reg signed [15:0] tm39;
reg signed [15:0] tm40;
reg signed [15:0] tm170;
reg signed [15:0] tm174;
reg signed [15:0] tm186;
reg signed [15:0] tm193;
reg signed [15:0] tm187;
reg signed [15:0] tm194;
wire signed [15:0] a228;
wire signed [15:0] a230;
wire signed [15:0] a231;
wire signed [15:0] a232;
reg signed [15:0] tm188;
reg signed [15:0] tm195;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
reg signed [15:0] tm189;
reg signed [15:0] tm196;
assign a233 = X0;
assign a222 = a233;
assign a236 = X1;
assign a226 = a236;
assign a237 = X2;
assign a238 = X3;
assign a227 = tm9;
assign a229 = tm10;
assign Y0 = tm189;
assign Y1 = tm196;
D14_7604 instD14inst0_7604(.addr(i4[1:0]), .out(tm9), .clk(clk));
D16_7616 instD16inst0_7616(.addr(i4[1:0]), .out(tm10), .clk(clk));
multfix #(16, 2) m7531(.a(tm39), .b(tm170), .clk(clk), .q_sc(a228), .q_unsc(), .rst(reset));
multfix #(16, 2) m7553(.a(tm40), .b(tm174), .clk(clk), .q_sc(a230), .q_unsc(), .rst(reset));
multfix #(16, 2) m7571(.a(tm40), .b(tm170), .clk(clk), .q_sc(a231), .q_unsc(), .rst(reset));
multfix #(16, 2) m7582(.a(tm39), .b(tm174), .clk(clk), .q_sc(a232), .q_unsc(), .rst(reset));
subfxp #(16, 1) sub7560(.a(a228), .b(a230), .clk(clk), .q(Y2)); // 6
addfxp #(16, 1) add7589(.a(a231), .b(a232), .clk(clk), .q(Y3)); // 6
always @(posedge clk) begin
if (reset == 1) begin
tm39 <= 0;
tm170 <= 0;
tm40 <= 0;
tm174 <= 0;
tm40 <= 0;
tm170 <= 0;
tm39 <= 0;
tm174 <= 0;
end
else begin
i4 <= i4_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm167 <= a237;
tm171 <= a238;
tm183 <= a222;
tm190 <= a226;
tm168 <= tm167;
tm172 <= tm171;
tm184 <= tm183;
tm191 <= tm190;
tm169 <= tm168;
tm173 <= tm172;
tm185 <= tm184;
tm192 <= tm191;
tm39 <= a227;
tm40 <= a229;
tm170 <= tm169;
tm174 <= tm173;
tm186 <= tm185;
tm193 <= tm192;
tm187 <= tm186;
tm194 <= tm193;
tm188 <= tm187;
tm195 <= tm194;
tm189 <= tm188;
tm196 <= tm195;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock7621(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_9759(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a189;
wire signed [15:0] a190;
wire signed [15:0] a191;
wire signed [15:0] a192;
wire signed [15:0] t93;
wire signed [15:0] t94;
wire signed [15:0] t95;
wire signed [15:0] t96;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a189 = X0;
assign a190 = X2;
assign a191 = X1;
assign a192 = X3;
assign Y0 = t93;
assign Y1 = t94;
assign Y2 = t95;
assign Y3 = t96;
addfxp #(16, 1) add7633(.a(a189), .b(a190), .clk(clk), .q(t93)); // 0
addfxp #(16, 1) add7648(.a(a191), .b(a192), .clk(clk), .q(t94)); // 0
subfxp #(16, 1) sub7663(.a(a189), .b(a190), .clk(clk), .q(t95)); // 0
subfxp #(16, 1) sub7678(.a(a191), .b(a192), .clk(clk), .q(t96)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 20
// Gap: 8
module rc7703(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm7701 instPerm9760(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet7701(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [2:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
3'd0: control <= 1'b1;
3'd1: control <= 1'b1;
3'd2: control <= 1'b1;
3'd3: control <= 1'b1;
3'd4: control <= 1'b0;
3'd5: control <= 1'b0;
3'd6: control <= 1'b0;
3'd7: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 20
// Gap: 8
module perm7701(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 8;
parameter addrbits = 3;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm11;
assign tm11 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_9765(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9766(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
shiftRegFIFO #(7, 1) shiftFIFO_9775(.X(next), .Y(next2), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_9776(.X(next2), .Y(next3), .clk(clk));
shiftRegFIFO #(8, 1) shiftFIFO_9777(.X(next3), .Y(next4), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9778(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(7, 1) shiftFIFO_9781(.X(tm11), .Y(tm11_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_9784(.X(tm11_d), .Y(tm11_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 3) shiftFIFO_9789(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm11_d, s1rdloc})
{1'd0, 3'd0}: s1rd0 <= 4;
{1'd0, 3'd1}: s1rd0 <= 5;
{1'd0, 3'd2}: s1rd0 <= 6;
{1'd0, 3'd3}: s1rd0 <= 7;
{1'd0, 3'd4}: s1rd0 <= 0;
{1'd0, 3'd5}: s1rd0 <= 1;
{1'd0, 3'd6}: s1rd0 <= 2;
{1'd0, 3'd7}: s1rd0 <= 3;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm11_d, s1rdloc})
{1'd0, 3'd0}: s1rd1 <= 0;
{1'd0, 3'd1}: s1rd1 <= 1;
{1'd0, 3'd2}: s1rd1 <= 2;
{1'd0, 3'd3}: s1rd1 <= 3;
{1'd0, 3'd4}: s1rd1 <= 4;
{1'd0, 3'd5}: s1rd1 <= 5;
{1'd0, 3'd6}: s1rd1 <= 6;
{1'd0, 3'd7}: s1rd1 <= 7;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet7701 sw(tm11_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm11_dd, writeCycle})
{1'd0, 3'd0}: s2wr0 <= 4;
{1'd0, 3'd1}: s2wr0 <= 5;
{1'd0, 3'd2}: s2wr0 <= 6;
{1'd0, 3'd3}: s2wr0 <= 7;
{1'd0, 3'd4}: s2wr0 <= 0;
{1'd0, 3'd5}: s2wr0 <= 1;
{1'd0, 3'd6}: s2wr0 <= 2;
{1'd0, 3'd7}: s2wr0 <= 3;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm11_dd, writeCycle})
{1'd0, 3'd0}: s2wr1 <= 0;
{1'd0, 3'd1}: s2wr1 <= 1;
{1'd0, 3'd2}: s2wr1 <= 2;
{1'd0, 3'd3}: s2wr1 <= 3;
{1'd0, 3'd4}: s2wr1 <= 4;
{1'd0, 3'd5}: s2wr1 <= 5;
{1'd0, 3'd6}: s2wr1 <= 6;
{1'd0, 3'd7}: s2wr1 <= 7;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 8
module DirSum_7908(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [2:0] i3;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i3 <= 0;
end
else begin
if (next == 1)
i3 <= 0;
else if (i3 == 7)
i3 <= 0;
else
i3 <= i3 + 1;
end
end
codeBlock7706 codeBlockIsnt9790(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i3_in(i3),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D10_7886(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [2:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h3b21;
2: out3 <= 16'h2d41;
3: out3 <= 16'h187e;
4: out3 <= 16'h0;
5: out3 <= 16'he782;
6: out3 <= 16'hd2bf;
7: out3 <= 16'hc4df;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D12_7906(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [2:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'h187e;
2: out3 <= 16'h2d41;
3: out3 <= 16'h3b21;
4: out3 <= 16'h4000;
5: out3 <= 16'h3b21;
6: out3 <= 16'h2d41;
7: out3 <= 16'h187e;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock7706(clk, reset, next_in, next_out,
i3_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [2:0] i3_in;
reg [2:0] i3;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(7, 1) shiftFIFO_9793(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a173;
wire signed [15:0] a162;
wire signed [15:0] a176;
wire signed [15:0] a166;
wire signed [15:0] a177;
wire signed [15:0] a178;
reg signed [15:0] tm197;
reg signed [15:0] tm201;
reg signed [15:0] tm213;
reg signed [15:0] tm220;
reg signed [15:0] tm198;
reg signed [15:0] tm202;
reg signed [15:0] tm214;
reg signed [15:0] tm221;
wire signed [15:0] tm14;
wire signed [15:0] a167;
wire signed [15:0] tm15;
wire signed [15:0] a169;
reg signed [15:0] tm199;
reg signed [15:0] tm203;
reg signed [15:0] tm215;
reg signed [15:0] tm222;
reg signed [15:0] tm47;
reg signed [15:0] tm48;
reg signed [15:0] tm200;
reg signed [15:0] tm204;
reg signed [15:0] tm216;
reg signed [15:0] tm223;
reg signed [15:0] tm217;
reg signed [15:0] tm224;
wire signed [15:0] a168;
wire signed [15:0] a170;
wire signed [15:0] a171;
wire signed [15:0] a172;
reg signed [15:0] tm218;
reg signed [15:0] tm225;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
reg signed [15:0] tm219;
reg signed [15:0] tm226;
assign a173 = X0;
assign a162 = a173;
assign a176 = X1;
assign a166 = a176;
assign a177 = X2;
assign a178 = X3;
assign a167 = tm14;
assign a169 = tm15;
assign Y0 = tm219;
assign Y1 = tm226;
D10_7886 instD10inst0_7886(.addr(i3[2:0]), .out(tm14), .clk(clk));
D12_7906 instD12inst0_7906(.addr(i3[2:0]), .out(tm15), .clk(clk));
multfix #(16, 2) m7805(.a(tm47), .b(tm200), .clk(clk), .q_sc(a168), .q_unsc(), .rst(reset));
multfix #(16, 2) m7827(.a(tm48), .b(tm204), .clk(clk), .q_sc(a170), .q_unsc(), .rst(reset));
multfix #(16, 2) m7845(.a(tm48), .b(tm200), .clk(clk), .q_sc(a171), .q_unsc(), .rst(reset));
multfix #(16, 2) m7856(.a(tm47), .b(tm204), .clk(clk), .q_sc(a172), .q_unsc(), .rst(reset));
subfxp #(16, 1) sub7834(.a(a168), .b(a170), .clk(clk), .q(Y2)); // 6
addfxp #(16, 1) add7863(.a(a171), .b(a172), .clk(clk), .q(Y3)); // 6
always @(posedge clk) begin
if (reset == 1) begin
tm47 <= 0;
tm200 <= 0;
tm48 <= 0;
tm204 <= 0;
tm48 <= 0;
tm200 <= 0;
tm47 <= 0;
tm204 <= 0;
end
else begin
i3 <= i3_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm197 <= a177;
tm201 <= a178;
tm213 <= a162;
tm220 <= a166;
tm198 <= tm197;
tm202 <= tm201;
tm214 <= tm213;
tm221 <= tm220;
tm199 <= tm198;
tm203 <= tm202;
tm215 <= tm214;
tm222 <= tm221;
tm47 <= a167;
tm48 <= a169;
tm200 <= tm199;
tm204 <= tm203;
tm216 <= tm215;
tm223 <= tm222;
tm217 <= tm216;
tm224 <= tm223;
tm218 <= tm217;
tm225 <= tm224;
tm219 <= tm218;
tm226 <= tm225;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock7911(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_9796(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a129;
wire signed [15:0] a130;
wire signed [15:0] a131;
wire signed [15:0] a132;
wire signed [15:0] t69;
wire signed [15:0] t70;
wire signed [15:0] t71;
wire signed [15:0] t72;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a129 = X0;
assign a130 = X2;
assign a131 = X1;
assign a132 = X3;
assign Y0 = t69;
assign Y1 = t70;
assign Y2 = t71;
assign Y3 = t72;
addfxp #(16, 1) add7923(.a(a129), .b(a130), .clk(clk), .q(t69)); // 0
addfxp #(16, 1) add7938(.a(a131), .b(a132), .clk(clk), .q(t70)); // 0
subfxp #(16, 1) sub7953(.a(a129), .b(a130), .clk(clk), .q(t71)); // 0
subfxp #(16, 1) sub7968(.a(a131), .b(a132), .clk(clk), .q(t72)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 36
// Gap: 16
module rc7993(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm7991 instPerm9797(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet7991(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [3:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
4'd0: control <= 1'b1;
4'd1: control <= 1'b1;
4'd2: control <= 1'b1;
4'd3: control <= 1'b1;
4'd4: control <= 1'b1;
4'd5: control <= 1'b1;
4'd6: control <= 1'b1;
4'd7: control <= 1'b1;
4'd8: control <= 1'b0;
4'd9: control <= 1'b0;
4'd10: control <= 1'b0;
4'd11: control <= 1'b0;
4'd12: control <= 1'b0;
4'd13: control <= 1'b0;
4'd14: control <= 1'b0;
4'd15: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 36
// Gap: 16
module perm7991(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 16;
parameter addrbits = 4;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm16;
assign tm16 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_9802(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9803(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
nextReg #(15, 4) nextReg_9814(.X(next), .Y(next2), .reset(reset), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_9815(.X(next2), .Y(next3), .clk(clk));
nextReg #(16, 4) nextReg_9818(.X(next3), .Y(next4), .reset(reset), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9819(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(15, 1) shiftFIFO_9822(.X(tm16), .Y(tm16_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_9825(.X(tm16_d), .Y(tm16_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 4) shiftFIFO_9830(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm16_d, s1rdloc})
{1'd0, 4'd0}: s1rd0 <= 8;
{1'd0, 4'd1}: s1rd0 <= 9;
{1'd0, 4'd2}: s1rd0 <= 10;
{1'd0, 4'd3}: s1rd0 <= 11;
{1'd0, 4'd4}: s1rd0 <= 12;
{1'd0, 4'd5}: s1rd0 <= 13;
{1'd0, 4'd6}: s1rd0 <= 14;
{1'd0, 4'd7}: s1rd0 <= 15;
{1'd0, 4'd8}: s1rd0 <= 0;
{1'd0, 4'd9}: s1rd0 <= 1;
{1'd0, 4'd10}: s1rd0 <= 2;
{1'd0, 4'd11}: s1rd0 <= 3;
{1'd0, 4'd12}: s1rd0 <= 4;
{1'd0, 4'd13}: s1rd0 <= 5;
{1'd0, 4'd14}: s1rd0 <= 6;
{1'd0, 4'd15}: s1rd0 <= 7;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm16_d, s1rdloc})
{1'd0, 4'd0}: s1rd1 <= 0;
{1'd0, 4'd1}: s1rd1 <= 1;
{1'd0, 4'd2}: s1rd1 <= 2;
{1'd0, 4'd3}: s1rd1 <= 3;
{1'd0, 4'd4}: s1rd1 <= 4;
{1'd0, 4'd5}: s1rd1 <= 5;
{1'd0, 4'd6}: s1rd1 <= 6;
{1'd0, 4'd7}: s1rd1 <= 7;
{1'd0, 4'd8}: s1rd1 <= 8;
{1'd0, 4'd9}: s1rd1 <= 9;
{1'd0, 4'd10}: s1rd1 <= 10;
{1'd0, 4'd11}: s1rd1 <= 11;
{1'd0, 4'd12}: s1rd1 <= 12;
{1'd0, 4'd13}: s1rd1 <= 13;
{1'd0, 4'd14}: s1rd1 <= 14;
{1'd0, 4'd15}: s1rd1 <= 15;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet7991 sw(tm16_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm16_dd, writeCycle})
{1'd0, 4'd0}: s2wr0 <= 8;
{1'd0, 4'd1}: s2wr0 <= 9;
{1'd0, 4'd2}: s2wr0 <= 10;
{1'd0, 4'd3}: s2wr0 <= 11;
{1'd0, 4'd4}: s2wr0 <= 12;
{1'd0, 4'd5}: s2wr0 <= 13;
{1'd0, 4'd6}: s2wr0 <= 14;
{1'd0, 4'd7}: s2wr0 <= 15;
{1'd0, 4'd8}: s2wr0 <= 0;
{1'd0, 4'd9}: s2wr0 <= 1;
{1'd0, 4'd10}: s2wr0 <= 2;
{1'd0, 4'd11}: s2wr0 <= 3;
{1'd0, 4'd12}: s2wr0 <= 4;
{1'd0, 4'd13}: s2wr0 <= 5;
{1'd0, 4'd14}: s2wr0 <= 6;
{1'd0, 4'd15}: s2wr0 <= 7;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm16_dd, writeCycle})
{1'd0, 4'd0}: s2wr1 <= 0;
{1'd0, 4'd1}: s2wr1 <= 1;
{1'd0, 4'd2}: s2wr1 <= 2;
{1'd0, 4'd3}: s2wr1 <= 3;
{1'd0, 4'd4}: s2wr1 <= 4;
{1'd0, 4'd5}: s2wr1 <= 5;
{1'd0, 4'd6}: s2wr1 <= 6;
{1'd0, 4'd7}: s2wr1 <= 7;
{1'd0, 4'd8}: s2wr1 <= 8;
{1'd0, 4'd9}: s2wr1 <= 9;
{1'd0, 4'd10}: s2wr1 <= 10;
{1'd0, 4'd11}: s2wr1 <= 11;
{1'd0, 4'd12}: s2wr1 <= 12;
{1'd0, 4'd13}: s2wr1 <= 13;
{1'd0, 4'd14}: s2wr1 <= 14;
{1'd0, 4'd15}: s2wr1 <= 15;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 16
module DirSum_8230(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [3:0] i2;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i2 <= 0;
end
else begin
if (next == 1)
i2 <= 0;
else if (i2 == 15)
i2 <= 0;
else
i2 <= i2 + 1;
end
end
codeBlock7996 codeBlockIsnt9835(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i2_in(i2),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D6_8192(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [3:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h3ec5;
2: out3 <= 16'h3b21;
3: out3 <= 16'h3537;
4: out3 <= 16'h2d41;
5: out3 <= 16'h238e;
6: out3 <= 16'h187e;
7: out3 <= 16'hc7c;
8: out3 <= 16'h0;
9: out3 <= 16'hf384;
10: out3 <= 16'he782;
11: out3 <= 16'hdc72;
12: out3 <= 16'hd2bf;
13: out3 <= 16'hcac9;
14: out3 <= 16'hc4df;
15: out3 <= 16'hc13b;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D8_8228(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [3:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'hc7c;
2: out3 <= 16'h187e;
3: out3 <= 16'h238e;
4: out3 <= 16'h2d41;
5: out3 <= 16'h3537;
6: out3 <= 16'h3b21;
7: out3 <= 16'h3ec5;
8: out3 <= 16'h4000;
9: out3 <= 16'h3ec5;
10: out3 <= 16'h3b21;
11: out3 <= 16'h3537;
12: out3 <= 16'h2d41;
13: out3 <= 16'h238e;
14: out3 <= 16'h187e;
15: out3 <= 16'hc7c;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock7996(clk, reset, next_in, next_out,
i2_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [3:0] i2_in;
reg [3:0] i2;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(7, 1) shiftFIFO_9838(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a113;
wire signed [15:0] a102;
wire signed [15:0] a116;
wire signed [15:0] a106;
wire signed [15:0] a117;
wire signed [15:0] a118;
reg signed [15:0] tm227;
reg signed [15:0] tm231;
reg signed [15:0] tm243;
reg signed [15:0] tm250;
reg signed [15:0] tm228;
reg signed [15:0] tm232;
reg signed [15:0] tm244;
reg signed [15:0] tm251;
wire signed [15:0] tm19;
wire signed [15:0] a107;
wire signed [15:0] tm20;
wire signed [15:0] a109;
reg signed [15:0] tm229;
reg signed [15:0] tm233;
reg signed [15:0] tm245;
reg signed [15:0] tm252;
reg signed [15:0] tm55;
reg signed [15:0] tm56;
reg signed [15:0] tm230;
reg signed [15:0] tm234;
reg signed [15:0] tm246;
reg signed [15:0] tm253;
reg signed [15:0] tm247;
reg signed [15:0] tm254;
wire signed [15:0] a108;
wire signed [15:0] a110;
wire signed [15:0] a111;
wire signed [15:0] a112;
reg signed [15:0] tm248;
reg signed [15:0] tm255;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
reg signed [15:0] tm249;
reg signed [15:0] tm256;
assign a113 = X0;
assign a102 = a113;
assign a116 = X1;
assign a106 = a116;
assign a117 = X2;
assign a118 = X3;
assign a107 = tm19;
assign a109 = tm20;
assign Y0 = tm249;
assign Y1 = tm256;
D6_8192 instD6inst0_8192(.addr(i2[3:0]), .out(tm19), .clk(clk));
D8_8228 instD8inst0_8228(.addr(i2[3:0]), .out(tm20), .clk(clk));
multfix #(16, 2) m8095(.a(tm55), .b(tm230), .clk(clk), .q_sc(a108), .q_unsc(), .rst(reset));
multfix #(16, 2) m8117(.a(tm56), .b(tm234), .clk(clk), .q_sc(a110), .q_unsc(), .rst(reset));
multfix #(16, 2) m8135(.a(tm56), .b(tm230), .clk(clk), .q_sc(a111), .q_unsc(), .rst(reset));
multfix #(16, 2) m8146(.a(tm55), .b(tm234), .clk(clk), .q_sc(a112), .q_unsc(), .rst(reset));
subfxp #(16, 1) sub8124(.a(a108), .b(a110), .clk(clk), .q(Y2)); // 6
addfxp #(16, 1) add8153(.a(a111), .b(a112), .clk(clk), .q(Y3)); // 6
always @(posedge clk) begin
if (reset == 1) begin
tm55 <= 0;
tm230 <= 0;
tm56 <= 0;
tm234 <= 0;
tm56 <= 0;
tm230 <= 0;
tm55 <= 0;
tm234 <= 0;
end
else begin
i2 <= i2_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm227 <= a117;
tm231 <= a118;
tm243 <= a102;
tm250 <= a106;
tm228 <= tm227;
tm232 <= tm231;
tm244 <= tm243;
tm251 <= tm250;
tm229 <= tm228;
tm233 <= tm232;
tm245 <= tm244;
tm252 <= tm251;
tm55 <= a107;
tm56 <= a109;
tm230 <= tm229;
tm234 <= tm233;
tm246 <= tm245;
tm253 <= tm252;
tm247 <= tm246;
tm254 <= tm253;
tm248 <= tm247;
tm255 <= tm254;
tm249 <= tm248;
tm256 <= tm255;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock8233(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_9841(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a69;
wire signed [15:0] a70;
wire signed [15:0] a71;
wire signed [15:0] a72;
wire signed [15:0] t45;
wire signed [15:0] t46;
wire signed [15:0] t47;
wire signed [15:0] t48;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a69 = X0;
assign a70 = X2;
assign a71 = X1;
assign a72 = X3;
assign Y0 = t45;
assign Y1 = t46;
assign Y2 = t47;
assign Y3 = t48;
addfxp #(16, 1) add8245(.a(a69), .b(a70), .clk(clk), .q(t45)); // 0
addfxp #(16, 1) add8260(.a(a71), .b(a72), .clk(clk), .q(t46)); // 0
subfxp #(16, 1) sub8275(.a(a69), .b(a70), .clk(clk), .q(t47)); // 0
subfxp #(16, 1) sub8290(.a(a71), .b(a72), .clk(clk), .q(t48)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 68
// Gap: 32
module rc8315(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm8313 instPerm9842(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet8313(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [4:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
5'd0: control <= 1'b1;
5'd1: control <= 1'b1;
5'd2: control <= 1'b1;
5'd3: control <= 1'b1;
5'd4: control <= 1'b1;
5'd5: control <= 1'b1;
5'd6: control <= 1'b1;
5'd7: control <= 1'b1;
5'd8: control <= 1'b1;
5'd9: control <= 1'b1;
5'd10: control <= 1'b1;
5'd11: control <= 1'b1;
5'd12: control <= 1'b1;
5'd13: control <= 1'b1;
5'd14: control <= 1'b1;
5'd15: control <= 1'b1;
5'd16: control <= 1'b0;
5'd17: control <= 1'b0;
5'd18: control <= 1'b0;
5'd19: control <= 1'b0;
5'd20: control <= 1'b0;
5'd21: control <= 1'b0;
5'd22: control <= 1'b0;
5'd23: control <= 1'b0;
5'd24: control <= 1'b0;
5'd25: control <= 1'b0;
5'd26: control <= 1'b0;
5'd27: control <= 1'b0;
5'd28: control <= 1'b0;
5'd29: control <= 1'b0;
5'd30: control <= 1'b0;
5'd31: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 68
// Gap: 32
module perm8313(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 32;
parameter addrbits = 5;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm21;
assign tm21 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_9847(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9848(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
nextReg #(31, 5) nextReg_9859(.X(next), .Y(next2), .reset(reset), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_9860(.X(next2), .Y(next3), .clk(clk));
nextReg #(32, 5) nextReg_9863(.X(next3), .Y(next4), .reset(reset), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9864(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(31, 1) shiftFIFO_9867(.X(tm21), .Y(tm21_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_9870(.X(tm21_d), .Y(tm21_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 5) shiftFIFO_9875(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm21_d, s1rdloc})
{1'd0, 5'd0}: s1rd0 <= 16;
{1'd0, 5'd1}: s1rd0 <= 17;
{1'd0, 5'd2}: s1rd0 <= 18;
{1'd0, 5'd3}: s1rd0 <= 19;
{1'd0, 5'd4}: s1rd0 <= 20;
{1'd0, 5'd5}: s1rd0 <= 21;
{1'd0, 5'd6}: s1rd0 <= 22;
{1'd0, 5'd7}: s1rd0 <= 23;
{1'd0, 5'd8}: s1rd0 <= 24;
{1'd0, 5'd9}: s1rd0 <= 25;
{1'd0, 5'd10}: s1rd0 <= 26;
{1'd0, 5'd11}: s1rd0 <= 27;
{1'd0, 5'd12}: s1rd0 <= 28;
{1'd0, 5'd13}: s1rd0 <= 29;
{1'd0, 5'd14}: s1rd0 <= 30;
{1'd0, 5'd15}: s1rd0 <= 31;
{1'd0, 5'd16}: s1rd0 <= 0;
{1'd0, 5'd17}: s1rd0 <= 1;
{1'd0, 5'd18}: s1rd0 <= 2;
{1'd0, 5'd19}: s1rd0 <= 3;
{1'd0, 5'd20}: s1rd0 <= 4;
{1'd0, 5'd21}: s1rd0 <= 5;
{1'd0, 5'd22}: s1rd0 <= 6;
{1'd0, 5'd23}: s1rd0 <= 7;
{1'd0, 5'd24}: s1rd0 <= 8;
{1'd0, 5'd25}: s1rd0 <= 9;
{1'd0, 5'd26}: s1rd0 <= 10;
{1'd0, 5'd27}: s1rd0 <= 11;
{1'd0, 5'd28}: s1rd0 <= 12;
{1'd0, 5'd29}: s1rd0 <= 13;
{1'd0, 5'd30}: s1rd0 <= 14;
{1'd0, 5'd31}: s1rd0 <= 15;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm21_d, s1rdloc})
{1'd0, 5'd0}: s1rd1 <= 0;
{1'd0, 5'd1}: s1rd1 <= 1;
{1'd0, 5'd2}: s1rd1 <= 2;
{1'd0, 5'd3}: s1rd1 <= 3;
{1'd0, 5'd4}: s1rd1 <= 4;
{1'd0, 5'd5}: s1rd1 <= 5;
{1'd0, 5'd6}: s1rd1 <= 6;
{1'd0, 5'd7}: s1rd1 <= 7;
{1'd0, 5'd8}: s1rd1 <= 8;
{1'd0, 5'd9}: s1rd1 <= 9;
{1'd0, 5'd10}: s1rd1 <= 10;
{1'd0, 5'd11}: s1rd1 <= 11;
{1'd0, 5'd12}: s1rd1 <= 12;
{1'd0, 5'd13}: s1rd1 <= 13;
{1'd0, 5'd14}: s1rd1 <= 14;
{1'd0, 5'd15}: s1rd1 <= 15;
{1'd0, 5'd16}: s1rd1 <= 16;
{1'd0, 5'd17}: s1rd1 <= 17;
{1'd0, 5'd18}: s1rd1 <= 18;
{1'd0, 5'd19}: s1rd1 <= 19;
{1'd0, 5'd20}: s1rd1 <= 20;
{1'd0, 5'd21}: s1rd1 <= 21;
{1'd0, 5'd22}: s1rd1 <= 22;
{1'd0, 5'd23}: s1rd1 <= 23;
{1'd0, 5'd24}: s1rd1 <= 24;
{1'd0, 5'd25}: s1rd1 <= 25;
{1'd0, 5'd26}: s1rd1 <= 26;
{1'd0, 5'd27}: s1rd1 <= 27;
{1'd0, 5'd28}: s1rd1 <= 28;
{1'd0, 5'd29}: s1rd1 <= 29;
{1'd0, 5'd30}: s1rd1 <= 30;
{1'd0, 5'd31}: s1rd1 <= 31;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet8313 sw(tm21_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm21_dd, writeCycle})
{1'd0, 5'd0}: s2wr0 <= 16;
{1'd0, 5'd1}: s2wr0 <= 17;
{1'd0, 5'd2}: s2wr0 <= 18;
{1'd0, 5'd3}: s2wr0 <= 19;
{1'd0, 5'd4}: s2wr0 <= 20;
{1'd0, 5'd5}: s2wr0 <= 21;
{1'd0, 5'd6}: s2wr0 <= 22;
{1'd0, 5'd7}: s2wr0 <= 23;
{1'd0, 5'd8}: s2wr0 <= 24;
{1'd0, 5'd9}: s2wr0 <= 25;
{1'd0, 5'd10}: s2wr0 <= 26;
{1'd0, 5'd11}: s2wr0 <= 27;
{1'd0, 5'd12}: s2wr0 <= 28;
{1'd0, 5'd13}: s2wr0 <= 29;
{1'd0, 5'd14}: s2wr0 <= 30;
{1'd0, 5'd15}: s2wr0 <= 31;
{1'd0, 5'd16}: s2wr0 <= 0;
{1'd0, 5'd17}: s2wr0 <= 1;
{1'd0, 5'd18}: s2wr0 <= 2;
{1'd0, 5'd19}: s2wr0 <= 3;
{1'd0, 5'd20}: s2wr0 <= 4;
{1'd0, 5'd21}: s2wr0 <= 5;
{1'd0, 5'd22}: s2wr0 <= 6;
{1'd0, 5'd23}: s2wr0 <= 7;
{1'd0, 5'd24}: s2wr0 <= 8;
{1'd0, 5'd25}: s2wr0 <= 9;
{1'd0, 5'd26}: s2wr0 <= 10;
{1'd0, 5'd27}: s2wr0 <= 11;
{1'd0, 5'd28}: s2wr0 <= 12;
{1'd0, 5'd29}: s2wr0 <= 13;
{1'd0, 5'd30}: s2wr0 <= 14;
{1'd0, 5'd31}: s2wr0 <= 15;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm21_dd, writeCycle})
{1'd0, 5'd0}: s2wr1 <= 0;
{1'd0, 5'd1}: s2wr1 <= 1;
{1'd0, 5'd2}: s2wr1 <= 2;
{1'd0, 5'd3}: s2wr1 <= 3;
{1'd0, 5'd4}: s2wr1 <= 4;
{1'd0, 5'd5}: s2wr1 <= 5;
{1'd0, 5'd6}: s2wr1 <= 6;
{1'd0, 5'd7}: s2wr1 <= 7;
{1'd0, 5'd8}: s2wr1 <= 8;
{1'd0, 5'd9}: s2wr1 <= 9;
{1'd0, 5'd10}: s2wr1 <= 10;
{1'd0, 5'd11}: s2wr1 <= 11;
{1'd0, 5'd12}: s2wr1 <= 12;
{1'd0, 5'd13}: s2wr1 <= 13;
{1'd0, 5'd14}: s2wr1 <= 14;
{1'd0, 5'd15}: s2wr1 <= 15;
{1'd0, 5'd16}: s2wr1 <= 16;
{1'd0, 5'd17}: s2wr1 <= 17;
{1'd0, 5'd18}: s2wr1 <= 18;
{1'd0, 5'd19}: s2wr1 <= 19;
{1'd0, 5'd20}: s2wr1 <= 20;
{1'd0, 5'd21}: s2wr1 <= 21;
{1'd0, 5'd22}: s2wr1 <= 22;
{1'd0, 5'd23}: s2wr1 <= 23;
{1'd0, 5'd24}: s2wr1 <= 24;
{1'd0, 5'd25}: s2wr1 <= 25;
{1'd0, 5'd26}: s2wr1 <= 26;
{1'd0, 5'd27}: s2wr1 <= 27;
{1'd0, 5'd28}: s2wr1 <= 28;
{1'd0, 5'd29}: s2wr1 <= 29;
{1'd0, 5'd30}: s2wr1 <= 30;
{1'd0, 5'd31}: s2wr1 <= 31;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 32
module DirSum_8615(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [4:0] i1;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i1 <= 0;
end
else begin
if (next == 1)
i1 <= 0;
else if (i1 == 31)
i1 <= 0;
else
i1 <= i1 + 1;
end
end
codeBlock8317 codeBlockIsnt9880(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i1_in(i1),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D2_8545(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [4:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h3fb1;
2: out3 <= 16'h3ec5;
3: out3 <= 16'h3d3f;
4: out3 <= 16'h3b21;
5: out3 <= 16'h3871;
6: out3 <= 16'h3537;
7: out3 <= 16'h3179;
8: out3 <= 16'h2d41;
9: out3 <= 16'h289a;
10: out3 <= 16'h238e;
11: out3 <= 16'h1e2b;
12: out3 <= 16'h187e;
13: out3 <= 16'h1294;
14: out3 <= 16'hc7c;
15: out3 <= 16'h646;
16: out3 <= 16'h0;
17: out3 <= 16'hf9ba;
18: out3 <= 16'hf384;
19: out3 <= 16'hed6c;
20: out3 <= 16'he782;
21: out3 <= 16'he1d5;
22: out3 <= 16'hdc72;
23: out3 <= 16'hd766;
24: out3 <= 16'hd2bf;
25: out3 <= 16'hce87;
26: out3 <= 16'hcac9;
27: out3 <= 16'hc78f;
28: out3 <= 16'hc4df;
29: out3 <= 16'hc2c1;
30: out3 <= 16'hc13b;
31: out3 <= 16'hc04f;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D4_8613(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [4:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'h646;
2: out3 <= 16'hc7c;
3: out3 <= 16'h1294;
4: out3 <= 16'h187e;
5: out3 <= 16'h1e2b;
6: out3 <= 16'h238e;
7: out3 <= 16'h289a;
8: out3 <= 16'h2d41;
9: out3 <= 16'h3179;
10: out3 <= 16'h3537;
11: out3 <= 16'h3871;
12: out3 <= 16'h3b21;
13: out3 <= 16'h3d3f;
14: out3 <= 16'h3ec5;
15: out3 <= 16'h3fb1;
16: out3 <= 16'h4000;
17: out3 <= 16'h3fb1;
18: out3 <= 16'h3ec5;
19: out3 <= 16'h3d3f;
20: out3 <= 16'h3b21;
21: out3 <= 16'h3871;
22: out3 <= 16'h3537;
23: out3 <= 16'h3179;
24: out3 <= 16'h2d41;
25: out3 <= 16'h289a;
26: out3 <= 16'h238e;
27: out3 <= 16'h1e2b;
28: out3 <= 16'h187e;
29: out3 <= 16'h1294;
30: out3 <= 16'hc7c;
31: out3 <= 16'h646;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock8317(clk, reset, next_in, next_out,
i1_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [4:0] i1_in;
reg [4:0] i1;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(7, 1) shiftFIFO_9883(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a53;
wire signed [15:0] a42;
wire signed [15:0] a56;
wire signed [15:0] a46;
wire signed [15:0] a57;
wire signed [15:0] a58;
reg signed [15:0] tm257;
reg signed [15:0] tm261;
reg signed [15:0] tm273;
reg signed [15:0] tm280;
reg signed [15:0] tm258;
reg signed [15:0] tm262;
reg signed [15:0] tm274;
reg signed [15:0] tm281;
wire signed [15:0] tm24;
wire signed [15:0] a47;
wire signed [15:0] tm25;
wire signed [15:0] a49;
reg signed [15:0] tm259;
reg signed [15:0] tm263;
reg signed [15:0] tm275;
reg signed [15:0] tm282;
reg signed [15:0] tm63;
reg signed [15:0] tm64;
reg signed [15:0] tm260;
reg signed [15:0] tm264;
reg signed [15:0] tm276;
reg signed [15:0] tm283;
reg signed [15:0] tm277;
reg signed [15:0] tm284;
wire signed [15:0] a48;
wire signed [15:0] a50;
wire signed [15:0] a51;
wire signed [15:0] a52;
reg signed [15:0] tm278;
reg signed [15:0] tm285;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
reg signed [15:0] tm279;
reg signed [15:0] tm286;
assign a53 = X0;
assign a42 = a53;
assign a56 = X1;
assign a46 = a56;
assign a57 = X2;
assign a58 = X3;
assign a47 = tm24;
assign a49 = tm25;
assign Y0 = tm279;
assign Y1 = tm286;
D2_8545 instD2inst0_8545(.addr(i1[4:0]), .out(tm24), .clk(clk));
D4_8613 instD4inst0_8613(.addr(i1[4:0]), .out(tm25), .clk(clk));
multfix #(16, 2) m8416(.a(tm63), .b(tm260), .clk(clk), .q_sc(a48), .q_unsc(), .rst(reset));
multfix #(16, 2) m8438(.a(tm64), .b(tm264), .clk(clk), .q_sc(a50), .q_unsc(), .rst(reset));
multfix #(16, 2) m8456(.a(tm64), .b(tm260), .clk(clk), .q_sc(a51), .q_unsc(), .rst(reset));
multfix #(16, 2) m8467(.a(tm63), .b(tm264), .clk(clk), .q_sc(a52), .q_unsc(), .rst(reset));
subfxp #(16, 1) sub8445(.a(a48), .b(a50), .clk(clk), .q(Y2)); // 6
addfxp #(16, 1) add8474(.a(a51), .b(a52), .clk(clk), .q(Y3)); // 6
always @(posedge clk) begin
if (reset == 1) begin
tm63 <= 0;
tm260 <= 0;
tm64 <= 0;
tm264 <= 0;
tm64 <= 0;
tm260 <= 0;
tm63 <= 0;
tm264 <= 0;
end
else begin
i1 <= i1_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm257 <= a57;
tm261 <= a58;
tm273 <= a42;
tm280 <= a46;
tm258 <= tm257;
tm262 <= tm261;
tm274 <= tm273;
tm281 <= tm280;
tm259 <= tm258;
tm263 <= tm262;
tm275 <= tm274;
tm282 <= tm281;
tm63 <= a47;
tm64 <= a49;
tm260 <= tm259;
tm264 <= tm263;
tm276 <= tm275;
tm283 <= tm282;
tm277 <= tm276;
tm284 <= tm283;
tm278 <= tm277;
tm285 <= tm284;
tm279 <= tm278;
tm286 <= tm285;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock8618(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_9886(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a9;
wire signed [15:0] a10;
wire signed [15:0] a11;
wire signed [15:0] a12;
wire signed [15:0] t21;
wire signed [15:0] t22;
wire signed [15:0] t23;
wire signed [15:0] t24;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a9 = X0;
assign a10 = X2;
assign a11 = X1;
assign a12 = X3;
assign Y0 = t21;
assign Y1 = t22;
assign Y2 = t23;
assign Y3 = t24;
addfxp #(16, 1) add8630(.a(a9), .b(a10), .clk(clk), .q(t21)); // 0
addfxp #(16, 1) add8645(.a(a11), .b(a12), .clk(clk), .q(t22)); // 0
subfxp #(16, 1) sub8660(.a(a9), .b(a10), .clk(clk), .q(t23)); // 0
subfxp #(16, 1) sub8675(.a(a11), .b(a12), .clk(clk), .q(t24)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 68
// Gap: 32
module rc8700(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm8698 instPerm9887(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet8698(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [4:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
5'd0: control <= 1'b1;
5'd1: control <= 1'b1;
5'd2: control <= 1'b1;
5'd3: control <= 1'b1;
5'd4: control <= 1'b1;
5'd5: control <= 1'b1;
5'd6: control <= 1'b1;
5'd7: control <= 1'b1;
5'd8: control <= 1'b1;
5'd9: control <= 1'b1;
5'd10: control <= 1'b1;
5'd11: control <= 1'b1;
5'd12: control <= 1'b1;
5'd13: control <= 1'b1;
5'd14: control <= 1'b1;
5'd15: control <= 1'b1;
5'd16: control <= 1'b0;
5'd17: control <= 1'b0;
5'd18: control <= 1'b0;
5'd19: control <= 1'b0;
5'd20: control <= 1'b0;
5'd21: control <= 1'b0;
5'd22: control <= 1'b0;
5'd23: control <= 1'b0;
5'd24: control <= 1'b0;
5'd25: control <= 1'b0;
5'd26: control <= 1'b0;
5'd27: control <= 1'b0;
5'd28: control <= 1'b0;
5'd29: control <= 1'b0;
5'd30: control <= 1'b0;
5'd31: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 68
// Gap: 32
module perm8698(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 32;
parameter addrbits = 5;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm26;
assign tm26 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_9892(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9893(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
nextReg #(31, 5) nextReg_9904(.X(next), .Y(next2), .reset(reset), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_9905(.X(next2), .Y(next3), .clk(clk));
nextReg #(32, 5) nextReg_9908(.X(next3), .Y(next4), .reset(reset), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9909(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(31, 1) shiftFIFO_9912(.X(tm26), .Y(tm26_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_9915(.X(tm26_d), .Y(tm26_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 5) shiftFIFO_9920(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm26_d, s1rdloc})
{1'd0, 5'd0}: s1rd0 <= 1;
{1'd0, 5'd1}: s1rd0 <= 3;
{1'd0, 5'd2}: s1rd0 <= 5;
{1'd0, 5'd3}: s1rd0 <= 7;
{1'd0, 5'd4}: s1rd0 <= 9;
{1'd0, 5'd5}: s1rd0 <= 11;
{1'd0, 5'd6}: s1rd0 <= 13;
{1'd0, 5'd7}: s1rd0 <= 15;
{1'd0, 5'd8}: s1rd0 <= 17;
{1'd0, 5'd9}: s1rd0 <= 19;
{1'd0, 5'd10}: s1rd0 <= 21;
{1'd0, 5'd11}: s1rd0 <= 23;
{1'd0, 5'd12}: s1rd0 <= 25;
{1'd0, 5'd13}: s1rd0 <= 27;
{1'd0, 5'd14}: s1rd0 <= 29;
{1'd0, 5'd15}: s1rd0 <= 31;
{1'd0, 5'd16}: s1rd0 <= 0;
{1'd0, 5'd17}: s1rd0 <= 2;
{1'd0, 5'd18}: s1rd0 <= 4;
{1'd0, 5'd19}: s1rd0 <= 6;
{1'd0, 5'd20}: s1rd0 <= 8;
{1'd0, 5'd21}: s1rd0 <= 10;
{1'd0, 5'd22}: s1rd0 <= 12;
{1'd0, 5'd23}: s1rd0 <= 14;
{1'd0, 5'd24}: s1rd0 <= 16;
{1'd0, 5'd25}: s1rd0 <= 18;
{1'd0, 5'd26}: s1rd0 <= 20;
{1'd0, 5'd27}: s1rd0 <= 22;
{1'd0, 5'd28}: s1rd0 <= 24;
{1'd0, 5'd29}: s1rd0 <= 26;
{1'd0, 5'd30}: s1rd0 <= 28;
{1'd0, 5'd31}: s1rd0 <= 30;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm26_d, s1rdloc})
{1'd0, 5'd0}: s1rd1 <= 0;
{1'd0, 5'd1}: s1rd1 <= 2;
{1'd0, 5'd2}: s1rd1 <= 4;
{1'd0, 5'd3}: s1rd1 <= 6;
{1'd0, 5'd4}: s1rd1 <= 8;
{1'd0, 5'd5}: s1rd1 <= 10;
{1'd0, 5'd6}: s1rd1 <= 12;
{1'd0, 5'd7}: s1rd1 <= 14;
{1'd0, 5'd8}: s1rd1 <= 16;
{1'd0, 5'd9}: s1rd1 <= 18;
{1'd0, 5'd10}: s1rd1 <= 20;
{1'd0, 5'd11}: s1rd1 <= 22;
{1'd0, 5'd12}: s1rd1 <= 24;
{1'd0, 5'd13}: s1rd1 <= 26;
{1'd0, 5'd14}: s1rd1 <= 28;
{1'd0, 5'd15}: s1rd1 <= 30;
{1'd0, 5'd16}: s1rd1 <= 1;
{1'd0, 5'd17}: s1rd1 <= 3;
{1'd0, 5'd18}: s1rd1 <= 5;
{1'd0, 5'd19}: s1rd1 <= 7;
{1'd0, 5'd20}: s1rd1 <= 9;
{1'd0, 5'd21}: s1rd1 <= 11;
{1'd0, 5'd22}: s1rd1 <= 13;
{1'd0, 5'd23}: s1rd1 <= 15;
{1'd0, 5'd24}: s1rd1 <= 17;
{1'd0, 5'd25}: s1rd1 <= 19;
{1'd0, 5'd26}: s1rd1 <= 21;
{1'd0, 5'd27}: s1rd1 <= 23;
{1'd0, 5'd28}: s1rd1 <= 25;
{1'd0, 5'd29}: s1rd1 <= 27;
{1'd0, 5'd30}: s1rd1 <= 29;
{1'd0, 5'd31}: s1rd1 <= 31;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet8698 sw(tm26_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm26_dd, writeCycle})
{1'd0, 5'd0}: s2wr0 <= 16;
{1'd0, 5'd1}: s2wr0 <= 17;
{1'd0, 5'd2}: s2wr0 <= 18;
{1'd0, 5'd3}: s2wr0 <= 19;
{1'd0, 5'd4}: s2wr0 <= 20;
{1'd0, 5'd5}: s2wr0 <= 21;
{1'd0, 5'd6}: s2wr0 <= 22;
{1'd0, 5'd7}: s2wr0 <= 23;
{1'd0, 5'd8}: s2wr0 <= 24;
{1'd0, 5'd9}: s2wr0 <= 25;
{1'd0, 5'd10}: s2wr0 <= 26;
{1'd0, 5'd11}: s2wr0 <= 27;
{1'd0, 5'd12}: s2wr0 <= 28;
{1'd0, 5'd13}: s2wr0 <= 29;
{1'd0, 5'd14}: s2wr0 <= 30;
{1'd0, 5'd15}: s2wr0 <= 31;
{1'd0, 5'd16}: s2wr0 <= 0;
{1'd0, 5'd17}: s2wr0 <= 1;
{1'd0, 5'd18}: s2wr0 <= 2;
{1'd0, 5'd19}: s2wr0 <= 3;
{1'd0, 5'd20}: s2wr0 <= 4;
{1'd0, 5'd21}: s2wr0 <= 5;
{1'd0, 5'd22}: s2wr0 <= 6;
{1'd0, 5'd23}: s2wr0 <= 7;
{1'd0, 5'd24}: s2wr0 <= 8;
{1'd0, 5'd25}: s2wr0 <= 9;
{1'd0, 5'd26}: s2wr0 <= 10;
{1'd0, 5'd27}: s2wr0 <= 11;
{1'd0, 5'd28}: s2wr0 <= 12;
{1'd0, 5'd29}: s2wr0 <= 13;
{1'd0, 5'd30}: s2wr0 <= 14;
{1'd0, 5'd31}: s2wr0 <= 15;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm26_dd, writeCycle})
{1'd0, 5'd0}: s2wr1 <= 0;
{1'd0, 5'd1}: s2wr1 <= 1;
{1'd0, 5'd2}: s2wr1 <= 2;
{1'd0, 5'd3}: s2wr1 <= 3;
{1'd0, 5'd4}: s2wr1 <= 4;
{1'd0, 5'd5}: s2wr1 <= 5;
{1'd0, 5'd6}: s2wr1 <= 6;
{1'd0, 5'd7}: s2wr1 <= 7;
{1'd0, 5'd8}: s2wr1 <= 8;
{1'd0, 5'd9}: s2wr1 <= 9;
{1'd0, 5'd10}: s2wr1 <= 10;
{1'd0, 5'd11}: s2wr1 <= 11;
{1'd0, 5'd12}: s2wr1 <= 12;
{1'd0, 5'd13}: s2wr1 <= 13;
{1'd0, 5'd14}: s2wr1 <= 14;
{1'd0, 5'd15}: s2wr1 <= 15;
{1'd0, 5'd16}: s2wr1 <= 16;
{1'd0, 5'd17}: s2wr1 <= 17;
{1'd0, 5'd18}: s2wr1 <= 18;
{1'd0, 5'd19}: s2wr1 <= 19;
{1'd0, 5'd20}: s2wr1 <= 20;
{1'd0, 5'd21}: s2wr1 <= 21;
{1'd0, 5'd22}: s2wr1 <= 22;
{1'd0, 5'd23}: s2wr1 <= 23;
{1'd0, 5'd24}: s2wr1 <= 24;
{1'd0, 5'd25}: s2wr1 <= 25;
{1'd0, 5'd26}: s2wr1 <= 26;
{1'd0, 5'd27}: s2wr1 <= 27;
{1'd0, 5'd28}: s2wr1 <= 28;
{1'd0, 5'd29}: s2wr1 <= 29;
{1'd0, 5'd30}: s2wr1 <= 30;
{1'd0, 5'd31}: s2wr1 <= 31;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
module multfix(clk, rst, a, b, q_sc, q_unsc);
parameter WIDTH=35, CYCLES=6;
input signed [WIDTH-1:0] a,b;
output [WIDTH-1:0] q_sc;
output [WIDTH-1:0] q_unsc;
input clk, rst;
reg signed [2*WIDTH-1:0] q[CYCLES-1:0];
wire signed [2*WIDTH-1:0] res;
integer i;
assign res = q[CYCLES-1];
assign q_unsc = res[WIDTH-1:0];
assign q_sc = {res[2*WIDTH-1], res[2*WIDTH-4:WIDTH-2]};
always @(posedge clk) begin
q[0] <= a * b;
for (i = 1; i < CYCLES; i=i+1) begin
q[i] <= q[i-1];
end
end
endmodule
module addfxp(a, b, q, clk);
parameter width = 16, cycles=1;
input signed [width-1:0] a, b;
input clk;
output signed [width-1:0] q;
reg signed [width-1:0] res[cycles-1:0];
assign q = res[cycles-1];
integer i;
always @(posedge clk) begin
res[0] <= a+b;
for (i=1; i < cycles; i = i+1)
res[i] <= res[i-1];
end
endmodule
module subfxp(a, b, q, clk);
parameter width = 16, cycles=1;
input signed [width-1:0] a, b;
input clk;
output signed [width-1:0] q;
reg signed [width-1:0] res[cycles-1:0];
assign q = res[cycles-1];
integer i;
always @(posedge clk) begin
res[0] <= a-b;
for (i=1; i < cycles; i = i+1)
res[i] <= res[i-1];
end
endmodule |
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : idft_top_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-IDFT core
//
module idft_top_top(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
wb_ack_o, wb_err_o, wb_dat_o,
wb_clk_i, wb_rst_i, int_o
);
parameter dw = 32;
parameter aw = 32;
input [aw-1:0] wb_adr_i;
input wb_cyc_i;
input [dw-1:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_stb_i;
input wb_we_i;
output wb_ack_o;
output wb_err_o;
output reg [dw-1:0] wb_dat_o;
output int_o;
input wb_clk_i;
input wb_rst_i;
assign wb_ack_o = 1'b1;
assign wb_err_o = 1'b0;
assign int_o = 1'b0;
// Internal registers
reg next;
reg [63:0] dataX [0:31];
reg [63:0] dataY [0:31];
reg [5:0] xSel;
reg [5:0] ySel;
wire [63:0] dataIn, dataOut, dataR_Out;
reg [63:0] data_In_data, data_In_addr, data_Out_addr;
reg data_valid, data_In_write;
wire next_out, next_posedge;
// Implement MD5 I/O memory map interface
// Write side
always @(posedge wb_clk_i)
begin
if(wb_rst_i)
begin
next <= 0;
data_In_write <= 0;
data_In_addr <= 0;
data_In_data[31:0] <= 0;
data_In_data[63:32]<= 0;
end
else if(wb_stb_i & wb_we_i)
case(wb_adr_i[5:2])
0:
next <= wb_dat_i[0];
1:
data_In_write <= wb_dat_i[0];
2:
data_In_addr <= wb_dat_i;
3:
data_In_data[31:0] <= wb_dat_i;
4:
data_In_data[63:32]<= wb_dat_i;
5:
data_Out_addr <= wb_dat_i;
default:
;
endcase
end // always @ (posedge wb_clk_i)
// Implement MD5 I/O memory map interface
// Read side
always @(*)
begin
case(wb_adr_i[5:2])
0:
wb_dat_o = {31'b0, next};
1:
wb_dat_o = {31'b0, data_In_write};
2:
wb_dat_o = data_In_addr;
3:
wb_dat_o = data_In_data[31:0];
4:
wb_dat_o = data_In_data[63:32];
5:
wb_dat_o = data_Out_addr;
6:
wb_dat_o = dataR_Out[31:0];
7:
wb_dat_o = dataR_Out[63:32];
8:
wb_dat_o = {31'b0, data_valid};
default:
wb_dat_o = 32'b0;
endcase
end // always @ (*)
idft_top idft_top(
.clk(wb_clk_i),
.reset(wb_rst_i),
.next(next_posedge),
.next_out(next_out),
.X0(dataIn[15:0]),
.X1(dataIn[31:16]),
.X2(dataIn[47:32]),
.X3(dataIn[63:48]),
.Y0(dataOut[15:0]),
.Y1(dataOut[31:16]),
.Y2(dataOut[47:32]),
.Y3(dataOut[63:48]));
reg data_In_write_r;
always @(posedge wb_clk_i)
begin
data_In_write_r <= data_In_write;
end
wire data_In_write_posedge = data_In_write & ~data_In_write_r;
always @ (posedge wb_clk_i)
begin
if(data_In_write_posedge)
begin
dataX[data_In_addr] <= data_In_data;
end
end
assign dataR_Out=dataY[data_Out_addr];
reg next_r;
always @(posedge wb_clk_i)
begin
next_r <= next;
end
assign next_posedge = next & ~next_r;
always @ (posedge wb_clk_i)
begin
if(next_posedge)
begin
xSel <= 6'h00;
end
else if(xSel<6'b100000)
begin
xSel <= xSel +1;
end
end
assign dataIn = dataX[xSel];
reg next_out_r;
always @(posedge wb_clk_i)
begin
next_out_r <= next_out;
end
wire next_out_posedge = next_out & ~next_out_r;
always @ (posedge wb_clk_i)
begin
if(next_out_posedge)
begin
ySel <= 6'h00;
end
else if(ySel<6'b100000)
begin
ySel <= ySel +1;
dataY[ySel] = dataOut;
end
end
always @ (posedge wb_clk_i)
begin
if(next_posedge)
begin
data_valid <= 0;
end
else if(next_out_posedge)
begin
data_valid <= 1;
end
end
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral IIR Filter Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./iirGen.pl -A 256 0 378 0 179 0 32 0 2 0 0 0 -B 0 4 22 68 136 191 191 136 68 22 4 0 -moduleName IIR_filter -fractionalBits 8 -bitWidth 32 -inData inData -inReg -outReg -outData outData -clk clk -reset reset -reset_edge negedge -filterForm 1 -debug -outFile ../outputs/filter_1536036361.v */
/* Warning: zero-valued filter taps have been optimized away. */
module IIR_filter_firBlock_left_MultiplyBlock (
X,
Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8,
Y9,
Y10,
Y11
);
// Port mode declarations:
input signed [31:0] X;
output signed [31:0]
Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8,
Y9,
Y10,
Y11;
wire [31:0] Y [0:10];
assign Y1 = Y[0];
assign Y2 = Y[1];
assign Y3 = Y[2];
assign Y4 = Y[3];
assign Y5 = Y[4];
assign Y6 = Y[5];
assign Y7 = Y[6];
assign Y8 = Y[7];
assign Y9 = Y[8];
assign Y10 = Y[9];
assign Y11 = Y[10];
//Multipliers:
wire signed [39:0]
w1,
w0,
w16,
w17,
w4,
w3,
w8,
w11,
w192,
w191,
w22,
w68,
w136;
assign w1 = X;
assign w0 = 0;
assign w11 = w3 + w8; //2195.42405790882 = adderArea(3,34)
assign w136 = w17 << 3; //shl(3,39)
assign w16 = w1 << 4; //shl(4,35)
assign w17 = w1 + w16; //2195.42405790882 = adderArea(4,35)
assign w191 = w192 - w1; //2561.32791574853 = subArea(6,39)
assign w192 = w3 << 6; //shl(6,39)
assign w22 = w11 << 1; //shl(1,36)
assign w3 = w4 - w1; //2408.3135227603 = subArea(2,33)
assign w4 = w1 << 2; //shl(2,33)
assign w68 = w17 << 2; //shl(2,38)
assign w8 = w1 << 3; //shl(3,34)
assign Y[0] = w4[39:8]; //BitwidthUsed(0, 25)
assign Y[1] = w22[39:8]; //BitwidthUsed(0, 28)
assign Y[2] = w68[39:8]; //BitwidthUsed(0, 30)
assign Y[3] = w136[39:8]; //BitwidthUsed(0, 31)
assign Y[4] = w191[39:8]; //BitwidthUsed(0, 31)
assign Y[5] = w191[39:8]; //BitwidthUsed(0, 31)
assign Y[6] = w136[39:8]; //BitwidthUsed(0, 31)
assign Y[7] = w68[39:8]; //BitwidthUsed(0, 30)
assign Y[8] = w22[39:8]; //BitwidthUsed(0, 28)
assign Y[9] = w4[39:8]; //BitwidthUsed(0, 25)
assign Y[10] = w0[39:8]; //BitwidthUsed(none)
//IIR_filter_firBlock_left_MultiplyBlock area estimate = 9360.48955432647;
endmodule //IIR_filter_firBlock_left_MultiplyBlock
module IIR_filter_firBlock_left (
X,
clk,
Y,
reset
);
// Port mode declarations:
input [31:0] X;
input clk;
output [31:0] Y;
input reset;
//registerOut
reg [31:0] Y;
wire [31:0] Y_in;
always@(posedge clk or negedge reset) begin
if(~reset) begin
Y <= 32'h00000000;
end else begin
Y <= Y_in;
end
end
wire [31:0] multProducts [0:10];
IIR_filter_firBlock_left_MultiplyBlock my_IIR_filter_firBlock_left_MultiplyBlock(
.X(X),
.Y1(multProducts[0]),
.Y2(multProducts[1]),
.Y3(multProducts[2]),
.Y4(multProducts[3]),
.Y5(multProducts[4]),
.Y6(multProducts[5]),
.Y7(multProducts[6]),
.Y8(multProducts[7]),
.Y9(multProducts[8]),
.Y10(multProducts[9]),
.Y11(multProducts[10])
);
reg [31:0] firStep[0:9];
always@(posedge clk or negedge reset) begin
if(~reset) begin
firStep[0] <= 32'h00000000;
firStep[1] <= 32'h00000000;
firStep[2] <= 32'h00000000;
firStep[3] <= 32'h00000000;
firStep[4] <= 32'h00000000;
firStep[5] <= 32'h00000000;
firStep[6] <= 32'h00000000;
firStep[7] <= 32'h00000000;
firStep[8] <= 32'h00000000;
firStep[9] <= 32'h00000000;
end
else begin
firStep[0] <= multProducts[0]; // 2448.23046908235 = flop(0, 31)
firStep[1] <= firStep[0] + multProducts[1]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[2] <= firStep[1] + multProducts[2]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[3] <= firStep[2] + multProducts[3]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[4] <= firStep[3] + multProducts[4]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[5] <= firStep[4] + multProducts[5]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[6] <= firStep[5] + multProducts[6]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[7] <= firStep[6] + multProducts[7]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[8] <= firStep[7] + multProducts[8]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[9] <= firStep[8] + multProducts[9]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
end
end
assign Y_in = firStep[9]+ multProducts[10];// 0 = adder(none)
//IIR_filter_firBlock_left area estimate = 56049.8412354117;
endmodule //IIR_filter_firBlock_left
/* Warning: zero-valued filter taps have been optimized away. */
module IIR_filter_firBlock_right_MultiplyBlock (
X,
Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8
);
// Port mode declarations:
input signed [31:0] X;
output signed [31:0]
Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8;
wire [31:0] Y [0:7];
assign Y1 = Y[0];
assign Y2 = Y[1];
assign Y3 = Y[2];
assign Y4 = Y[3];
assign Y5 = Y[4];
assign Y6 = Y[5];
assign Y7 = Y[6];
assign Y8 = Y[7];
//Multipliers:
wire signed [39:0]
w1,
w0,
w4,
w3,
w192,
w189,
w5,
w10,
w179,
w2,
w2_,
w32,
w32_,
w179_,
w378,
w378_;
assign w1 = X;
assign w0 = 0;
assign w10 = w5 << 1; //shl(1,35)
assign w179 = w189 - w10; //2943.86389821912 = subArea(1,39)
assign w179_ = -1 * w179; //1809.56165059559 = negArea(0,39)
assign w189 = w192 - w3; //2484.82071925441 = subArea(6,38)
assign w192 = w3 << 6; //shl(6,38)
assign w2 = w1 << 1; //shl(1,32)
assign w2_ = -1 * w2; //1437.00483871323 = negArea(1,32)
assign w3 = w4 - w1; //2331.80632626618 = subArea(2,32)
assign w32 = w1 << 5; //shl(5,36)
assign w32_ = -1 * w32; //1437.00483871323 = negArea(5,36)
assign w378 = w189 << 1; //shl(1,39)
assign w378_ = -1 * w378; //1762.99204911029 = negArea(1,39)
assign w4 = w1 << 2; //shl(2,32)
assign w5 = w1 + w4; //2195.42405790882 = adderArea(2,33)
assign Y[0] = w2_[39:8]; //BitwidthUsed(0, 24)
assign Y[1] = w0[39:8]; //BitwidthUsed(none)
assign Y[2] = w32_[39:8]; //BitwidthUsed(0, 28)
assign Y[3] = w0[39:8]; //BitwidthUsed(none)
assign Y[4] = w179_[39:8]; //BitwidthUsed(0, 31)
assign Y[5] = w0[39:8]; //BitwidthUsed(none)
assign Y[6] = w378_[39:8]; //BitwidthUsed(0, 31)
assign Y[7] = w0[39:8]; //BitwidthUsed(none)
//IIR_filter_firBlock_right_MultiplyBlock area estimate = 16402.4783787809;
endmodule //IIR_filter_firBlock_right_MultiplyBlock
module IIR_filter_firBlock_right (
X,
clk,
Y,
reset
);
// Port mode declarations:
input [31:0] X;
input clk;
output [31:0] Y;
input reset;
//registerOut
reg [31:0] Y;
wire [31:0] Y_in;
always@(posedge clk or negedge reset) begin
if(~reset) begin
Y <= 32'h00000000;
end else begin
Y <= Y_in;
end
end
wire [31:0] multProducts [0:7];
IIR_filter_firBlock_right_MultiplyBlock my_IIR_filter_firBlock_right_MultiplyBlock(
.X(X),
.Y1(multProducts[0]),
.Y2(multProducts[1]),
.Y3(multProducts[2]),
.Y4(multProducts[3]),
.Y5(multProducts[4]),
.Y6(multProducts[5]),
.Y7(multProducts[6]),
.Y8(multProducts[7])
);
reg [31:0] firStep[0:6];
always@(posedge clk or negedge reset) begin
if(~reset) begin
firStep[0] <= 32'h00000000;
firStep[1] <= 32'h00000000;
firStep[2] <= 32'h00000000;
firStep[3] <= 32'h00000000;
firStep[4] <= 32'h00000000;
firStep[5] <= 32'h00000000;
firStep[6] <= 32'h00000000;
end
else begin
firStep[0] <= multProducts[0]; // 2448.23046908235 = flop(0, 31)
firStep[1] <= firStep[0] + multProducts[1]; // 2448.23046908235 = flop(0, 31) + adder(none)
firStep[2] <= firStep[1] + multProducts[2]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[3] <= firStep[2] + multProducts[3]; // 2448.23046908235 = flop(0, 31) + adder(none)
firStep[4] <= firStep[3] + multProducts[4]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[5] <= firStep[4] + multProducts[5]; // 2448.23046908235 = flop(0, 31) + adder(none)
firStep[6] <= firStep[5] + multProducts[6]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
end
end
assign Y_in = firStep[6]+ multProducts[7];// 0 = adder(none)
//IIR_filter_firBlock_right area estimate = 42574.5943051662;
endmodule //IIR_filter_firBlock_right
module IIR_filter (
inData,
clk,
outData,
reset
);
// Port mode declarations:
input [31:0] inData;
input clk;
output [31:0] outData;
input reset;
//registerIn
reg [31:0] inData_in;
always@(posedge clk or negedge reset) begin
if(~reset) begin
inData_in <= 32'h00000000;
end else begin
inData_in <= inData;
end
end
//registerOut
reg [31:0] outData;
wire [31:0] outData_in;
always@(posedge clk or negedge reset) begin
if(~reset) begin
outData <= 32'h00000000;
end else begin
outData <= outData_in;
end
end
wire [31:0] leftOut, rightOut;
IIR_filter_firBlock_left my_IIR_filter_firBlock_left(
.X(inData_in),
.Y(leftOut),
.clk(clk),
.reset(reset)
);
IIR_filter_firBlock_right my_IIR_filter_firBlock_right(
.X(outData_in),
.Y(rightOut),
.clk(clk),
.reset(reset)
);
assign outData_in = leftOut + rightOut; // adder(32)
//IIR_filter area estimate = 105716.320536651;
endmodule //IIR_filter
|
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : iir_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-IIR core
//
module iir_top(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
wb_ack_o, wb_err_o, wb_dat_o,
wb_clk_i, wb_rst_i, int_o
);
parameter dw = 32;
parameter aw = 32;
input [aw-1:0] wb_adr_i;
input wb_cyc_i;
input [dw-1:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_stb_i;
input wb_we_i;
output wb_ack_o;
output wb_err_o;
output reg [dw-1:0] wb_dat_o;
output int_o;
input wb_clk_i;
input wb_rst_i;
assign wb_ack_o = 1'b1;
assign wb_err_o = 1'b0;
assign int_o = 1'b0;
// Internal registers
reg next;
reg [31:0] dataX [0:31];
reg [31:0] dataY [0:31];
reg [5:0] xSel=6'b0;
reg [5:0] ySel=6'b0;
reg [5:0] count;
wire [31:0] dataIn, dataOut, data_Out;
reg [31:0] data_In_data, data_In_addr, data_Out_addr;
reg data_valid, data_In_write;
wire next_out;
// Implement MD5 I/O memory map interface
// Write side
always @(posedge wb_clk_i)
begin
if(wb_rst_i)
begin
next <= 0;
data_In_write <= 0;
data_In_addr <= 0;
data_In_data <= 0;
end
else if(wb_stb_i & wb_we_i)
case(wb_adr_i[5:2])
0:
next <= wb_dat_i[0];
1:
data_In_write <= wb_dat_i[0];
2:
data_In_addr <= wb_dat_i;
3:
data_In_data <= wb_dat_i;
4:
data_Out_addr <= wb_dat_i;
default:
;
endcase
end // always @ (posedge wb_clk_i)
// Implement MD5 I/O memory map interface
// Read side
always @(*)
begin
case(wb_adr_i[5:2])
0:
wb_dat_o = {31'b0, next};
1:
wb_dat_o = {31'b0, data_In_write};
2:
wb_dat_o = data_In_addr;
3:
wb_dat_o = data_In_data;
4:
wb_dat_o = data_Out_addr;
5:
wb_dat_o = data_Out;
6:
wb_dat_o = {31'b0, data_valid};
default:
wb_dat_o = 32'b0;
endcase
end // always @ (*)
IIR_filter IIR_filter(
.clk(wb_clk_i),
.reset(~wb_rst_i),
.inData(dataIn),
.outData(dataOut));
reg data_In_write_r;
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
data_In_write_r <= 0;
else
data_In_write_r <= data_In_write;
end
wire data_In_write_posedge = data_In_write & ~data_In_write_r;
reg [15:0] i;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
for (i = 0; i < 32; i = i + 1)
dataX[i] <= 0;
else
dataX[data_In_addr] <= data_In_data;
end
assign data_Out = dataY[data_Out_addr];
reg next_r;
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
next_r <= 0;
else
next_r <= next;
end
wire next_posedge = next & ~next_r;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
xSel <= 0;
else if(next_posedge)
xSel <= 6'h00;
else if(xSel<6'b100000)
xSel <= xSel + 1;
end
assign dataIn = (xSel<6'b100000) ? dataX[xSel] : 32'b0;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
count <= 0;
else if(next_posedge)
begin
count <= 6'h00;
end
else if(xSel<4'b1010)
begin
count <= count +1;
end
end
assign next_out = (count == 4'b1000);
reg next_out_r;
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
next_out_r <= 0;
else
next_out_r <= next_out;
end
wire next_out_posedge = next_out & ~next_out_r;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i) begin
ySel <= 0;
for (i = 0; i < 32; i = i + 1)
dataY[i] <= 0;
end else if(next_out_posedge)
begin
ySel <= 6'h00;
end
else if(ySel<6'b100000)
begin
ySel <= ySel +1;
dataY[ySel] = dataOut;
end
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
data_valid <= 0;
else if(next_posedge)
begin
data_valid <= 0;
end
else if(next_out_posedge)
begin
data_valid <= 1;
end
end
endmodule
|
/* Copyright (c) 2016-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* ============================================================================
*
* Configuration struct
*
* This is the static configuration struct. It contains all global configuration
* settings and is propagated through the hierarchy.
*
* There are two struct: The base_config_t struct contains all configuration
* settings. It is used to setup the system. The config_t struct contains some
* extra settings, which are derived from the base settings. You can call the
* function derive_config to convert a base_config_t struct into a config_t.
*
* When you add a base variable you need to add it at three positions:
*
* - In base_config_t
* - In config_t
* - The copy operation in derive_config
*
* If it is a derived setting, you only need to add it to the latter two.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
package noc_soc_config;
import noc_soc_functions::*;
typedef enum { EXTERNAL, PLAIN } lmem_style_t;
typedef struct packed {
integer NR_MASTERS;
integer NR_SLAVES;
integer ID;
logic ENABLE_S0;
integer S0_BASE;
integer S0_SIZE;
logic ENABLE_S1;
integer S1_BASE;
integer S1_SIZE;
logic ENABLE_S2;
integer S2_BASE;
integer S2_SIZE;
logic ENABLE_S3;
integer S3_BASE;
integer S3_SIZE;
logic ENABLE_S4;
integer S4_BASE;
integer S4_SIZE;
logic ENABLE_S5;
integer S5_BASE;
integer S5_SIZE;
logic ENABLE_S6;
integer S6_BASE;
integer S6_SIZE;
logic ENABLE_S7;
integer S7_BASE;
integer S7_SIZE;
logic ENABLE_S8;
integer S8_BASE;
integer S8_SIZE;
logic ENABLE_S9;
integer S9_BASE;
integer S9_SIZE;
// System configuration
integer NUMTILES;
integer NUMCTS;
logic [63:0][15:0] CTLIST;
integer CORES_PER_TILE;
integer GMEM_SIZE;
integer GMEM_TILE;
// NoC-related configuration
logic NOC_ENABLE_VCHANNELS;
// -> derived
integer NOC_FLIT_WIDTH;
integer NOC_CHANNELS;
integer FLIT_WIDTH;
integer CHANNELS;
integer VCHANNELS;
integer BUFFER_SIZE_IN;
integer BUFFER_SIZE_OUT;
integer DESTS;
integer ROUTES;
// Tile configuration
integer LMEM_SIZE;
lmem_style_t LMEM_STYLE;
logic ENABLE_BOOTROM;
integer BOOTROM_SIZE;
logic ENABLE_DM;
integer DM_BASE;
integer DM_SIZE;
logic ENABLE_PGAS;
integer PGAS_BASE;
integer PGAS_SIZE;
// Network adapter configuration
logic NA_ENABLE_MPSIMPLE;
logic NA_ENABLE_DMA;
logic NA_DMA_GENIRQ;
integer NA_DMA_ENTRIES;
// Debug configuration
logic USE_DEBUG;
logic DEBUG_STM;
logic DEBUG_CTM;
integer DEBUG_SUBNET_BITS;
integer DEBUG_LOCAL_SUBNET;
integer DEBUG_ROUTER_BUFFER_SIZE;
integer DEBUG_MAX_PKT_LEN;
} base_config_t;
typedef struct packed {
logic ENABLE_S0;
integer S0_BASE;
integer S0_SIZE;
integer S0_RANGE_WIDTH;
integer S0_RANGE_MATCH;
logic ENABLE_S1;
integer S1_BASE;
integer S1_SIZE;
integer S1_RANGE_WIDTH;
integer S1_RANGE_MATCH;
logic ENABLE_S2;
integer S2_BASE;
integer S2_SIZE;
integer S2_RANGE_WIDTH;
integer S2_RANGE_MATCH;
logic ENABLE_S3;
integer S3_BASE;
integer S3_SIZE;
integer S3_RANGE_WIDTH;
integer S3_RANGE_MATCH;
logic ENABLE_S4;
integer S4_BASE;
integer S4_SIZE;
integer S4_RANGE_WIDTH;
integer S4_RANGE_MATCH;
logic ENABLE_S5;
integer S5_BASE;
integer S5_SIZE;
integer S5_RANGE_WIDTH;
integer S5_RANGE_MATCH;
logic ENABLE_S6;
integer S6_BASE;
integer S6_SIZE;
integer S6_RANGE_WIDTH;
integer S6_RANGE_MATCH;
logic ENABLE_S7;
integer S7_BASE;
integer S7_SIZE;
integer S7_RANGE_WIDTH;
integer S7_RANGE_MATCH;
logic ENABLE_S8;
integer S8_BASE;
integer S8_SIZE;
integer S8_RANGE_WIDTH;
integer S8_RANGE_MATCH;
logic ENABLE_S9;
integer S9_BASE;
integer S9_SIZE;
integer S9_RANGE_WIDTH;
integer S9_RANGE_MATCH;
integer NR_MASTERS;
integer NR_SLAVES;
integer ID;
// System configuration
integer NUMTILES;
integer NUMCTS;
logic [63:0][15:0] CTLIST;
integer CORES_PER_TILE;
integer GMEM_SIZE;
integer GMEM_TILE;
// -> derived
integer TOTAL_NUM_CORES;
// NoC-related configuration
logic NOC_ENABLE_VCHANNELS;
// -> derived
integer NOC_FLIT_WIDTH;
integer NOC_CHANNELS;
integer FLIT_WIDTH;
integer CHANNELS;
integer VCHANNELS;
integer BUFFER_SIZE_IN;
integer BUFFER_SIZE_OUT;
integer DESTS;
integer ROUTES;
// Tile configuration
integer LMEM_SIZE;
lmem_style_t LMEM_STYLE;
logic ENABLE_BOOTROM;
integer BOOTROM_SIZE;
logic ENABLE_DM;
integer DM_BASE;
integer DM_SIZE;
logic ENABLE_PGAS;
integer DM_RANGE_WIDTH;
integer DM_RANGE_MATCH;
integer PGAS_BASE;
integer PGAS_SIZE;
integer PGAS_RANGE_WIDTH;
integer PGAS_RANGE_MATCH;
// Network adapter configuration
logic NA_ENABLE_MPSIMPLE;
logic NA_ENABLE_DMA;
logic NA_DMA_GENIRQ;
integer NA_DMA_ENTRIES;
// Debug configuration
logic USE_DEBUG;
logic DEBUG_STM;
logic DEBUG_CTM;
integer DEBUG_SUBNET_BITS;
integer DEBUG_LOCAL_SUBNET;
integer DEBUG_ROUTER_BUFFER_SIZE;
integer DEBUG_MAX_PKT_LEN;
// -> derived
integer DEBUG_MODS_PER_CORE;
integer DEBUG_MODS_PER_TILE;
integer DEBUG_NUM_MODS;
} config_t;
function config_t derive_config(base_config_t conf);
derive_config.ENABLE_S0 = conf.ENABLE_S0;
derive_config.S0_BASE = conf.S0_BASE;
derive_config.S0_SIZE = conf.S0_SIZE;
derive_config.ENABLE_S1 = conf.ENABLE_S1;
derive_config.S1_BASE = conf.S1_BASE;
derive_config.S1_SIZE = conf.S1_SIZE;
derive_config.ENABLE_S2 = conf.ENABLE_S2;
derive_config.S2_BASE = conf.S2_BASE;
derive_config.S2_SIZE = conf.S2_SIZE;
derive_config.ENABLE_S3 = conf.ENABLE_S3;
derive_config.S3_BASE = conf.S3_BASE;
derive_config.S3_SIZE = conf.S3_SIZE;
derive_config.ENABLE_S4 = conf.ENABLE_S4;
derive_config.S4_BASE = conf.S4_BASE;
derive_config.S4_SIZE = conf.S4_SIZE;
derive_config.ENABLE_S5 = conf.ENABLE_S5;
derive_config.S5_BASE = conf.S5_BASE;
derive_config.S5_SIZE = conf.S5_SIZE;
derive_config.ENABLE_S6 = conf.ENABLE_S6;
derive_config.S6_BASE = conf.S6_BASE;
derive_config.S6_SIZE = conf.S6_SIZE;
derive_config.ENABLE_S7 = conf.ENABLE_S7;
derive_config.S7_BASE = conf.S7_BASE;
derive_config.S7_SIZE = conf.S7_SIZE;
derive_config.ENABLE_S8 = conf.ENABLE_S8;
derive_config.S8_BASE = conf.S8_BASE;
derive_config.S8_SIZE = conf.S8_SIZE;
derive_config.ENABLE_S9 = conf.ENABLE_S9;
derive_config.S9_BASE = conf.S9_BASE;
derive_config.S9_SIZE = conf.S9_SIZE;
derive_config.S0_RANGE_WIDTH = 1;
derive_config.S0_RANGE_MATCH = 1'b0;
derive_config.S1_RANGE_WIDTH = 1;
derive_config.S1_RANGE_MATCH = 1'b0;
//derive_config.S2_RANGE_WIDTH = 1;
//derive_config.S2_RANGE_MATCH = 1'b0;
//derive_config.S3_RANGE_WIDTH = 1;
//derive_config.S3_RANGE_MATCH = 1'b0;
// derive_config.S4_RANGE_WIDTH = 1;
//derive_config.S4_RANGE_MATCH = 1'b0;
// derive_config.S5_RANGE_WIDTH = 1;
// derive_config.S5_RANGE_MATCH = 1'b0;
// derive_config.S6_RANGE_WIDTH = 1;
// derive_config.S6_RANGE_MATCH = 1'b0;
// derive_config.S7_RANGE_WIDTH = 1;
// derive_config.S7_RANGE_MATCH = 1'b0;
// derive_config.S8_RANGE_WIDTH = 1;
// derive_config.S8_RANGE_MATCH = 1'b0;
// derive_config.S9_RANGE_WIDTH = 1;
// derive_config.S9_RANGE_MATCH = 1'b0;
derive_config.S1_RANGE_WIDTH = conf.ENABLE_S1 ? 32-clog2_width(conf.S1_SIZE) : 1;
derive_config.S1_RANGE_MATCH = conf.S1_BASE >> (32-derive_config.S1_RANGE_WIDTH);
derive_config.S2_RANGE_WIDTH = conf.ENABLE_S2 ? 32-clog2_width(conf.S2_SIZE) : 1;
derive_config.S2_RANGE_MATCH = conf.S2_BASE >> (32-derive_config.S2_RANGE_WIDTH);
derive_config.S3_RANGE_WIDTH = conf.ENABLE_S3 ? 32-clog2_width(conf.S3_SIZE) : 1;
derive_config.S3_RANGE_MATCH = conf.S3_BASE >> (32-derive_config.S3_RANGE_WIDTH);
derive_config.S4_RANGE_WIDTH = conf.ENABLE_S4 ? 32-clog2_width(conf.S4_SIZE) : 1;
derive_config.S4_RANGE_MATCH = conf.S4_BASE >> (32-derive_config.S4_RANGE_WIDTH);
derive_config.S5_RANGE_WIDTH = conf.ENABLE_S5 ? 32-clog2_width(conf.S5_SIZE) : 1;
derive_config.S5_RANGE_MATCH = conf.S5_BASE >> (32-derive_config.S5_RANGE_WIDTH);
derive_config.S6_RANGE_WIDTH = conf.ENABLE_S6 ? 32-clog2_width(conf.S6_SIZE) : 1;
derive_config.S6_RANGE_MATCH = conf.S6_BASE >> (32-derive_config.S6_RANGE_WIDTH);
derive_config.S7_RANGE_WIDTH = conf.ENABLE_S7 ? 32-clog2_width(conf.S7_SIZE) : 1;
derive_config.S7_RANGE_MATCH = conf.S7_BASE >> (32-derive_config.S7_RANGE_WIDTH);
derive_config.S8_RANGE_WIDTH = conf.ENABLE_S8 ? 32-clog2_width(conf.S8_SIZE) : 1;
derive_config.S8_RANGE_MATCH = conf.S8_BASE >> (32-derive_config.S8_RANGE_WIDTH);
derive_config.S9_RANGE_WIDTH = conf.ENABLE_S9 ? 32-clog2_width(conf.S9_SIZE) : 1;
derive_config.S9_RANGE_MATCH = conf.S9_BASE >> (32-derive_config.S9_RANGE_WIDTH);
derive_config.S0_RANGE_WIDTH = conf.ENABLE_S0 ? 32-clog2_width(conf.S0_SIZE) : 1;
derive_config.S0_RANGE_MATCH = conf.S0_BASE >> (32-derive_config.S0_RANGE_WIDTH);
//derive_config.S1_RANGE_WIDTH = conf.ENABLE_S1 ? 32-clog2_width(conf.S1_SIZE) : 1;
//derive_config.S1_RANGE_MATCH = conf.S1_BASE >> (32-derive_config.S1_RANGE_WIDTH);
// derive_config.S2_RANGE_WIDTH = conf.ENABLE_S2 ? 32-clog2_width(conf.S2_SIZE) : 1;
// derive_config.S2_RANGE_MATCH = conf.S2_BASE >> (32-derive_config.S2_RANGE_WIDTH);
// derive_config.S3_RANGE_WIDTH = conf.ENABLE_S3 ? 32-clog2_width(conf.S3_SIZE) : 1;
// derive_config.S3_RANGE_MATCH = conf.S3_BASE >> (32-derive_config.S3_RANGE_WIDTH);
// derive_config.S4_RANGE_WIDTH = conf.ENABLE_S4 ? 32-clog2_width(conf.S4_SIZE) : 1;
// derive_config.S4_RANGE_MATCH = conf.S4_BASE >> (32-derive_config.S4_RANGE_WIDTH);
//derive_config.S5_RANGE_WIDTH = conf.ENABLE_S5 ? 32-clog2_width(conf.S5_SIZE) : 1;
// derive_config.S5_RANGE_MATCH = conf.S5_BASE >> (32-derive_config.S5_RANGE_WIDTH);
// derive_config.S6_RANGE_WIDTH = conf.ENABLE_S6 ? 32-clog2_width(conf.S6_SIZE) : 1;
// derive_config.S6_RANGE_MATCH = conf.S6_BASE >> (32-derive_config.S6_RANGE_WIDTH);
// derive_config.S7_RANGE_WIDTH = conf.ENABLE_S7 ? 32-clog2_width(conf.S7_SIZE) : 1;
//derive_config.S7_RANGE_MATCH = conf.S7_BASE >> (32-derive_config.S7_RANGE_WIDTH);
//derive_config.S8_RANGE_WIDTH = conf.ENABLE_S8 ? 32-clog2_width(conf.S8_SIZE) : 1;
//derive_config.S8_RANGE_MATCH = conf.S8_BASE >> (32-derive_config.S8_RANGE_WIDTH);
//derive_config.S9_RANGE_WIDTH = conf.ENABLE_S9 ? 32-clog2_width(conf.S9_SIZE) : 1;
//derive_config.S9_RANGE_MATCH = conf.S9_BASE >> (32-derive_config.S9_RANGE_WIDTH);
// Copy the basic parameters
derive_config.NUMTILES = conf.NUMTILES;
derive_config.NUMCTS = conf.NUMCTS;
derive_config.CTLIST = conf.CTLIST;
derive_config.CORES_PER_TILE = conf.CORES_PER_TILE;
derive_config.GMEM_SIZE = conf.GMEM_SIZE;
derive_config.GMEM_TILE = conf.GMEM_TILE;
derive_config.NOC_ENABLE_VCHANNELS = conf.NOC_ENABLE_VCHANNELS;
derive_config.LMEM_SIZE = conf.LMEM_SIZE;
derive_config.LMEM_STYLE = conf.LMEM_STYLE;
derive_config.ENABLE_BOOTROM = conf.ENABLE_BOOTROM;
derive_config.BOOTROM_SIZE = conf.BOOTROM_SIZE;
derive_config.ENABLE_DM = conf.ENABLE_DM;
derive_config.DM_BASE = conf.DM_BASE;
derive_config.DM_SIZE = conf.DM_SIZE;
derive_config.ENABLE_PGAS = conf.ENABLE_PGAS;
derive_config.PGAS_BASE = conf.PGAS_BASE;
derive_config.PGAS_SIZE = conf.PGAS_SIZE;
derive_config.NA_ENABLE_MPSIMPLE = conf.NA_ENABLE_MPSIMPLE;
derive_config.NA_ENABLE_DMA = conf.NA_ENABLE_DMA;
derive_config.NA_DMA_GENIRQ = conf.NA_DMA_GENIRQ;
derive_config.NA_DMA_ENTRIES = conf.NA_DMA_ENTRIES;
derive_config.USE_DEBUG = conf.USE_DEBUG;
derive_config.DEBUG_STM = conf.DEBUG_STM;
derive_config.DEBUG_CTM = conf.DEBUG_CTM;
derive_config.DEBUG_SUBNET_BITS = conf.DEBUG_SUBNET_BITS;
derive_config.DEBUG_LOCAL_SUBNET = conf.DEBUG_LOCAL_SUBNET;
derive_config.DEBUG_ROUTER_BUFFER_SIZE = conf.DEBUG_ROUTER_BUFFER_SIZE;
derive_config.DEBUG_MAX_PKT_LEN = conf.DEBUG_MAX_PKT_LEN;
// Derive the other parameters
derive_config.TOTAL_NUM_CORES = conf.NUMCTS * conf.CORES_PER_TILE;
derive_config.DM_RANGE_WIDTH = conf.ENABLE_DM ? 32-clog2_width(conf.DM_SIZE) : 1;
derive_config.DM_RANGE_MATCH = conf.DM_BASE >> (32-derive_config.DM_RANGE_WIDTH);
derive_config.PGAS_RANGE_WIDTH = conf.ENABLE_PGAS ? 32-clog2_width(conf.PGAS_SIZE) : 1;
derive_config.PGAS_RANGE_MATCH = conf.PGAS_BASE >> (32-derive_config.PGAS_RANGE_WIDTH);
derive_config.DEBUG_MODS_PER_CORE = (int'(conf.DEBUG_STM) + int'(conf.DEBUG_CTM)) * int'(conf.USE_DEBUG);
derive_config.DEBUG_MODS_PER_TILE = conf.USE_DEBUG *
(1 /* MAM */
+ derive_config.DEBUG_MODS_PER_CORE * conf.CORES_PER_TILE);
derive_config.DEBUG_NUM_MODS = conf.USE_DEBUG *
(1 /* SCM */
+ conf.NUMCTS * derive_config.DEBUG_MODS_PER_TILE);
// Those are supposed to be variables, but are constant at least for now
// derive_config.CHANNELS = 2;
// derive_config.FLIT_WIDTH = 32;
endfunction // DERIVE_CONFIG
localparam base_config_t
BASE_CONFIG = '{
ENABLE_S0:1,
S0_BASE:32'h0000_0000,
S0_SIZE: 32,
ENABLE_S1:1,
S1_BASE:32'h9000_0000,
S1_SIZE: 32,
ENABLE_S2:1,
S2_BASE:32'h9300_0000,
S2_SIZE:32,
ENABLE_S3:1,
S3_BASE:32'h9400_0000,
S3_SIZE:32,
ENABLE_S4:1,
S4_BASE:32'h9500_0000,
S4_SIZE:32,
ENABLE_S5:1,
S5_BASE:32'h9600_0000,
S5_SIZE:32,
ENABLE_S6:1,
S6_BASE:32'h9700_0000,
S6_SIZE:32,
ENABLE_S7:1,
S7_BASE:32'h9800_0000,
S7_SIZE:32,
ENABLE_S8:1,
S8_BASE:32'h9900_0000,
S8_SIZE:32,
ENABLE_S9:1,
S9_BASE:32'h9A00_0000,
S9_SIZE:32,
NR_MASTERS:1,
NR_SLAVES:9,
ID: 10,
NUMTILES: 10,
NUMCTS: 10,
CTLIST: 0,
CORES_PER_TILE: 1,
GMEM_SIZE: 'x,
GMEM_TILE: 'x,
// NoC-related configuration
NOC_ENABLE_VCHANNELS:1,
// -> derived
NOC_FLIT_WIDTH: 32,
NOC_CHANNELS:2,
FLIT_WIDTH:32,
CHANNELS:2,
VCHANNELS:2,
BUFFER_SIZE_IN: 4,
BUFFER_SIZE_OUT: 4,
DESTS: 32,
ROUTES: 320,
// Tile configuration
LMEM_SIZE: 'x,
LMEM_STYLE: PLAIN,
ENABLE_BOOTROM:0,
BOOTROM_SIZE:'x,
ENABLE_DM:0,
DM_BASE:'x,
DM_SIZE:'x,
ENABLE_PGAS:0,
PGAS_BASE:'x,
PGAS_SIZE:'x,
// Network adapter configuration
NA_ENABLE_MPSIMPLE:1,
NA_ENABLE_DMA:1,
NA_DMA_GENIRQ: 1,
NA_DMA_ENTRIES:'x,
// Debug configuration
USE_DEBUG:0,
DEBUG_STM:0,
DEBUG_CTM:0,
DEBUG_SUBNET_BITS: 'x,
DEBUG_LOCAL_SUBNET: 'x,
DEBUG_ROUTER_BUFFER_SIZE: 'x,
DEBUG_MAX_PKT_LEN: 'x
};
localparam config_t CONFIG = derive_config(BASE_CONFIG);
endpackage // optimsoc
|
/* Copyright (c) 2013 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* System-wide definitions for an OpTiMSoC system instance.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
// Number of virtual channels
`define VCHANNELS 3
// Assign virtual channels to services
`define VCHANNEL_LSU_REQ 'x
`define VCHANNEL_LSU_RESP 'x
`define VCHANNEL_DMA_REQ 0
`define VCHANNEL_DMA_RESP 1
`define VCHANNEL_MPSIMPLE 2
`define OPTIMSOC_XDIM 2
`define OPTIMSOC_YDIM 2
`define OPTIMSOC_SRAM_IMPLEMENTATION "PLAIN"
`define OPTIMSOC_SRAM_VALIDATE_ADDRESS 1
|
/* Copyright (c) 2013-2018 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* ============================================================================
*
* Utility functions
*
* Author(s):
* Philipp Wagner <[email protected]>
* Stefan Wallentowitz <[email protected]>
*/
package noc_soc_functions;
/**
* Math function: $clog2 as specified in Verilog-2005
*
* clog2 = 0 for value == 0
* ceil(log2(value)) for value >= 1
*
* This implementation is a synthesizable variant of the $clog2 function as
* specified in the Verilog-2005 standard (IEEE 1364-2005).
*
* To quote the standard:
* The system function $clog2 shall return the ceiling of the log
* base 2 of the argument (the log rounded up to an integer
* value). The argument can be an integer or an arbitrary sized
* vector value. The argument shall be treated as an unsigned
* value, and an argument value of 0 shall produce a result of 0.
*/
function automatic integer clog2;
input integer value;
begin
value = value - 1;
for (clog2 = 0; value > 0; clog2 = clog2 + 1) begin
value = value >> 1;
end
end
endfunction
/**
* Math function: enhanced clog2 function
*
* 0 for value == 0
* clog2_width = 1 for value == 1
* ceil(log2(value)) for value > 1
*
*
* This function is a variant of the clog2() function, which returns 1 if the
* input value is 1. In all other cases it behaves exactly like clog2().
* This is useful to define registers which are wide enough to contain
* "value" values.
*
* Example 1:
* parameter ITEMS = 1;
* localparam ITEMS_WIDTH = clog2_width(ITEMS); // 1
* reg [ITEMS_WIDTH-1:0] item_register; // items_register is now [0:0]
*
* Example 2:
* parameter ITEMS = 64;
* localparam ITEMS_WIDTH = clog2_width(ITEMS); // 6
* reg [ITEMS_WIDTH-1:0] item_register; // items_register is now [5:0]
*
* Note: I if you want to store the number "value" inside a
* register, you need a register with size clog2(value + 1), since
* you also need to store the number 0.
*
* Example 3:
* reg [clog2_width(64) - 1 : 0] store_64_items; // width is [5:0]
* reg [clog2_width(64 + 1) - 1 : 0] store_number_64; // width is [6:0]
*/
function automatic integer clog2_width;
input integer value;
begin
if (value == 1) begin
clog2_width = 1;
end else begin
clog2_width = clog2(value);
end
end
endfunction
function automatic [23:0] index2string;
input integer index;
integer hundreds;
integer tens;
integer ones;
begin
hundreds = index / 100;
tens = (index - (hundreds * 100)) / 10;
ones = (index - (hundreds * 100) - (tens * 10));
index2string[23:16] = hundreds[7:0] + 8'd48;
index2string[15:8] = tens[7:0] + 8'd48;
index2string[7:0] = ones[7:0] + 8'd48;
end
endfunction
endpackage // functions
|
/* Copyright (c) 2016-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* ============================================================================
*
* Configuration struct
*
* This is the static configuration struct. It contains all global configuration
* settings and is propagated through the hierarchy.
*
* There are two struct: The base_config_t struct contains all configuration
* settings. It is used to setup the system. The config_t struct contains some
* extra settings, which are derived from the base settings. You can call the
* function derive_config to convert a base_config_t struct into a config_t.
*
* When you add a base variable you need to add it at three positions:
*
* - In base_config_t
* - In config_t
* - The copy operation in derive_config
*
* If it is a derived setting, you only need to add it to the latter two.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
package optimsoc_config;
import optimsoc_functions::*;
typedef enum { EXTERNAL, PLAIN } lmem_style_t;
typedef struct packed {
// System configuration
integer NUMTILES;
integer NUMCTS;
logic [63:0][15:0] CTLIST;
integer CORES_PER_TILE;
integer GMEM_SIZE;
integer GMEM_TILE;
// NoC-related configuration
logic NOC_ENABLE_VCHANNELS;
// Tile configuration
integer LMEM_SIZE;
lmem_style_t LMEM_STYLE;
logic ENABLE_BOOTROM;
integer BOOTROM_SIZE;
logic ENABLE_DM;
integer DM_BASE;
integer DM_SIZE;
logic ENABLE_PGAS;
integer PGAS_BASE;
integer PGAS_SIZE;
// Network adapter configuration
logic NA_ENABLE_MPSIMPLE;
logic NA_ENABLE_DMA;
logic NA_DMA_GENIRQ;
integer NA_DMA_ENTRIES;
// Debug configuration
logic USE_DEBUG;
logic DEBUG_STM;
logic DEBUG_CTM;
integer DEBUG_SUBNET_BITS;
integer DEBUG_LOCAL_SUBNET;
integer DEBUG_ROUTER_BUFFER_SIZE;
integer DEBUG_MAX_PKT_LEN;
} base_config_t;
typedef struct packed {
// System configuration
integer NUMTILES;
integer NUMCTS;
logic [63:0][15:0] CTLIST;
integer CORES_PER_TILE;
integer GMEM_SIZE;
integer GMEM_TILE;
// -> derived
integer TOTAL_NUM_CORES;
// NoC-related configuration
logic NOC_ENABLE_VCHANNELS;
// -> derived
integer NOC_FLIT_WIDTH;
integer NOC_CHANNELS;
// Tile configuration
integer LMEM_SIZE;
lmem_style_t LMEM_STYLE;
logic ENABLE_BOOTROM;
integer BOOTROM_SIZE;
logic ENABLE_DM;
integer DM_BASE;
integer DM_SIZE;
logic ENABLE_PGAS;
integer DM_RANGE_WIDTH;
integer DM_RANGE_MATCH;
integer PGAS_BASE;
integer PGAS_SIZE;
integer PGAS_RANGE_WIDTH;
integer PGAS_RANGE_MATCH;
// Network adapter configuration
logic NA_ENABLE_MPSIMPLE;
logic NA_ENABLE_DMA;
logic NA_DMA_GENIRQ;
integer NA_DMA_ENTRIES;
// Debug configuration
logic USE_DEBUG;
logic DEBUG_STM;
logic DEBUG_CTM;
integer DEBUG_SUBNET_BITS;
integer DEBUG_LOCAL_SUBNET;
integer DEBUG_ROUTER_BUFFER_SIZE;
integer DEBUG_MAX_PKT_LEN;
// -> derived
integer DEBUG_MODS_PER_CORE;
integer DEBUG_MODS_PER_TILE;
integer DEBUG_NUM_MODS;
} config_t;
function config_t derive_config(base_config_t conf);
// Copy the basic parameters
derive_config.NUMTILES = conf.NUMTILES;
derive_config.NUMCTS = conf.NUMCTS;
derive_config.CTLIST = conf.CTLIST;
derive_config.CORES_PER_TILE = conf.CORES_PER_TILE;
derive_config.GMEM_SIZE = conf.GMEM_SIZE;
derive_config.GMEM_TILE = conf.GMEM_TILE;
derive_config.NOC_ENABLE_VCHANNELS = conf.NOC_ENABLE_VCHANNELS;
derive_config.LMEM_SIZE = conf.LMEM_SIZE;
derive_config.LMEM_STYLE = conf.LMEM_STYLE;
derive_config.ENABLE_BOOTROM = conf.ENABLE_BOOTROM;
derive_config.BOOTROM_SIZE = conf.BOOTROM_SIZE;
derive_config.ENABLE_DM = conf.ENABLE_DM;
derive_config.DM_BASE = conf.DM_BASE;
derive_config.DM_SIZE = conf.DM_SIZE;
derive_config.ENABLE_PGAS = conf.ENABLE_PGAS;
derive_config.PGAS_BASE = conf.PGAS_BASE;
derive_config.PGAS_SIZE = conf.PGAS_SIZE;
derive_config.NA_ENABLE_MPSIMPLE = conf.NA_ENABLE_MPSIMPLE;
derive_config.NA_ENABLE_DMA = conf.NA_ENABLE_DMA;
derive_config.NA_DMA_GENIRQ = conf.NA_DMA_GENIRQ;
derive_config.NA_DMA_ENTRIES = conf.NA_DMA_ENTRIES;
derive_config.USE_DEBUG = conf.USE_DEBUG;
derive_config.DEBUG_STM = conf.DEBUG_STM;
derive_config.DEBUG_CTM = conf.DEBUG_CTM;
derive_config.DEBUG_SUBNET_BITS = conf.DEBUG_SUBNET_BITS;
derive_config.DEBUG_LOCAL_SUBNET = conf.DEBUG_LOCAL_SUBNET;
derive_config.DEBUG_ROUTER_BUFFER_SIZE = conf.DEBUG_ROUTER_BUFFER_SIZE;
derive_config.DEBUG_MAX_PKT_LEN = conf.DEBUG_MAX_PKT_LEN;
// Derive the other parameters
derive_config.TOTAL_NUM_CORES = conf.NUMCTS * conf.CORES_PER_TILE;
derive_config.DM_RANGE_WIDTH = conf.ENABLE_DM ? 32-clog2_width(conf.DM_SIZE) : 1;
derive_config.DM_RANGE_MATCH = conf.DM_BASE >> (32-derive_config.DM_RANGE_WIDTH);
derive_config.PGAS_RANGE_WIDTH = conf.ENABLE_PGAS ? 32-clog2_width(conf.PGAS_SIZE) : 1;
derive_config.PGAS_RANGE_MATCH = conf.PGAS_BASE >> (32-derive_config.PGAS_RANGE_WIDTH);
derive_config.DEBUG_MODS_PER_CORE = (int'(conf.DEBUG_STM) + int'(conf.DEBUG_CTM)) * int'(conf.USE_DEBUG);
derive_config.DEBUG_MODS_PER_TILE = conf.USE_DEBUG *
(1 /* MAM */
+ derive_config.DEBUG_MODS_PER_CORE * conf.CORES_PER_TILE);
derive_config.DEBUG_NUM_MODS = conf.USE_DEBUG *
(1 /* SCM */
+ conf.NUMCTS * derive_config.DEBUG_MODS_PER_TILE);
// Those are supposed to be variables, but are constant at least for now
derive_config.NOC_CHANNELS = 2;
derive_config.NOC_FLIT_WIDTH = 32;
endfunction // DERIVE_CONFIG
endpackage // optimsoc
|
/* Copyright (c) 2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* Constants
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
package optimsoc_constants;
// Maximum packet length
localparam NOC_MAX_LEN = 32;
// NoC packet header
// Mandatory fields
localparam NOC_DEST_MSB = 31;
localparam NOC_DEST_LSB = 27;
localparam NOC_CLASS_MSB = 26;
localparam NOC_CLASS_LSB = 24;
localparam NOC_SRC_MSB = 23;
localparam NOC_SRC_LSB = 19;
// Classes
localparam NOC_CLASS_LSU = 3'h2;
// NoC LSU
localparam NOC_LSU_MSGTYPE_MSB = 18;
localparam NOC_LSU_MSGTYPE_LSB = 16;
localparam NOC_LSU_MSGTYPE_READREQ = 3'h0;
localparam NOC_LSU_SIZE_IDX = 15;
localparam NOC_LSU_SIZE_SINGLE = 0;
localparam NOC_LSU_SIZE_BURST = 1;
endpackage // constants
|
/* Copyright (c) 2013 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* System-wide definitions for an OpTiMSoC system instance.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
// Number of virtual channels
`define VCHANNELS 3
// Assign virtual channels to services
`define VCHANNEL_LSU_REQ 'x
`define VCHANNEL_LSU_RESP 'x
`define VCHANNEL_DMA_REQ 0
`define VCHANNEL_DMA_RESP 1
`define VCHANNEL_MPSIMPLE 2
`define OPTIMSOC_XDIM 2
`define OPTIMSOC_YDIM 2
`define OPTIMSOC_SRAM_IMPLEMENTATION "PLAIN"
`define OPTIMSOC_SRAM_VALIDATE_ADDRESS 1
|
/* Copyright (c) 2013-2018 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* ============================================================================
*
* Utility functions
*
* Author(s):
* Philipp Wagner <[email protected]>
* Stefan Wallentowitz <[email protected]>
*/
package optimsoc_functions;
/**
* Math function: $clog2 as specified in Verilog-2005
*
* clog2 = 0 for value == 0
* ceil(log2(value)) for value >= 1
*
* This implementation is a synthesizable variant of the $clog2 function as
* specified in the Verilog-2005 standard (IEEE 1364-2005).
*
* To quote the standard:
* The system function $clog2 shall return the ceiling of the log
* base 2 of the argument (the log rounded up to an integer
* value). The argument can be an integer or an arbitrary sized
* vector value. The argument shall be treated as an unsigned
* value, and an argument value of 0 shall produce a result of 0.
*/
function automatic integer clog2;
input integer value;
begin
value = value - 1;
for (clog2 = 0; value > 0; clog2 = clog2 + 1) begin
value = value >> 1;
end
end
endfunction
/**
* Math function: enhanced clog2 function
*
* 0 for value == 0
* clog2_width = 1 for value == 1
* ceil(log2(value)) for value > 1
*
*
* This function is a variant of the clog2() function, which returns 1 if the
* input value is 1. In all other cases it behaves exactly like clog2().
* This is useful to define registers which are wide enough to contain
* "value" values.
*
* Example 1:
* parameter ITEMS = 1;
* localparam ITEMS_WIDTH = clog2_width(ITEMS); // 1
* reg [ITEMS_WIDTH-1:0] item_register; // items_register is now [0:0]
*
* Example 2:
* parameter ITEMS = 64;
* localparam ITEMS_WIDTH = clog2_width(ITEMS); // 6
* reg [ITEMS_WIDTH-1:0] item_register; // items_register is now [5:0]
*
* Note: I if you want to store the number "value" inside a
* register, you need a register with size clog2(value + 1), since
* you also need to store the number 0.
*
* Example 3:
* reg [clog2_width(64) - 1 : 0] store_64_items; // width is [5:0]
* reg [clog2_width(64 + 1) - 1 : 0] store_number_64; // width is [6:0]
*/
function automatic integer clog2_width;
input integer value;
begin
if (value == 1) begin
clog2_width = 1;
end else begin
clog2_width = clog2(value);
end
end
endfunction
function automatic [23:0] index2string;
input integer index;
integer hundreds;
integer tens;
integer ones;
begin
hundreds = index / 100;
tens = (index - (hundreds * 100)) / 10;
ones = (index - (hundreds * 100) - (tens * 10));
index2string[23:16] = hundreds[7:0] + 8'd48;
index2string[15:8] = tens[7:0] + 8'd48;
index2string[7:0] = ones[7:0] + 8'd48;
end
endfunction
endpackage // functions
|
//////////////////////////////////////////////////////////////////////
//// ////
//// timescale.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// Defines of the Core ////
//// ////
//// Known problems (limits): ////
//// None ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// Timescale define
`timescale 1ns/10ps
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* Generic round robin arbiter.
*
* (c) 2011-2013 by the author(s)
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*
*/
module lisnoc_arb_rr(/*AUTOARG*/
// Outputs
nxt_gnt,
// Inputs
req, gnt
);
parameter N = 2;
input [N-1:0] req;
input [N-1:0] gnt;
output [N-1:0] nxt_gnt;
reg [N-1:0] mask [0:N-1];
integer i,j;
always @(*) begin
for (i=0;i<N;i=i+1) begin
mask[i] = {N{1'b0}};
if(i>0)
mask[i][i-1] = ~gnt[i-1];
else
mask[i][N-1] = ~gnt[N-1];
for (j=2;j<N;j=j+1) begin
if (i-j>=0)
mask[i][i-j] = mask[i][i-j+1] & ~gnt[i-j];
else if(i-j+1>=0)
mask[i][i-j+N] = mask[i][i-j+1] & ~gnt[i-j+N];
else
mask[i][i-j+N] = mask[i][i-j+N+1] & ~gnt[i-j+N];
end
end
end // always @ (*)
genvar k;
generate
for (k=0;k<N;k=k+1) begin
assign nxt_gnt[k] = (~|(mask[k] & req) & req[k]) | (~|req & gnt[k]);
end
endgenerate
endmodule // lisnoc_arb_rr
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* The wishbone master of the initiator.
*
* (c) 2011-2013 by the author(s)
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*
*/
`include "lisnoc_def.vh"
`include "lisnoc_dma_def.vh"
module lisnoc_dma_initiator_wbreq(/*AUTOARG*/
// Outputs
wb_req_cyc_o, wb_req_stb_o, wb_req_we_o, wb_req_dat_o,
wb_req_adr_o, wb_req_cti_o, wb_req_bte_o, wb_req_sel_o,
req_data_valid, req_data,
// Inputs
clk, rst, wb_req_ack_i, wb_req_dat_i, req_start, req_is_l2r,
req_size, req_laddr, req_data_ready
);
input clk, rst;
input wb_req_ack_i;
output reg wb_req_cyc_o, wb_req_stb_o;
output wb_req_we_o;
input [31:0] wb_req_dat_i;
output [31:0] wb_req_dat_o;
output reg [31:0] wb_req_adr_o;
output reg [2:0] wb_req_cti_o;
output [1:0] wb_req_bte_o;
output [3:0] wb_req_sel_o;
input req_start;
input req_is_l2r;
input [`DMA_REQFIELD_SIZE_WIDTH-3:0] req_size;
input [31:0] req_laddr;
output req_data_valid;
output [31:0] req_data;
input req_data_ready;
//
// Wishbone state machine
//
`define WB_REQ_WIDTH 2
`define WB_REQ_IDLE 2'b00
`define WB_REQ_DATA 2'b01
`define WB_REQ_WAIT 2'b10
// State logic
reg [`WB_REQ_WIDTH-1:0] wb_req_state;
reg [`WB_REQ_WIDTH-1:0] nxt_wb_req_state;
// Counter for the state machine for loaded words
reg [`DMA_REQFIELD_SIZE_WIDTH-3:0] wb_req_count;
reg [`DMA_REQFIELD_SIZE_WIDTH-3:0] nxt_wb_req_count;
/*
* The wishbone data fetch and the NoC interface are seperated by a FIFO.
* This FIFO relaxes problems with bursts and their termination and decouples
* the timing of the NoC side and the wishbone side (in terms of termination).
*/
// The intermediate store a FIFO of three elements
//
// There should be no combinatorial path from input to output, so
// that it takes one cycle before the wishbone interface knows
// about back pressure from the NoC. Additionally, the wishbone
// interface needs one extra cycle for burst termination. The data
// should be stored and not discarded. Finally, there is one
// element in the FIFO that is the normal timing decoupling.
reg [31:0] data_fifo [0:2]; // data storage
wire data_fifo_pop; // NoC pops
reg data_fifo_push; // WB pushes
wire [31:0] data_fifo_out; // Current first element
wire [31:0] data_fifo_in; // Push element
// Shift register for current position (4th bit is full mark)
reg [3:0] data_fifo_pos;
wire data_fifo_empty; // FIFO empty
wire data_fifo_ready; // FIFO accepts new elements
// Connect the fifo signals to the ports
assign data_fifo_pop = req_data_ready;
assign req_data_valid = ~data_fifo_empty;
assign req_data = data_fifo_out;
assign data_fifo_empty = data_fifo_pos[0]; // Empty when pushing to first one
assign data_fifo_out = data_fifo[0]; // First element is out
// FIFO is not ready when back-pressure would result in discarded data,
// that is, we need one store element (high-water).
assign data_fifo_ready = ~|data_fifo_pos[3:2];
// FIFO position pointer logic
always @(posedge clk) begin
if (rst) begin
data_fifo_pos <= 4'b001;
end else begin
if (data_fifo_push & ~data_fifo_pop) begin
// push and no pop
data_fifo_pos <= data_fifo_pos << 1;
end else if (~data_fifo_push & data_fifo_pop) begin
// pop and no push
data_fifo_pos <= data_fifo_pos >> 1;
end else begin
// * no push or pop or
// * both push and pop
data_fifo_pos <= data_fifo_pos;
end
end
end
// FIFO data shifting logic
always @(posedge clk) begin : data_fifo_shift
integer i;
// Iterate all fifo elements, starting from lowest
for (i=0;i<3;i=i+1) begin
if (data_fifo_pop) begin
// when popping data..
if (data_fifo_push & data_fifo_pos[i+1])
// .. and we also push this cycle, we need to check
// whether the pointer was on the next one
data_fifo[i] <= data_fifo_in;
else if (i<2)
// .. otherwise shift if not last
data_fifo[i] <= data_fifo[i+1];
else
// the last stays static
data_fifo[i] <= data_fifo[i];
end else if (data_fifo_push & data_fifo_pos[i]) begin
// when pushing only and this is the current write
// position
data_fifo[i] <= data_fifo_in;
end else begin
// else just keep
data_fifo[i] <= data_fifo[i];
end
end
end
//
// Wishbone interface logic
//
// Statically zero (this interface reads)
assign wb_req_dat_o = 32'h0000_0000;
assign wb_req_we_o = 1'b0;
// We only support full (aligned) word transfers
assign wb_req_sel_o = 4'b1111;
// We only need linear bursts
assign wb_req_bte_o = 2'b00;
// The input to the fifo is the data from the bus
assign data_fifo_in = wb_req_dat_i;
// Next state, wishbone combinatorial signals and counting
always @(*) begin
// Signal defaults
nxt_wb_req_count = wb_req_count;
wb_req_stb_o = 1'b0;
wb_req_cyc_o = 1'b0;
data_fifo_push = 1'b0;
wb_req_adr_o = 32'hx;
wb_req_cti_o = 3'b000;
case (wb_req_state)
`WB_REQ_IDLE: begin
// We are idle'ing
// Always reset counter
nxt_wb_req_count = 0;
if (req_start & req_is_l2r)
// start when new request is handled and it is a L2R
// request. Direct transition to data fetching from bus,
// as the FIFO is always empty at this point.
nxt_wb_req_state = `WB_REQ_DATA;
else
// otherwise keep idle'ing
nxt_wb_req_state = `WB_REQ_IDLE;
end
`WB_REQ_DATA: begin
// We get data from the bus
// Signal cycle and strobe. We do bursts, but don't insert
// wait states, so both of them are always equal.
wb_req_stb_o = 1'b1;
wb_req_cyc_o = 1'b1;
// The address is the base address plus the counter
// Counter counts words, not bytes
wb_req_adr_o = req_laddr + (wb_req_count << 2);
if (~data_fifo_ready | (wb_req_count==req_size-1)) begin
// If fifo gets full next cycle, do cycle termination
wb_req_cti_o = 3'b111;
end else begin
// As long as we can also store the _next_ element in
// the fifo, signal we are in an incrementing burst
wb_req_cti_o = 3'b010;
end
if (wb_req_ack_i) begin
// When this request was successfull..
// increment word counter
nxt_wb_req_count = wb_req_count + 1;
// signal push to data fifo
data_fifo_push = 1'b1;
if (wb_req_count==req_size-1)
// This was the last word
nxt_wb_req_state = `WB_REQ_IDLE;
else if (data_fifo_ready)
// when FIFO can still get data, we stay here
nxt_wb_req_state = `WB_REQ_DATA;
else
// .. otherwise we wait for FIFO to become ready
nxt_wb_req_state = `WB_REQ_WAIT;
end else begin // if (wb_req_ack_i)
// ..otherwise we still wait for the acknowledgement
nxt_wb_req_state = `WB_REQ_DATA;
end
end
`WB_REQ_WAIT: begin
// Waiting for FIFO to accept new data
if (data_fifo_ready)
// FIFO ready, restart burst
nxt_wb_req_state = `WB_REQ_DATA;
else
// wait
nxt_wb_req_state = `WB_REQ_WAIT;
end
default: begin
nxt_wb_req_state = `WB_REQ_IDLE;
end
endcase
end
// Sequential part of the state machine
always @(posedge clk) begin
if (rst) begin
wb_req_state <= `WB_REQ_IDLE;
wb_req_count <= 0;
end else begin
wb_req_state <= nxt_wb_req_state;
wb_req_count <= nxt_wb_req_count;
end
end
endmodule // lisnoc_dma_initiator_wbreq
`include "lisnoc_dma_undef.vh"
// Local Variables:
// verilog-library-directories:("../" "../infrastructure")
// verilog-auto-inst-param-value: t
// End:
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* The wishbone slave interface to configure the DMA module.
*
* (c) 2011-2013 by the author(s)
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*
*/
`include "lisnoc_dma_def.vh"
module lisnoc_dma_wbinterface(/*AUTOARG*/
// Outputs
wb_if_dat_o, wb_if_ack_o, if_write_req, if_write_pos,
if_write_select, if_write_en, if_valid_pos, if_valid_set,
if_valid_en, if_validrd_en,
// Inputs
clk, rst, wb_if_adr_i, wb_if_dat_i, wb_if_cyc_i, wb_if_stb_i,
wb_if_we_i, done
);
parameter table_entries = 4;
// localparam table_entries_ptrwidth = $clog2(table_entries);
localparam table_entries_ptrwidth = 2;
parameter tileid = 0; // TODO: remove
input clk,rst;
input [31:0] wb_if_adr_i;
input [31:0] wb_if_dat_i;
input wb_if_cyc_i;
input wb_if_stb_i;
input wb_if_we_i;
output reg [31:0] wb_if_dat_o;
output wb_if_ack_o;
output [`DMA_REQUEST_WIDTH-1:0] if_write_req;
output [table_entries_ptrwidth-1:0] if_write_pos;
output [`DMA_REQMASK_WIDTH-1:0] if_write_select;
output if_write_en;
// Interface read (status) interface
output [table_entries_ptrwidth-1:0] if_valid_pos;
output if_valid_set;
output if_valid_en;
output if_validrd_en;
input [table_entries-1:0] done;
assign if_write_req = { wb_if_dat_i[`DMA_REQFIELD_LADDR_WIDTH-1:0],
wb_if_dat_i[`DMA_REQFIELD_SIZE_WIDTH-1:0],
wb_if_dat_i[`DMA_REQFIELD_RTILE_WIDTH-1:0],
wb_if_dat_i[`DMA_REQFIELD_RADDR_WIDTH-1:0],
wb_if_dat_i[0] };
assign if_write_pos = wb_if_adr_i[table_entries_ptrwidth+4:5]; // ptrwidth MUST be <= 7 (=128 entries)
assign if_write_en = wb_if_cyc_i & wb_if_stb_i & wb_if_we_i;
assign if_valid_pos = wb_if_adr_i[table_entries_ptrwidth+4:5]; // ptrwidth MUST be <= 7 (=128 entries)
assign if_valid_en = wb_if_cyc_i & wb_if_stb_i & (wb_if_adr_i[4:0] == 5'h14) & wb_if_we_i;
assign if_validrd_en = wb_if_cyc_i & wb_if_stb_i & (wb_if_adr_i[4:0] == 5'h14) & ~wb_if_we_i;
assign if_valid_set = wb_if_we_i | (~wb_if_we_i & ~done[if_valid_pos]);
assign wb_if_ack_o = wb_if_cyc_i & wb_if_stb_i;
always @(*) begin
if (wb_if_adr_i[4:0] == 5'h14) begin
wb_if_dat_o = {31'h0,done[if_valid_pos]};
end else begin
wb_if_dat_o = 32'h0;
end
end
genvar i;
// This assumes, that mask and address match
generate
for (i=0;i<`DMA_REQMASK_WIDTH;i=i+1) begin
assign if_write_select[i] = (wb_if_adr_i[4:2] == i);
end
endgenerate
endmodule // lisnoc_dma_wbinterface
`include "lisnoc_dma_undef.vh"
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is a deserializer for virtual channels
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
* Alexandra Weber <[email protected]>
*/
// TODO: Make more flexible by lookup vector class->vc
module lisnoc_vc_deserializer(
//output
flit_o, valid_o, ready_for_input,
//input
flit_i, valid_i, ready_for_output,
clk, rst
);
parameter flit_data_width = 32;
parameter flit_type_width = 2;
localparam flit_width = flit_data_width + flit_type_width;
parameter FLIT_TYPE_HEADER = 2'b01;
parameter FLIT_TYPE_PAYLOAD = 2'b00;
parameter FLIT_TYPE_LAST = 2'b10;
parameter FLIT_TYPE_SINGLE = 2'b11;
// every vchannel gets the packets of one class
parameter class_msb = 21;
parameter class_lsb = 20;
parameter class_width = 2;
// number of output vchannels
parameter vchannels = 2;
input clk;
input rst;
// array of readys from the vchannels
input [vchannels-1:0] ready_for_output;
// not-full signal from the fifo
output reg ready_for_input;
// one vchannel in (serialized)
input [flit_width-1:0] flit_i;
input valid_i;
// n-vchannel out (multiple vchannels)
output reg [flit_width-1:0] flit_o;
output reg [vchannels-1:0] valid_o;
reg [flit_width-1:0] nxt_flit_o;
reg [vchannels-1:0] nxt_valid_o;
reg [class_width-1:0] req_vchannel;
reg [class_width-1:0] nxt_req_vchannel;
reg state;
reg nxt_state;
always @ (*) begin: fsm
localparam WAITING = 1'b0;
localparam SENDING = 1'b1;
case (state)
WAITING: begin
nxt_flit_o = 'hx;
nxt_valid_o = {vchannels{1'b0}};
ready_for_input = 1'b0;
if(flit_i[flit_width-1:flit_width-2] == FLIT_TYPE_HEADER ||
flit_i[flit_width-1:flit_width-2] == FLIT_TYPE_SINGLE) begin
nxt_req_vchannel = flit_i[class_msb:class_lsb];
nxt_state = SENDING;
nxt_flit_o = flit_i;
ready_for_input = 1'b1;
nxt_valid_o[nxt_req_vchannel] = 1'b1;
end else begin
nxt_req_vchannel = req_vchannel;
nxt_state = WAITING;
ready_for_input = 1'b0;
end
end
SENDING: begin : sending
nxt_flit_o = flit_o;
nxt_valid_o[req_vchannel] = 1'b1;
if(ready_for_output[req_vchannel] == 1'b1) begin
ready_for_input = 1'b1;
nxt_flit_o = flit_i;
if(flit_o[flit_width-1:flit_width-2] == FLIT_TYPE_SINGLE ||
flit_o[flit_width-1:flit_width-2] == FLIT_TYPE_LAST) begin
nxt_state = WAITING;
nxt_valid_o[nxt_req_vchannel] = 1'b0;
end else begin
nxt_state = SENDING;
end
end else begin
ready_for_input = 1'b0;
nxt_state = state;
nxt_flit_o = flit_o;
end
end
endcase
end
always @ (posedge clk) begin
if(rst == 1'b1) begin
flit_o = 'hx;
valid_o = {vchannels{1'b0}};
state = 1'b0;
end else begin
flit_o = nxt_flit_o;
valid_o = nxt_valid_o;
req_vchannel = nxt_req_vchannel;
state = nxt_state;
end
end
endmodule
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is a multiplexer that muxes several incoming vchannels to a
* single one. It ensures wormhole forwarding in a first-come,
* first-served way. There must not be two valid vchannels at the
* same time, so it cannot be used as an arbiter!
*
* Author(s):
* Michael Tempelmeier <[email protected]>
*/
`include "lisnoc_def.vh"
module lisnoc_vc_multiplexer(/*AUTOARG*/
// Outputs
ready_o, valid_o, data_o,
// Inputs
clk, rst, valid_i, data_i, ready_i
);
parameter vchannels = 3;
parameter flit_width = 32;
input clk;
input rst;
//n-vchannel in
input [vchannels-1:0] valid_i;
output [vchannels-1:0] ready_o;
input [flit_width-1:0] data_i;
//one vchannel out
input ready_i;
output valid_o;
output [flit_width-1:0] data_o;
reg state;
reg nxt_state;
`define STATE_READY 1'b0
`define STATE_VALID 1'b1
reg [vchannels-1 :0] channel_mask;
reg [vchannels-1 :0] nxt_channel_mask;
assign data_o = data_i;
assign valid_o = |(valid_i & channel_mask);
assign ready_o = channel_mask & {vchannels{ready_i}};
always @ (*) begin : fsm_logic
//default:
nxt_state = state;
nxt_channel_mask = channel_mask;
case (state)
`STATE_READY: begin
if (ready_i) begin
if((data_i[flit_width-1:flit_width-2] == `FLIT_TYPE_HEADER) && (|valid_i)) begin
//save the current vchannel if a new packet arrives
//if the packet is a single-flit we don't need this information since there are no
//following flits that have to be served on the same vchannel
nxt_state = `STATE_VALID;
nxt_channel_mask = valid_i; //save the current channel;
end
end
end // case: `STATE_READY
`STATE_VALID: begin
if (ready_i) begin
if((data_i[flit_width-1:flit_width-2] == `FLIT_TYPE_LAST) && (valid_i & channel_mask)) begin
//end of packet - we are ready for a new one
nxt_state = `STATE_READY;
nxt_channel_mask = {vchannels{1'b1}};
end
end
end
default: begin
//nothing
end
endcase // case (state)
end // block: fsm_logic
always @ (posedge clk) begin : fsm_reg
if (rst) begin
state = `STATE_READY;
channel_mask = {vchannels{1'b1}};
end else begin
state = nxt_state;
channel_mask = nxt_channel_mask;
end
end
endmodule // lisnoc_vc_multiplexer
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is a serializer that serializes several incoming vchannels to a
* single one. It ensures wormhole forwarding in a first-come,
* first-served way. There must not be two valid vchannels at the
* same time, so it cannot be used as an arbiter!
*
* Author(s):
* Michael Tempelmeier <[email protected]>
*/
`include "lisnoc_def.vh"
module lisnoc_vc_serializer(/*AUTOARG*/
// Outputs
ready_mvc, valid_ser, data_ser,
// Inputs
clk, rst, valid_mvc, data_mvc, ready_ser
);
parameter vchannels = 3;
parameter flit_width = 32;
input clk;
input rst;
//n-vchannel in (multiple vchannels)
input [vchannels-1:0] valid_mvc;
output [vchannels-1:0] ready_mvc;
input [flit_width-1:0] data_mvc;
//one vchannel out (serialized)
input ready_ser;
output valid_ser;
output [flit_width-1:0] data_ser;
reg state;
reg nxt_state;
localparam STATE_READY = 1'b0;
localparam STATE_VALID = 1'b1;
reg [vchannels-1 :0] channel_mask;
reg [vchannels-1 :0] nxt_channel_mask;
assign data_ser = data_mvc;
assign valid_ser = |(valid_mvc & channel_mask);
assign ready_mvc = channel_mask & {vchannels{ready_ser}};
always @ (*) begin : fsm_logic
//default:
nxt_state = state;
nxt_channel_mask = channel_mask;
case (state)
STATE_READY: begin
if (ready_ser) begin
if((data_mvc[flit_width-1:flit_width-2] == `FLIT_TYPE_HEADER) && (|valid_mvc)) begin
//save the current vchannel if a new packet arrives
//if the packet is a single-flit we don't need this information since there are no
//following flits that have to be served on the same vchannel
nxt_state = STATE_VALID;
nxt_channel_mask = valid_mvc; //save the current channel;
end
end
end // case: STATE_READY
STATE_VALID: begin
if (ready_ser) begin
if((data_mvc[flit_width-1:flit_width-2] == `FLIT_TYPE_LAST) && (valid_mvc & channel_mask)) begin
//end of packet - we are ready for a new one
nxt_state = STATE_READY;
nxt_channel_mask = {vchannels{1'b1}};
end
end
end
default: begin
//nothing
end
endcase // case (state)
end // block: fsm_logic
always @ (posedge clk) begin : fsm_reg
if (rst) begin
state = STATE_READY;
channel_mask = {vchannels{1'b1}};
end else begin
state = nxt_state;
channel_mask = nxt_channel_mask;
end
end
endmodule // lisnoc_vc_multiplexer
|
/* Copyright (c) 2013-2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This modules provides the configuration information of the network
* adapter to the software via memory mapped registers.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
/*
* BASE+
* +----------------------------+
* | 0x0 R: tile id |
* +----------------------------+
* | 0x4 R: number of tiles |
* +----------------------------+
* | 0x8 R: |
* +----------------------------+
* | 0xc R: configuration |
* | bit 0: mp_simple |
* | bit 1: dma |
* +----------------------------+
* | 0x10 R: core base id |
* +----------------------------+
* | 0x14 R: |
* +----------------------------+
* | 0x18 R: domain core number |
* +----------------------------+
* | 0x1c R: global memory size |
* +----------------------------+
* | 0x20 R: global memory tile |
* +----------------------------+
* | 0x24 R: local memory size |
* +----------------------------+
* | 0x28 R: number of compute |
* | tiles |
* +----------------------------+
* | 0x2c R: read a random seed |
* +----------------------------+
* .
* .
* +----------------------------+
* | 0x200 R: list of compute |
* | tiles |
* +----------------------------+
*/
module networkadapter_conf
import optimsoc_config::*;
#(parameter config_t CONFIG = 'x,
parameter TILEID = 'x,
parameter COREBASE = 'x
)
(
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
cdc_conf, cdc_enable,
`endif
`endif
/*AUTOARG*/
// Outputs
data, ack, rty, err,
// Inputs
clk, rst, adr, we, data_i
);
reg [31:0] seed = 0;
`ifdef verilator
initial begin
seed = $random();
end
`endif
localparam REG_TILEID = 0;
localparam REG_NUMTILES = 1;
localparam REG_CONF = 3;
localparam REG_COREBASE = 4;
localparam REG_DOMAIN_NUMCORES = 6;
localparam REG_GMEM_SIZE = 7;
localparam REG_GMEM_TILE = 8;
localparam REG_LMEM_SIZE = 9;
localparam REG_NUMCTS = 10;
localparam REG_SEED = 11;
localparam REG_CDC = 10'h40;
localparam REG_CDC_DYN = 10'h41;
localparam REG_CDC_CONF = 10'h42;
localparam REG_CTLIST = 10'h80;
localparam REGBIT_CONF_MPSIMPLE = 0;
localparam REGBIT_CONF_DMA = 1;
input clk;
input rst;
input [15:0] adr;
input we;
input [31:0] data_i;
output reg [31:0] data;
output ack;
output rty;
output err;
assign ack = ~|adr[15:12];
assign err = ~ack;
assign rty = 1'b0;
// CDC configuration register
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
output reg [2:0] cdc_conf;
output reg cdc_enable;
`endif
`endif
wire [15:0] ctlist_vector[0:63];
genvar i;
generate
for (i=0; i<CONFIG.NUMCTS; i=i+1) begin : gen_ctlist_vector // array is indexed by the desired destination
// The entries of this array are subranges from the parameter, where
// the indexing is reversed (num_dests-i-1)!
assign ctlist_vector[CONFIG.NUMCTS - i - 1] = CONFIG.CTLIST[i];
end
endgenerate
always @(*) begin
if (adr[11:9] == REG_CTLIST[9:7]) begin
if (adr[1]) begin
data = {16'h0,ctlist_vector[adr[6:1]]};
end else begin
data = {ctlist_vector[adr[6:1]],16'h0};
end
end else begin
case (adr[11:2])
REG_TILEID: begin
data = TILEID;
end
REG_NUMTILES: begin
data = CONFIG.NUMTILES;
end
REG_CONF: begin
data = 32'h0000_0000;
data[REGBIT_CONF_MPSIMPLE] = CONFIG.NA_ENABLE_MPSIMPLE;
data[REGBIT_CONF_DMA] = CONFIG.NA_ENABLE_DMA;
end
REG_COREBASE: begin
data = 32'(COREBASE);
end
REG_DOMAIN_NUMCORES: begin
data = CONFIG.CORES_PER_TILE;
end
REG_GMEM_SIZE: begin
data = CONFIG.GMEM_SIZE;
end
REG_GMEM_TILE: begin
data = CONFIG.GMEM_TILE;
end
REG_LMEM_SIZE: begin
data = CONFIG.LMEM_SIZE;
end
REG_NUMCTS: begin
data = CONFIG.NUMCTS;
end
REG_SEED: begin
data = seed;
end
REG_CDC: begin
`ifdef OPTIMSOC_CLOCKDOMAINS
data = 32'b1;
`else
data = 32'b0;
`endif
end
REG_CDC_DYN: begin
`ifdef OPTIMSOC_CDC_DYNAMIC
data = 32'b1;
`else
data = 32'b0;
`endif
end
REG_CDC_CONF: begin
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
data = cdc_conf;
`else
data = 32'hx;
`endif
`else
data = 32'hx;
`endif
end
default: begin
data = 32'hx;
end
endcase // case (adr[11:2])
end
end
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
always @(posedge clk) begin
if (rst) begin
cdc_conf <= `OPTIMSOC_CDC_DYN_DEFAULT;
cdc_enable <= 0;
end else begin
if ((adr[11:2]==REG_CDC_CONF) && we) begin
cdc_conf <= data_i[2:0];
cdc_enable <= 1;
end else begin
cdc_conf <= cdc_conf;
cdc_enable <= 0;
end
end
end // always @ (posedge clk)
`endif // `ifdef OPTIMSOC_CDC_DYNAMIC
`endif // `ifdef OPTIMSOC_CLOCKDOMAINS
endmodule // networkadapter_conf
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the network adapter for compute tiles. It is configurable to
* contain different elements, e.g. message passing or DMA.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
`include "lisnoc_def.vh"
module networkadapter_ct
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
parameter TILEID = 'x,
parameter COREBASE = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH
)
(
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
output [2:0] cdc_conf,
output cdc_enable,
`endif
`endif
input clk, rst,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready,
output [31:0] wbm_adr_o,
output wbm_cyc_o,
output [31:0] wbm_dat_o,
output [3:0] wbm_sel_o,
output wbm_stb_o,
output wbm_we_o,
output wbm_cab_o,
output [2:0] wbm_cti_o,
output [1:0] wbm_bte_o,
input wbm_ack_i,
input wbm_rty_i,
input wbm_err_i,
input [31:0] wbm_dat_i,
input [31:0] wbs_adr_i,
input wbs_cyc_i,
input [31:0] wbs_dat_i,
input [3:0] wbs_sel_i,
input wbs_stb_i,
input wbs_we_i,
input wbs_cab_i,
input [2:0] wbs_cti_i,
input [1:0] wbs_bte_i,
output wbs_ack_o,
output wbs_rty_o,
output wbs_err_o,
output [31:0] wbs_dat_o,
output [1:0] irq
);
// Those are the actual channels from the modules
localparam MODCHANNELS = 4;
localparam C_MPSIMPLE_REQ = 0;
localparam C_MPSIMPLE_RESP = 1;
localparam C_DMA_REQ = 2;
localparam C_DMA_RESP = 3;
wire [MODCHANNELS-1:0] mod_out_ready;
wire [MODCHANNELS-1:0] mod_out_valid;
wire [MODCHANNELS-1:0] mod_out_last;
wire [MODCHANNELS-1:0][FLIT_WIDTH-1:0] mod_out_flit;
wire [MODCHANNELS-1:0] mod_in_ready;
wire [MODCHANNELS-1:0] mod_in_valid;
wire [MODCHANNELS-1:0] mod_in_last;
wire [MODCHANNELS-1:0][FLIT_WIDTH-1:0] mod_in_flit;
// The different interfaces at the bus slave
// slave 0: configuration
// NABASE + 0x000000
// slave 1: mp_simple
// NABASE + 0x100000
// slave 2: dma
// NABASE + 0x200000
// If a slave is not present there is a gap
localparam SLAVES = 3; // This is the number of maximum slaves
localparam ID_CONF = 0;
localparam ID_MPSIMPLE = 1;
localparam ID_DMA = 2;
wire [24*SLAVES-1:0] wbif_adr_i;
wire [32*SLAVES-1:0] wbif_dat_i;
wire [SLAVES-1:0] wbif_cyc_i;
wire [SLAVES-1:0] wbif_stb_i;
wire [4*SLAVES-1:0] wbif_sel_i;
wire [SLAVES-1:0] wbif_we_i;
wire [SLAVES*3-1:0] wbif_cti_i;
wire [SLAVES*2-1:0] wbif_bte_i;
wire [32*SLAVES-1:0] wbif_dat_o;
wire [SLAVES-1:0] wbif_ack_o;
wire [SLAVES-1:0] wbif_err_o;
wire [SLAVES-1:0] wbif_rty_o;
wb_decode
#(.SLAVES(3), .DATA_WIDTH(32), .ADDR_WIDTH(24),
.S0_RANGE_WIDTH(4), .S0_RANGE_MATCH(4'h0),
.S1_RANGE_WIDTH(4), .S1_RANGE_MATCH(4'h1),
.S2_RANGE_WIDTH(4), .S2_RANGE_MATCH(4'h2)
)
u_slavedecode
(.clk_i (clk),
.rst_i (rst),
.m_adr_i (wbs_adr_i[23:0]),
.m_dat_i (wbs_dat_i),
.m_cyc_i (wbs_cyc_i),
.m_stb_i (wbs_stb_i),
.m_sel_i (wbs_sel_i),
.m_we_i (wbs_we_i),
.m_cti_i (wbs_cti_i),
.m_bte_i (wbs_bte_i),
.m_dat_o (wbs_dat_o),
.m_ack_o (wbs_ack_o),
.m_err_o (wbs_err_o),
.m_rty_o (wbs_rty_o),
.s_adr_o (wbif_adr_i),
.s_dat_o (wbif_dat_i),
.s_cyc_o (wbif_cyc_i),
.s_stb_o (wbif_stb_i),
.s_sel_o (wbif_sel_i),
.s_we_o (wbif_we_i),
.s_cti_o (wbif_cti_i),
.s_bte_o (wbif_bte_i),
.s_dat_i (wbif_dat_o),
.s_ack_i (wbif_ack_o),
.s_err_i (wbif_err_o),
.s_rty_i (wbif_rty_o));
networkadapter_conf
#(.CONFIG (CONFIG),
.TILEID (TILEID),
.COREBASE (COREBASE))
u_conf(
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
.cdc_conf (cdc_conf[2:0]),
.cdc_enable (cdc_enable),
`endif
`endif
// Outputs
.data (wbif_dat_o[ID_CONF*32 +: 32]),
.ack (wbif_ack_o[ID_CONF]),
.rty (wbif_rty_o[ID_CONF]),
.err (wbif_err_o[ID_CONF]),
// Inputs
.clk (clk),
.rst (rst),
.adr (wbs_adr_i[15:0]),
.we (wbs_cyc_i & wbs_stb_i & wbs_we_i),
.data_i (wbif_dat_i[ID_CONF*32 +: 32]));
// just wire them statically for the moment
assign wbif_rty_o[ID_MPSIMPLE] = 1'b0;
mpbuffer_wb
#(.CONFIG(CONFIG),.N(2),.SIZE(16))
u_mpbuffer
(.*,
.noc_out_flit ({mod_out_flit[C_MPSIMPLE_RESP], mod_out_flit[C_MPSIMPLE_REQ]}),
.noc_out_last ({mod_out_last[C_MPSIMPLE_RESP], mod_out_last[C_MPSIMPLE_REQ]}),
.noc_out_valid ({mod_out_valid[C_MPSIMPLE_RESP], mod_out_valid[C_MPSIMPLE_REQ]}),
.noc_out_ready ({mod_out_ready[C_MPSIMPLE_RESP], mod_out_ready[C_MPSIMPLE_REQ]}),
.noc_in_flit ({mod_in_flit[C_MPSIMPLE_RESP], mod_in_flit[C_MPSIMPLE_REQ]}),
.noc_in_last ({mod_in_last[C_MPSIMPLE_RESP], mod_in_last[C_MPSIMPLE_REQ]}),
.noc_in_valid ({mod_in_valid[C_MPSIMPLE_RESP], mod_in_valid[C_MPSIMPLE_REQ]}),
.noc_in_ready ({mod_in_ready[C_MPSIMPLE_RESP], mod_in_ready[C_MPSIMPLE_REQ]}),
.wb_dat_o (wbif_dat_o[ID_MPSIMPLE*32 +: 32]),
.wb_ack_o (wbif_ack_o[ID_MPSIMPLE]),
.wb_err_o (wbif_err_o[ID_MPSIMPLE]),
.wb_adr_i ({8'h0, wbif_adr_i[ID_MPSIMPLE*24 +: 24]}),
.wb_we_i (wbif_we_i[ID_MPSIMPLE]),
.wb_cyc_i (wbif_cyc_i[ID_MPSIMPLE]),
.wb_stb_i (wbif_stb_i[ID_MPSIMPLE]),
.wb_dat_i (wbif_dat_i[ID_MPSIMPLE*32 +: 32]),
.irq (irq[1])
);
generate
if (CONFIG.NA_ENABLE_DMA) begin
wire [3:0] irq_dma;
assign irq[0] = |irq_dma;
wire [1:0][CONFIG.NOC_FLIT_WIDTH+1:0] dma_in_flit, dma_out_flit;
assign dma_in_flit[0] = {mod_in_last[C_DMA_REQ], 1'b0, mod_in_flit[C_DMA_REQ]};
assign mod_out_last[C_DMA_REQ] = dma_out_flit[0][CONFIG.NOC_FLIT_WIDTH+1];
assign mod_out_flit[C_DMA_REQ] = dma_out_flit[0][CONFIG.NOC_FLIT_WIDTH-1:0];
assign dma_in_flit[1] = {mod_in_last[C_DMA_RESP], 1'b0, mod_in_flit[C_DMA_RESP]};
assign mod_out_last[C_DMA_RESP] = dma_out_flit[1][CONFIG.NOC_FLIT_WIDTH+1];
assign mod_out_flit[C_DMA_RESP] = dma_out_flit[1][CONFIG.NOC_FLIT_WIDTH-1:0];
/* lisnoc_dma AUTO_TEMPLATE(
.noc_in_req_ready (mod_in_ready[C_DMA_REQ]),
.noc_in_req_valid (mod_in_valid[C_DMA_REQ]),
.noc_in_req_flit (dma_in_flit[0]),
.noc_in_resp_ready (mod_in_ready[C_DMA_RESP]),
.noc_in_resp_valid (mod_in_valid[C_DMA_RESP]),
.noc_in_resp_flit (dma_in_flit[1]),
.noc_out_req_ready (mod_out_ready[C_DMA_REQ]),
.noc_out_req_valid (mod_out_valid[C_DMA_REQ]),
.noc_out_req_flit (dma_out_flit[0]),
.noc_out_resp_ready (mod_out_ready[C_DMA_RESP]),
.noc_out_resp_valid (mod_out_valid[C_DMA_RESP]),
.noc_out_resp_flit (dma_out_flit[1]),
.wb_if_dat_\(.*\) (wbif_dat_\1[ID_DMA*32 +: 32]),
.wb_if_adr_i ({8'h0, wbif_adr_i[ID_DMA*24 +: 24]}),
.wb_if_\(.*\) (wbif_\1[ID_DMA]),
.wb_\(.*\) (wbm_\1),
.irq (irq_dma),
); */
lisnoc_dma
#(.tileid(TILEID),.table_entries(CONFIG.NA_DMA_ENTRIES))
u_dma(/*AUTOINST*/
// Outputs
.noc_in_req_ready (mod_in_ready[C_DMA_REQ]), // Templated
.noc_in_resp_ready (mod_in_ready[C_DMA_RESP]), // Templated
.noc_out_req_flit (dma_out_flit[0]), // Templated
.noc_out_req_valid (mod_out_valid[C_DMA_REQ]), // Templated
.noc_out_resp_flit (dma_out_flit[1]), // Templated
.noc_out_resp_valid (mod_out_valid[C_DMA_RESP]), // Templated
.wb_if_dat_o (wbif_dat_o[ID_DMA*32 +: 32]), // Templated
.wb_if_ack_o (wbif_ack_o[ID_DMA]), // Templated
.wb_if_err_o (wbif_err_o[ID_DMA]), // Templated
.wb_if_rty_o (wbif_rty_o[ID_DMA]), // Templated
.wb_adr_o (wbm_adr_o), // Templated
.wb_dat_o (wbm_dat_o), // Templated
.wb_cyc_o (wbm_cyc_o), // Templated
.wb_stb_o (wbm_stb_o), // Templated
.wb_sel_o (wbm_sel_o), // Templated
.wb_we_o (wbm_we_o), // Templated
.wb_cab_o (wbm_cab_o), // Templated
.wb_cti_o (wbm_cti_o), // Templated
.wb_bte_o (wbm_bte_o), // Templated
.irq (irq_dma), // Templated
// Inputs
.clk (clk),
.rst (rst),
.noc_in_req_flit (dma_in_flit[0]), // Templated
.noc_in_req_valid (mod_in_valid[C_DMA_REQ]), // Templated
.noc_in_resp_flit (dma_in_flit[1]), // Templated
.noc_in_resp_valid (mod_in_valid[C_DMA_RESP]), // Templated
.noc_out_req_ready (mod_out_ready[C_DMA_REQ]), // Templated
.noc_out_resp_ready (mod_out_ready[C_DMA_RESP]), // Templated
.wb_if_adr_i ({8'h0, wbif_adr_i[ID_DMA*24 +: 24]}), // Templated
.wb_if_dat_i (wbif_dat_i[ID_DMA*32 +: 32]), // Templated
.wb_if_cyc_i (wbif_cyc_i[ID_DMA]), // Templated
.wb_if_stb_i (wbif_stb_i[ID_DMA]), // Templated
.wb_if_we_i (wbif_we_i[ID_DMA]), // Templated
.wb_dat_i (wbm_dat_i), // Templated
.wb_ack_i (wbm_ack_i)); // Templated
end else begin // if (CONFIG.NA_ENABLE_DMA)
assign irq[0] = 1'b0;
end
endgenerate
wire [1:0][FLIT_WIDTH-1:0] muxed_flit;
wire [1:0] muxed_last, muxed_valid, muxed_ready;
noc_mux
#(.FLIT_WIDTH(FLIT_WIDTH), .CHANNELS(2))
u_mux0
(.*,
.in_flit ({mod_out_flit[C_MPSIMPLE_REQ], mod_out_flit[C_DMA_REQ]}),
.in_last ({mod_out_last[C_MPSIMPLE_REQ], mod_out_last[C_DMA_REQ]}),
.in_valid ({mod_out_valid[C_MPSIMPLE_REQ], mod_out_valid[C_DMA_REQ]}),
.in_ready ({mod_out_ready[C_MPSIMPLE_REQ], mod_out_ready[C_DMA_REQ]}),
.out_flit (muxed_flit[0]),
.out_last (muxed_last[0]),
.out_valid (muxed_valid[0]),
.out_ready (muxed_ready[0]));
noc_mux
#(.FLIT_WIDTH(FLIT_WIDTH), .CHANNELS(2))
u_mux1
(.*,
.in_flit ({mod_out_flit[C_MPSIMPLE_RESP], mod_out_flit[C_DMA_RESP]}),
.in_last ({mod_out_last[C_MPSIMPLE_RESP], mod_out_last[C_DMA_RESP]}),
.in_valid ({mod_out_valid[C_MPSIMPLE_RESP], mod_out_valid[C_DMA_RESP]}),
.in_ready ({mod_out_ready[C_MPSIMPLE_RESP], mod_out_ready[C_DMA_RESP]}),
.out_flit (muxed_flit[1]),
.out_last (muxed_last[1]),
.out_valid (muxed_valid[1]),
.out_ready (muxed_ready[1]));
noc_buffer
#(.FLIT_WIDTH(FLIT_WIDTH), .DEPTH(4))
u_outbuffer0
(.*,
.in_flit (muxed_flit[0]),
.in_last (muxed_last[0]),
.in_valid (muxed_valid[0]),
.in_ready (muxed_ready[0]),
.out_flit (noc_out_flit[0]),
.out_last (noc_out_last[0]),
.out_valid (noc_out_valid[0]),
.out_ready (noc_out_ready[0]),
.packet_size ()
);
noc_buffer
#(.FLIT_WIDTH(FLIT_WIDTH), .DEPTH(4))
u_outbuffer1
(.*,
.in_flit (muxed_flit[1]),
.in_last (muxed_last[1]),
.in_valid (muxed_valid[1]),
.in_ready (muxed_ready[1]),
.out_flit (noc_out_flit[1]),
.out_last (noc_out_last[1]),
.out_valid (noc_out_valid[1]),
.out_ready (noc_out_ready[1]),
.packet_size ()
);
wire [1:0][FLIT_WIDTH-1:0] inbuffer_flit;
wire [1:0] inbuffer_last, inbuffer_valid, inbuffer_ready;
noc_buffer
#(.FLIT_WIDTH(FLIT_WIDTH), .DEPTH(4))
u_inbuffer0
(.*,
.in_flit (noc_in_flit[0]),
.in_last (noc_in_last[0]),
.in_valid (noc_in_valid[0]),
.in_ready (noc_in_ready[0]),
.out_flit (inbuffer_flit[0]),
.out_last (inbuffer_last[0]),
.out_valid (inbuffer_valid[0]),
.out_ready (inbuffer_ready[0]),
.packet_size ()
);
noc_demux
#(.FLIT_WIDTH (FLIT_WIDTH), .CHANNELS (2),
.MAPPING ({ 48'h0, 8'h2, 8'h1 }))
u_demux0
(.*,
.in_flit (inbuffer_flit[0]),
.in_last (inbuffer_last[0]),
.in_valid (inbuffer_valid[0]),
.in_ready (inbuffer_ready[0]),
.out_flit ({mod_in_flit[C_DMA_REQ], mod_in_flit[C_MPSIMPLE_REQ]}),
.out_last ({mod_in_last[C_DMA_REQ], mod_in_last[C_MPSIMPLE_REQ]}),
.out_valid ({mod_in_valid[C_DMA_REQ], mod_in_valid[C_MPSIMPLE_REQ]}),
.out_ready ({mod_in_ready[C_DMA_REQ], mod_in_ready[C_MPSIMPLE_REQ]}));
noc_buffer
#(.FLIT_WIDTH(FLIT_WIDTH), .DEPTH(4))
u_inbuffer1
(.*,
.in_flit (noc_in_flit[1]),
.in_last (noc_in_last[1]),
.in_valid (noc_in_valid[1]),
.in_ready (noc_in_ready[1]),
.out_flit (inbuffer_flit[1]),
.out_last (inbuffer_last[1]),
.out_valid (inbuffer_valid[1]),
.out_ready (inbuffer_ready[1]),
.packet_size ()
);
noc_demux
#(.FLIT_WIDTH (FLIT_WIDTH), .CHANNELS (2),
.MAPPING ({ 48'h0, 8'h2, 8'h1 }))
u_demux1
(.*,
.in_flit (inbuffer_flit[1]),
.in_last (inbuffer_last[1]),
.in_valid (inbuffer_valid[1]),
.in_ready (inbuffer_ready[1]),
.out_flit ({mod_in_flit[C_DMA_RESP], mod_in_flit[C_MPSIMPLE_RESP]}),
.out_last ({mod_in_last[C_DMA_RESP], mod_in_last[C_MPSIMPLE_RESP]}),
.out_valid ({mod_in_valid[C_DMA_RESP], mod_in_valid[C_MPSIMPLE_RESP]}),
.out_ready ({mod_in_ready[C_DMA_RESP], mod_in_ready[C_MPSIMPLE_RESP]}));
endmodule // networkadapter_ct
// Local Variables:
// verilog-library-directories:("../../../../../external/lisnoc/rtl/dma/" "../../../../../external/lisnoc/rtl/mp_simple/" "../../../../../external/lisnoc/rtl/router/" ".")
// verilog-auto-inst-param-value: t
// End:
|
/*
* PicoRV32 -- A Small RISC-V (RV32I) Processor Core
*
* Copyright (C) 2015 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
`timescale 1 ns / 1 ps
// `default_nettype none
// `define DEBUGNETS
// `define DEBUGREGS
// `define DEBUGASM
// `define DEBUG
`ifdef DEBUG
`define debug(debug_command) debug_command
`else
`define debug(debug_command)
`endif
`ifdef FORMAL
`define FORMAL_KEEP (* keep *)
`define assert(assert_expr) assert(assert_expr)
`else
`ifdef DEBUGNETS
`define FORMAL_KEEP (* keep *)
`else
`define FORMAL_KEEP
`endif
`define assert(assert_expr) empty_statement
`endif
// uncomment this for register file in extra module
// `define PICORV32_REGS picorv32_regs
// this macro can be used to check if the verilog files in your
// design are read in the correct order.
`define PICORV32_V
/***************************************************************
* picorv32
***************************************************************/
module picorv32 #(
parameter [ 0:0] ENABLE_COUNTERS = 1,
parameter [ 0:0] ENABLE_COUNTERS64 = 1,
parameter [ 0:0] ENABLE_REGS_16_31 = 1,
parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
parameter [ 0:0] LATCHED_MEM_RDATA = 0,
parameter [ 0:0] TWO_STAGE_SHIFT = 1,
parameter [ 0:0] BARREL_SHIFTER = 0,
parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
parameter [ 0:0] TWO_CYCLE_ALU = 0,
parameter [ 0:0] COMPRESSED_ISA = 0,
parameter [ 0:0] CATCH_MISALIGN = 1,
parameter [ 0:0] CATCH_ILLINSN = 1,
parameter [ 0:0] ENABLE_PCPI = 0,
parameter [ 0:0] ENABLE_MUL = 0,
parameter [ 0:0] ENABLE_FAST_MUL = 0,
parameter [ 0:0] ENABLE_DIV = 0,
parameter [ 0:0] ENABLE_IRQ = 0,
parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
parameter [ 0:0] ENABLE_TRACE = 0,
parameter [ 0:0] REGS_INIT_ZERO = 0,
parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
parameter [31:0] STACKADDR = 32'h ffff_ffff
) (
input clk, resetn,
output reg trap,
output reg mem_valid,
output reg mem_instr,
input mem_ready,
output reg [31:0] mem_addr,
output reg [31:0] mem_wdata,
output reg [ 3:0] mem_wstrb,
input [31:0] mem_rdata,
// Look-Ahead Interface
output mem_la_read,
output mem_la_write,
output [31:0] mem_la_addr,
output reg [31:0] mem_la_wdata,
output reg [ 3:0] mem_la_wstrb,
// Pico Co-Processor Interface (PCPI)
output reg pcpi_valid,
output reg [31:0] pcpi_insn,
output [31:0] pcpi_rs1,
output [31:0] pcpi_rs2,
input pcpi_wr,
input [31:0] pcpi_rd,
input pcpi_wait,
input pcpi_ready,
// IRQ Interface
input [31:0] irq,
output reg [31:0] eoi,
`ifdef RISCV_FORMAL
output reg rvfi_valid,
output reg [63:0] rvfi_order,
output reg [31:0] rvfi_insn,
output reg rvfi_trap,
output reg rvfi_halt,
output reg rvfi_intr,
output reg [ 1:0] rvfi_mode,
output reg [ 4:0] rvfi_rs1_addr,
output reg [ 4:0] rvfi_rs2_addr,
output reg [31:0] rvfi_rs1_rdata,
output reg [31:0] rvfi_rs2_rdata,
output reg [ 4:0] rvfi_rd_addr,
output reg [31:0] rvfi_rd_wdata,
output reg [31:0] rvfi_pc_rdata,
output reg [31:0] rvfi_pc_wdata,
output reg [31:0] rvfi_mem_addr,
output reg [ 3:0] rvfi_mem_rmask,
output reg [ 3:0] rvfi_mem_wmask,
output reg [31:0] rvfi_mem_rdata,
output reg [31:0] rvfi_mem_wdata,
`endif
// Trace Interface
output reg trace_valid,
output reg [35:0] trace_data
);
localparam integer irq_timer = 0;
localparam integer irq_ebreak = 1;
localparam integer irq_buserror = 2;
localparam integer irqregs_offset = ENABLE_REGS_16_31 ? 32 : 16;
localparam integer regfile_size = (ENABLE_REGS_16_31 ? 32 : 16) + 4*ENABLE_IRQ*ENABLE_IRQ_QREGS;
localparam integer regindex_bits = (ENABLE_REGS_16_31 ? 5 : 4) + ENABLE_IRQ*ENABLE_IRQ_QREGS;
localparam WITH_PCPI = ENABLE_PCPI || ENABLE_MUL || ENABLE_FAST_MUL || ENABLE_DIV;
localparam [35:0] TRACE_BRANCH = {4'b 0001, 32'b 0};
localparam [35:0] TRACE_ADDR = {4'b 0010, 32'b 0};
localparam [35:0] TRACE_IRQ = {4'b 1000, 32'b 0};
reg [63:0] count_cycle, count_instr;
reg [31:0] reg_pc, reg_next_pc, reg_op1, reg_op2, reg_out;
reg [4:0] reg_sh;
reg [31:0] next_insn_opcode;
reg [31:0] dbg_insn_opcode;
reg [31:0] dbg_insn_addr;
wire dbg_mem_valid = mem_valid;
wire dbg_mem_instr = mem_instr;
wire dbg_mem_ready = mem_ready;
wire [31:0] dbg_mem_addr = mem_addr;
wire [31:0] dbg_mem_wdata = mem_wdata;
wire [ 3:0] dbg_mem_wstrb = mem_wstrb;
wire [31:0] dbg_mem_rdata = mem_rdata;
assign pcpi_rs1 = reg_op1;
assign pcpi_rs2 = reg_op2;
wire [31:0] next_pc;
reg irq_delay;
reg irq_active;
reg [31:0] irq_mask;
reg [31:0] irq_pending;
reg [31:0] timer;
`ifndef PICORV32_REGS
reg [31:0] cpuregs [0:regfile_size-1];
integer i;
initial begin
if (REGS_INIT_ZERO) begin
for (i = 0; i < regfile_size; i = i+1)
cpuregs[i] = 0;
end
end
`endif
task empty_statement;
// This task is used by the `assert directive in non-formal mode to
// avoid empty statement (which are unsupported by plain Verilog syntax).
begin end
endtask
`ifdef DEBUGREGS
wire [31:0] dbg_reg_x0 = 0;
wire [31:0] dbg_reg_x1 = cpuregs[1];
wire [31:0] dbg_reg_x2 = cpuregs[2];
wire [31:0] dbg_reg_x3 = cpuregs[3];
wire [31:0] dbg_reg_x4 = cpuregs[4];
wire [31:0] dbg_reg_x5 = cpuregs[5];
wire [31:0] dbg_reg_x6 = cpuregs[6];
wire [31:0] dbg_reg_x7 = cpuregs[7];
wire [31:0] dbg_reg_x8 = cpuregs[8];
wire [31:0] dbg_reg_x9 = cpuregs[9];
wire [31:0] dbg_reg_x10 = cpuregs[10];
wire [31:0] dbg_reg_x11 = cpuregs[11];
wire [31:0] dbg_reg_x12 = cpuregs[12];
wire [31:0] dbg_reg_x13 = cpuregs[13];
wire [31:0] dbg_reg_x14 = cpuregs[14];
wire [31:0] dbg_reg_x15 = cpuregs[15];
wire [31:0] dbg_reg_x16 = cpuregs[16];
wire [31:0] dbg_reg_x17 = cpuregs[17];
wire [31:0] dbg_reg_x18 = cpuregs[18];
wire [31:0] dbg_reg_x19 = cpuregs[19];
wire [31:0] dbg_reg_x20 = cpuregs[20];
wire [31:0] dbg_reg_x21 = cpuregs[21];
wire [31:0] dbg_reg_x22 = cpuregs[22];
wire [31:0] dbg_reg_x23 = cpuregs[23];
wire [31:0] dbg_reg_x24 = cpuregs[24];
wire [31:0] dbg_reg_x25 = cpuregs[25];
wire [31:0] dbg_reg_x26 = cpuregs[26];
wire [31:0] dbg_reg_x27 = cpuregs[27];
wire [31:0] dbg_reg_x28 = cpuregs[28];
wire [31:0] dbg_reg_x29 = cpuregs[29];
wire [31:0] dbg_reg_x30 = cpuregs[30];
wire [31:0] dbg_reg_x31 = cpuregs[31];
`endif
// Internal PCPI Cores
wire pcpi_mul_wr;
wire [31:0] pcpi_mul_rd;
wire pcpi_mul_wait;
wire pcpi_mul_ready;
wire pcpi_div_wr;
wire [31:0] pcpi_div_rd;
wire pcpi_div_wait;
wire pcpi_div_ready;
reg pcpi_int_wr;
reg [31:0] pcpi_int_rd;
reg pcpi_int_wait;
reg pcpi_int_ready;
/*generate if (ENABLE_FAST_MUL) begin
picorv32_pcpi_fast_mul pcpi_mul (
.clk (clk ),
.resetn (resetn ),
.pcpi_valid(pcpi_valid ),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_mul_wr ),
.pcpi_rd (pcpi_mul_rd ),
.pcpi_wait (pcpi_mul_wait ),
.pcpi_ready(pcpi_mul_ready )
);
end else if (ENABLE_MUL) begin
picorv32_pcpi_mul pcpi_mul (
.clk (clk ),
.resetn (resetn ),
.pcpi_valid(pcpi_valid ),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_mul_wr ),
.pcpi_rd (pcpi_mul_rd ),
.pcpi_wait (pcpi_mul_wait ),
.pcpi_ready(pcpi_mul_ready )
);
end else begin
assign pcpi_mul_wr = 0;
assign pcpi_mul_rd = 32'bx;
assign pcpi_mul_wait = 0;
assign pcpi_mul_ready = 0;
end endgenerate
generate if (ENABLE_DIV) begin
picorv32_pcpi_div pcpi_div (
.clk (clk ),
.resetn (resetn ),
.pcpi_valid(pcpi_valid ),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_div_wr ),
.pcpi_rd (pcpi_div_rd ),
.pcpi_wait (pcpi_div_wait ),
.pcpi_ready(pcpi_div_ready )
);
end else begin
assign pcpi_div_wr = 0;
assign pcpi_div_rd = 32'bx;
assign pcpi_div_wait = 0;
assign pcpi_div_ready = 0;
end endgenerate
*/
always @* begin
pcpi_int_wr = 0;
pcpi_int_rd = 32'bx;
pcpi_int_wait = |{ENABLE_PCPI && pcpi_wait, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_wait, ENABLE_DIV && pcpi_div_wait};
pcpi_int_ready = |{ENABLE_PCPI && pcpi_ready, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready, ENABLE_DIV && pcpi_div_ready};
(* parallel_case *)
case (1'b1)
ENABLE_PCPI && pcpi_ready: begin
pcpi_int_wr = ENABLE_PCPI ? pcpi_wr : 0;
pcpi_int_rd = ENABLE_PCPI ? pcpi_rd : 0;
end
(ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready: begin
pcpi_int_wr = pcpi_mul_wr;
pcpi_int_rd = pcpi_mul_rd;
end
ENABLE_DIV && pcpi_div_ready: begin
pcpi_int_wr = pcpi_div_wr;
pcpi_int_rd = pcpi_div_rd;
end
endcase
end
// Memory Interface
reg [1:0] mem_state;
reg [1:0] mem_wordsize;
reg [31:0] mem_rdata_word;
reg [31:0] mem_rdata_q;
reg mem_do_prefetch;
reg mem_do_rinst;
reg mem_do_rdata;
reg mem_do_wdata;
wire mem_xfer;
reg mem_la_secondword, mem_la_firstword_reg, last_mem_valid;
wire mem_la_firstword = COMPRESSED_ISA && (mem_do_prefetch || mem_do_rinst) && next_pc[1] && !mem_la_secondword;
wire mem_la_firstword_xfer = COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg);
reg prefetched_high_word;
reg clear_prefetched_high_word;
reg [15:0] mem_16bit_buffer;
wire [31:0] mem_rdata_latched_noshuffle;
wire [31:0] mem_rdata_latched;
wire mem_la_use_prefetched_high_word = COMPRESSED_ISA && mem_la_firstword && prefetched_high_word && !clear_prefetched_high_word;
assign mem_xfer = (mem_valid && mem_ready) || (mem_la_use_prefetched_high_word && mem_do_rinst);
wire mem_busy = |{mem_do_prefetch, mem_do_rinst, mem_do_rdata, mem_do_wdata};
wire mem_done = resetn && ((mem_xfer && |mem_state && (mem_do_rinst || mem_do_rdata || mem_do_wdata)) || (&mem_state && mem_do_rinst)) &&
(!mem_la_firstword || (~&mem_rdata_latched[1:0] && mem_xfer));
assign mem_la_write = resetn && !mem_state && mem_do_wdata;
assign mem_la_read = resetn && ((!mem_la_use_prefetched_high_word && !mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata)) ||
(COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg) && !mem_la_secondword && &mem_rdata_latched[1:0]));
assign mem_la_addr = (mem_do_prefetch || mem_do_rinst) ? {next_pc[31:2] + mem_la_firstword_xfer, 2'b00} : {reg_op1[31:2], 2'b00};
assign mem_rdata_latched_noshuffle = (mem_xfer || LATCHED_MEM_RDATA) ? mem_rdata : mem_rdata_q;
assign mem_rdata_latched = COMPRESSED_ISA && mem_la_use_prefetched_high_word ? {16'bx, mem_16bit_buffer} :
COMPRESSED_ISA && mem_la_secondword ? {mem_rdata_latched_noshuffle[15:0], mem_16bit_buffer} :
COMPRESSED_ISA && mem_la_firstword ? {16'bx, mem_rdata_latched_noshuffle[31:16]} : mem_rdata_latched_noshuffle;
always @(posedge clk) begin
if (!resetn) begin
mem_la_firstword_reg <= 0;
last_mem_valid <= 0;
end else begin
if (!last_mem_valid)
mem_la_firstword_reg <= mem_la_firstword;
last_mem_valid <= mem_valid && !mem_ready;
end
end
always @* begin
(* full_case *)
case (mem_wordsize)
0: begin
mem_la_wdata = reg_op2;
mem_la_wstrb = 4'b1111;
mem_rdata_word = mem_rdata;
end
1: begin
mem_la_wdata = {2{reg_op2[15:0]}};
mem_la_wstrb = reg_op1[1] ? 4'b1100 : 4'b0011;
case (reg_op1[1])
1'b0: mem_rdata_word = {16'b0, mem_rdata[15: 0]};
1'b1: mem_rdata_word = {16'b0, mem_rdata[31:16]};
endcase
end
2: begin
mem_la_wdata = {4{reg_op2[7:0]}};
mem_la_wstrb = 4'b0001 << reg_op1[1:0];
case (reg_op1[1:0])
2'b00: mem_rdata_word = {24'b0, mem_rdata[ 7: 0]};
2'b01: mem_rdata_word = {24'b0, mem_rdata[15: 8]};
2'b10: mem_rdata_word = {24'b0, mem_rdata[23:16]};
2'b11: mem_rdata_word = {24'b0, mem_rdata[31:24]};
endcase
end
endcase
end
always @(posedge clk) begin
if (mem_xfer) begin
mem_rdata_q <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
next_insn_opcode <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
end
if (COMPRESSED_ISA && mem_done && (mem_do_prefetch || mem_do_rinst)) begin
case (mem_rdata_latched[1:0])
2'b00: begin // Quadrant 0
case (mem_rdata_latched[15:13])
3'b000: begin // C.ADDI4SPN
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= {2'b0, mem_rdata_latched[10:7], mem_rdata_latched[12:11], mem_rdata_latched[5], mem_rdata_latched[6], 2'b00};
end
3'b010: begin // C.LW
mem_rdata_q[31:20] <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00};
mem_rdata_q[14:12] <= 3'b 010;
end
3'b 110: begin // C.SW
{mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00};
mem_rdata_q[14:12] <= 3'b 010;
end
endcase
end
2'b01: begin // Quadrant 1
case (mem_rdata_latched[15:13])
3'b 000: begin // C.ADDI
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
end
3'b 010: begin // C.LI
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
end
3'b 011: begin
if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[4:3],
mem_rdata_latched[5], mem_rdata_latched[2], mem_rdata_latched[6], 4'b 0000});
end else begin // C.LUI
mem_rdata_q[31:12] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
end
end
3'b100: begin
if (mem_rdata_latched[11:10] == 2'b00) begin // C.SRLI
mem_rdata_q[31:25] <= 7'b0000000;
mem_rdata_q[14:12] <= 3'b 101;
end
if (mem_rdata_latched[11:10] == 2'b01) begin // C.SRAI
mem_rdata_q[31:25] <= 7'b0100000;
mem_rdata_q[14:12] <= 3'b 101;
end
if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI
mem_rdata_q[14:12] <= 3'b111;
mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
end
if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND
if (mem_rdata_latched[6:5] == 2'b00) mem_rdata_q[14:12] <= 3'b000;
if (mem_rdata_latched[6:5] == 2'b01) mem_rdata_q[14:12] <= 3'b100;
if (mem_rdata_latched[6:5] == 2'b10) mem_rdata_q[14:12] <= 3'b110;
if (mem_rdata_latched[6:5] == 2'b11) mem_rdata_q[14:12] <= 3'b111;
mem_rdata_q[31:25] <= mem_rdata_latched[6:5] == 2'b00 ? 7'b0100000 : 7'b0000000;
end
end
3'b 110: begin // C.BEQZ
mem_rdata_q[14:12] <= 3'b000;
{ mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
$signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
mem_rdata_latched[11:10], mem_rdata_latched[4:3]});
end
3'b 111: begin // C.BNEZ
mem_rdata_q[14:12] <= 3'b001;
{ mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
$signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
mem_rdata_latched[11:10], mem_rdata_latched[4:3]});
end
endcase
end
2'b10: begin // Quadrant 2
case (mem_rdata_latched[15:13])
3'b000: begin // C.SLLI
mem_rdata_q[31:25] <= 7'b0000000;
mem_rdata_q[14:12] <= 3'b 001;
end
3'b010: begin // C.LWSP
mem_rdata_q[31:20] <= {4'b0, mem_rdata_latched[3:2], mem_rdata_latched[12], mem_rdata_latched[6:4], 2'b00};
mem_rdata_q[14:12] <= 3'b 010;
end
3'b100: begin
if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] == 0) begin // C.JR
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= 12'b0;
end
if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:25] <= 7'b0000000;
end
if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= 12'b0;
end
if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:25] <= 7'b0000000;
end
end
3'b110: begin // C.SWSP
{mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {4'b0, mem_rdata_latched[8:7], mem_rdata_latched[12:9], 2'b00};
mem_rdata_q[14:12] <= 3'b 010;
end
endcase
end
endcase
end
end
always @(posedge clk) begin
if (resetn && !trap) begin
if (mem_do_prefetch || mem_do_rinst || mem_do_rdata)
`assert(!mem_do_wdata);
if (mem_do_prefetch || mem_do_rinst)
`assert(!mem_do_rdata);
if (mem_do_rdata)
`assert(!mem_do_prefetch && !mem_do_rinst);
if (mem_do_wdata)
`assert(!(mem_do_prefetch || mem_do_rinst || mem_do_rdata));
if (mem_state == 2 || mem_state == 3)
`assert(mem_valid || mem_do_prefetch);
end
end
always @(posedge clk) begin
if (!resetn || trap) begin
if (!resetn)
mem_state <= 0;
if (!resetn || mem_ready)
mem_valid <= 0;
mem_la_secondword <= 0;
prefetched_high_word <= 0;
end else begin
if (mem_la_read || mem_la_write) begin
mem_addr <= mem_la_addr;
mem_wstrb <= mem_la_wstrb & {4{mem_la_write}};
end
if (mem_la_write) begin
mem_wdata <= mem_la_wdata;
end
case (mem_state)
0: begin
if (mem_do_prefetch || mem_do_rinst || mem_do_rdata) begin
mem_valid <= !mem_la_use_prefetched_high_word;
mem_instr <= mem_do_prefetch || mem_do_rinst;
mem_wstrb <= 0;
mem_state <= 1;
end
if (mem_do_wdata) begin
mem_valid <= 1;
mem_instr <= 0;
mem_state <= 2;
end
end
1: begin
`assert(mem_wstrb == 0);
`assert(mem_do_prefetch || mem_do_rinst || mem_do_rdata);
`assert(mem_valid == !mem_la_use_prefetched_high_word);
`assert(mem_instr == (mem_do_prefetch || mem_do_rinst));
if (mem_xfer) begin
if (COMPRESSED_ISA && mem_la_read) begin
mem_valid <= 1;
mem_la_secondword <= 1;
if (!mem_la_use_prefetched_high_word)
mem_16bit_buffer <= mem_rdata[31:16];
end else begin
mem_valid <= 0;
mem_la_secondword <= 0;
if (COMPRESSED_ISA && !mem_do_rdata) begin
if (~&mem_rdata[1:0] || mem_la_secondword) begin
mem_16bit_buffer <= mem_rdata[31:16];
prefetched_high_word <= 1;
end else begin
prefetched_high_word <= 0;
end
end
mem_state <= mem_do_rinst || mem_do_rdata ? 0 : 3;
end
end
end
2: begin
`assert(mem_wstrb != 0);
`assert(mem_do_wdata);
if (mem_xfer) begin
mem_valid <= 0;
mem_state <= 0;
end
end
3: begin
`assert(mem_wstrb == 0);
`assert(mem_do_prefetch);
if (mem_do_rinst) begin
mem_state <= 0;
end
end
endcase
end
if (clear_prefetched_high_word)
prefetched_high_word <= 0;
end
// Instruction Decoder
reg instr_lui, instr_auipc, instr_jal, instr_jalr;
reg instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu;
reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw;
reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai;
reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and;
reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak;
reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer;
wire instr_trap;
reg [regindex_bits-1:0] decoded_rd, decoded_rs1, decoded_rs2;
reg [31:0] decoded_imm, decoded_imm_j;
reg decoder_trigger;
reg decoder_trigger_q;
reg decoder_pseudo_trigger;
reg decoder_pseudo_trigger_q;
reg compressed_instr;
reg is_lui_auipc_jal;
reg is_lb_lh_lw_lbu_lhu;
reg is_slli_srli_srai;
reg is_jalr_addi_slti_sltiu_xori_ori_andi;
reg is_sb_sh_sw;
reg is_sll_srl_sra;
reg is_lui_auipc_jal_jalr_addi_add_sub;
reg is_slti_blt_slt;
reg is_sltiu_bltu_sltu;
reg is_beq_bne_blt_bge_bltu_bgeu;
reg is_lbu_lhu_lw;
reg is_alu_reg_imm;
reg is_alu_reg_reg;
reg is_compare;
assign instr_trap = (CATCH_ILLINSN || WITH_PCPI) && !{instr_lui, instr_auipc, instr_jal, instr_jalr,
instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu,
instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw,
instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai,
instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and,
instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh,
instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer};
wire is_rdcycle_rdcycleh_rdinstr_rdinstrh;
assign is_rdcycle_rdcycleh_rdinstr_rdinstrh = |{instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh};
reg [63:0] new_ascii_instr;
`FORMAL_KEEP reg [63:0] dbg_ascii_instr;
`FORMAL_KEEP reg [31:0] dbg_insn_imm;
`FORMAL_KEEP reg [4:0] dbg_insn_rs1;
`FORMAL_KEEP reg [4:0] dbg_insn_rs2;
`FORMAL_KEEP reg [4:0] dbg_insn_rd;
`FORMAL_KEEP reg [31:0] dbg_rs1val;
`FORMAL_KEEP reg [31:0] dbg_rs2val;
`FORMAL_KEEP reg dbg_rs1val_valid;
`FORMAL_KEEP reg dbg_rs2val_valid;
always @* begin
new_ascii_instr = "";
if (instr_lui) new_ascii_instr = "lui";
if (instr_auipc) new_ascii_instr = "auipc";
if (instr_jal) new_ascii_instr = "jal";
if (instr_jalr) new_ascii_instr = "jalr";
if (instr_beq) new_ascii_instr = "beq";
if (instr_bne) new_ascii_instr = "bne";
if (instr_blt) new_ascii_instr = "blt";
if (instr_bge) new_ascii_instr = "bge";
if (instr_bltu) new_ascii_instr = "bltu";
if (instr_bgeu) new_ascii_instr = "bgeu";
if (instr_lb) new_ascii_instr = "lb";
if (instr_lh) new_ascii_instr = "lh";
if (instr_lw) new_ascii_instr = "lw";
if (instr_lbu) new_ascii_instr = "lbu";
if (instr_lhu) new_ascii_instr = "lhu";
if (instr_sb) new_ascii_instr = "sb";
if (instr_sh) new_ascii_instr = "sh";
if (instr_sw) new_ascii_instr = "sw";
if (instr_addi) new_ascii_instr = "addi";
if (instr_slti) new_ascii_instr = "slti";
if (instr_sltiu) new_ascii_instr = "sltiu";
if (instr_xori) new_ascii_instr = "xori";
if (instr_ori) new_ascii_instr = "ori";
if (instr_andi) new_ascii_instr = "andi";
if (instr_slli) new_ascii_instr = "slli";
if (instr_srli) new_ascii_instr = "srli";
if (instr_srai) new_ascii_instr = "srai";
if (instr_add) new_ascii_instr = "add";
if (instr_sub) new_ascii_instr = "sub";
if (instr_sll) new_ascii_instr = "sll";
if (instr_slt) new_ascii_instr = "slt";
if (instr_sltu) new_ascii_instr = "sltu";
if (instr_xor) new_ascii_instr = "xor";
if (instr_srl) new_ascii_instr = "srl";
if (instr_sra) new_ascii_instr = "sra";
if (instr_or) new_ascii_instr = "or";
if (instr_and) new_ascii_instr = "and";
if (instr_rdcycle) new_ascii_instr = "rdcycle";
if (instr_rdcycleh) new_ascii_instr = "rdcycleh";
if (instr_rdinstr) new_ascii_instr = "rdinstr";
if (instr_rdinstrh) new_ascii_instr = "rdinstrh";
if (instr_getq) new_ascii_instr = "getq";
if (instr_setq) new_ascii_instr = "setq";
if (instr_retirq) new_ascii_instr = "retirq";
if (instr_maskirq) new_ascii_instr = "maskirq";
if (instr_waitirq) new_ascii_instr = "waitirq";
if (instr_timer) new_ascii_instr = "timer";
end
reg [63:0] q_ascii_instr;
reg [31:0] q_insn_imm;
reg [31:0] q_insn_opcode;
reg [4:0] q_insn_rs1;
reg [4:0] q_insn_rs2;
reg [4:0] q_insn_rd;
reg dbg_next;
wire launch_next_insn;
reg dbg_valid_insn;
reg [63:0] cached_ascii_instr;
reg [31:0] cached_insn_imm;
reg [31:0] cached_insn_opcode;
reg [4:0] cached_insn_rs1;
reg [4:0] cached_insn_rs2;
reg [4:0] cached_insn_rd;
always @(posedge clk) begin
q_ascii_instr <= dbg_ascii_instr;
q_insn_imm <= dbg_insn_imm;
q_insn_opcode <= dbg_insn_opcode;
q_insn_rs1 <= dbg_insn_rs1;
q_insn_rs2 <= dbg_insn_rs2;
q_insn_rd <= dbg_insn_rd;
dbg_next <= launch_next_insn;
if (!resetn || trap)
dbg_valid_insn <= 0;
else if (launch_next_insn)
dbg_valid_insn <= 1;
if (decoder_trigger_q) begin
cached_ascii_instr <= new_ascii_instr;
cached_insn_imm <= decoded_imm;
if (&next_insn_opcode[1:0])
cached_insn_opcode <= next_insn_opcode;
else
cached_insn_opcode <= {16'b0, next_insn_opcode[15:0]};
cached_insn_rs1 <= decoded_rs1;
cached_insn_rs2 <= decoded_rs2;
cached_insn_rd <= decoded_rd;
end
if (launch_next_insn) begin
dbg_insn_addr <= next_pc;
end
end
always @* begin
dbg_ascii_instr = q_ascii_instr;
dbg_insn_imm = q_insn_imm;
dbg_insn_opcode = q_insn_opcode;
dbg_insn_rs1 = q_insn_rs1;
dbg_insn_rs2 = q_insn_rs2;
dbg_insn_rd = q_insn_rd;
if (dbg_next) begin
if (decoder_pseudo_trigger_q) begin
dbg_ascii_instr = cached_ascii_instr;
dbg_insn_imm = cached_insn_imm;
dbg_insn_opcode = cached_insn_opcode;
dbg_insn_rs1 = cached_insn_rs1;
dbg_insn_rs2 = cached_insn_rs2;
dbg_insn_rd = cached_insn_rd;
end else begin
dbg_ascii_instr = new_ascii_instr;
if (&next_insn_opcode[1:0])
dbg_insn_opcode = next_insn_opcode;
else
dbg_insn_opcode = {16'b0, next_insn_opcode[15:0]};
dbg_insn_imm = decoded_imm;
dbg_insn_rs1 = decoded_rs1;
dbg_insn_rs2 = decoded_rs2;
dbg_insn_rd = decoded_rd;
end
end
end
`ifdef DEBUGASM
always @(posedge clk) begin
if (dbg_next) begin
$display("debugasm %x %x %s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "*");
end
end
`endif
`ifdef DEBUG
always @(posedge clk) begin
if (dbg_next) begin
if (&dbg_insn_opcode[1:0])
$display("DECODE: 0x%08x 0x%08x %-0s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
else
$display("DECODE: 0x%08x 0x%04x %-0s", dbg_insn_addr, dbg_insn_opcode[15:0], dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
end
end
`endif
always @(posedge clk) begin
is_lui_auipc_jal <= |{instr_lui, instr_auipc, instr_jal};
is_lui_auipc_jal_jalr_addi_add_sub <= |{instr_lui, instr_auipc, instr_jal, instr_jalr, instr_addi, instr_add, instr_sub};
is_slti_blt_slt <= |{instr_slti, instr_blt, instr_slt};
is_sltiu_bltu_sltu <= |{instr_sltiu, instr_bltu, instr_sltu};
is_lbu_lhu_lw <= |{instr_lbu, instr_lhu, instr_lw};
is_compare <= |{is_beq_bne_blt_bge_bltu_bgeu, instr_slti, instr_slt, instr_sltiu, instr_sltu};
if (mem_do_rinst && mem_done) begin
instr_lui <= mem_rdata_latched[6:0] == 7'b0110111;
instr_auipc <= mem_rdata_latched[6:0] == 7'b0010111;
instr_jal <= mem_rdata_latched[6:0] == 7'b1101111;
instr_jalr <= mem_rdata_latched[6:0] == 7'b1100111 && mem_rdata_latched[14:12] == 3'b000;
instr_retirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ;
instr_waitirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000100 && ENABLE_IRQ;
is_beq_bne_blt_bge_bltu_bgeu <= mem_rdata_latched[6:0] == 7'b1100011;
is_lb_lh_lw_lbu_lhu <= mem_rdata_latched[6:0] == 7'b0000011;
is_sb_sh_sw <= mem_rdata_latched[6:0] == 7'b0100011;
is_alu_reg_imm <= mem_rdata_latched[6:0] == 7'b0010011;
is_alu_reg_reg <= mem_rdata_latched[6:0] == 7'b0110011;
{ decoded_imm_j[31:20], decoded_imm_j[10:1], decoded_imm_j[11], decoded_imm_j[19:12], decoded_imm_j[0] } <= $signed({mem_rdata_latched[31:12], 1'b0});
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[19:15];
decoded_rs2 <= mem_rdata_latched[24:20];
if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS)
decoded_rs1[regindex_bits-1] <= 1; // instr_getq
if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ)
decoded_rs1 <= ENABLE_IRQ_QREGS ? irqregs_offset : 3; // instr_retirq
compressed_instr <= 0;
if (COMPRESSED_ISA && mem_rdata_latched[1:0] != 2'b11) begin
compressed_instr <= 1;
decoded_rd <= 0;
decoded_rs1 <= 0;
decoded_rs2 <= 0;
{ decoded_imm_j[31:11], decoded_imm_j[4], decoded_imm_j[9:8], decoded_imm_j[10], decoded_imm_j[6],
decoded_imm_j[7], decoded_imm_j[3:1], decoded_imm_j[5], decoded_imm_j[0] } <= $signed({mem_rdata_latched[12:2], 1'b0});
case (mem_rdata_latched[1:0])
2'b00: begin // Quadrant 0
case (mem_rdata_latched[15:13])
3'b000: begin // C.ADDI4SPN
is_alu_reg_imm <= |mem_rdata_latched[12:5];
decoded_rs1 <= 2;
decoded_rd <= 8 + mem_rdata_latched[4:2];
end
3'b010: begin // C.LW
is_lb_lh_lw_lbu_lhu <= 1;
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rd <= 8 + mem_rdata_latched[4:2];
end
3'b110: begin // C.SW
is_sb_sh_sw <= 1;
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= 8 + mem_rdata_latched[4:2];
end
endcase
end
2'b01: begin // Quadrant 1
case (mem_rdata_latched[15:13])
3'b000: begin // C.NOP / C.ADDI
is_alu_reg_imm <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[11:7];
end
3'b001: begin // C.JAL
instr_jal <= 1;
decoded_rd <= 1;
end
3'b 010: begin // C.LI
is_alu_reg_imm <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= 0;
end
3'b 011: begin
if (mem_rdata_latched[12] || mem_rdata_latched[6:2]) begin
if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP
is_alu_reg_imm <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[11:7];
end else begin // C.LUI
instr_lui <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= 0;
end
end
end
3'b100: begin
if (!mem_rdata_latched[11] && !mem_rdata_latched[12]) begin // C.SRLI, C.SRAI
is_alu_reg_imm <= 1;
decoded_rd <= 8 + mem_rdata_latched[9:7];
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
end
if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI
is_alu_reg_imm <= 1;
decoded_rd <= 8 + mem_rdata_latched[9:7];
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
end
if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND
is_alu_reg_reg <= 1;
decoded_rd <= 8 + mem_rdata_latched[9:7];
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= 8 + mem_rdata_latched[4:2];
end
end
3'b101: begin // C.J
instr_jal <= 1;
end
3'b110: begin // C.BEQZ
is_beq_bne_blt_bge_bltu_bgeu <= 1;
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= 0;
end
3'b111: begin // C.BNEZ
is_beq_bne_blt_bge_bltu_bgeu <= 1;
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= 0;
end
endcase
end
2'b10: begin // Quadrant 2
case (mem_rdata_latched[15:13])
3'b000: begin // C.SLLI
if (!mem_rdata_latched[12]) begin
is_alu_reg_imm <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[11:7];
decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
end
end
3'b010: begin // C.LWSP
if (mem_rdata_latched[11:7]) begin
is_lb_lh_lw_lbu_lhu <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= 2;
end
end
3'b100: begin
if (mem_rdata_latched[12] == 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JR
instr_jalr <= 1;
decoded_rd <= 0;
decoded_rs1 <= mem_rdata_latched[11:7];
end
if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV
is_alu_reg_reg <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= 0;
decoded_rs2 <= mem_rdata_latched[6:2];
end
if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR
instr_jalr <= 1;
decoded_rd <= 1;
decoded_rs1 <= mem_rdata_latched[11:7];
end
if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD
is_alu_reg_reg <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[11:7];
decoded_rs2 <= mem_rdata_latched[6:2];
end
end
3'b110: begin // C.SWSP
is_sb_sh_sw <= 1;
decoded_rs1 <= 2;
decoded_rs2 <= mem_rdata_latched[6:2];
end
endcase
end
endcase
end
end
if (decoder_trigger && !decoder_pseudo_trigger) begin
pcpi_insn <= WITH_PCPI ? mem_rdata_q : 'bx;
instr_beq <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b000;
instr_bne <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b001;
instr_blt <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b100;
instr_bge <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b101;
instr_bltu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b110;
instr_bgeu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b111;
instr_lb <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b000;
instr_lh <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b001;
instr_lw <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b010;
instr_lbu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b100;
instr_lhu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b101;
instr_sb <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b000;
instr_sh <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b001;
instr_sw <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b010;
instr_addi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b000;
instr_slti <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b010;
instr_sltiu <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b011;
instr_xori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b100;
instr_ori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b110;
instr_andi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b111;
instr_slli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000;
instr_srli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000;
instr_srai <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000;
instr_add <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0000000;
instr_sub <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0100000;
instr_sll <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000;
instr_slt <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b010 && mem_rdata_q[31:25] == 7'b0000000;
instr_sltu <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b011 && mem_rdata_q[31:25] == 7'b0000000;
instr_xor <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b100 && mem_rdata_q[31:25] == 7'b0000000;
instr_srl <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000;
instr_sra <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000;
instr_or <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b110 && mem_rdata_q[31:25] == 7'b0000000;
instr_and <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b111 && mem_rdata_q[31:25] == 7'b0000000;
instr_rdcycle <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000000000010) ||
(mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000100000010)) && ENABLE_COUNTERS;
instr_rdcycleh <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000000000010) ||
(mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000100000010)) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
instr_rdinstr <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000001000000010) && ENABLE_COUNTERS;
instr_rdinstrh <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000001000000010) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
instr_ecall_ebreak <= ((mem_rdata_q[6:0] == 7'b1110011 && !mem_rdata_q[31:21] && !mem_rdata_q[19:7]) ||
(COMPRESSED_ISA && mem_rdata_q[15:0] == 16'h9002));
instr_getq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
instr_setq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000001 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
instr_maskirq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000011 && ENABLE_IRQ;
instr_timer <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000101 && ENABLE_IRQ && ENABLE_IRQ_TIMER;
is_slli_srli_srai <= is_alu_reg_imm && |{
mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000,
mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000,
mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000
};
is_jalr_addi_slti_sltiu_xori_ori_andi <= instr_jalr || is_alu_reg_imm && |{
mem_rdata_q[14:12] == 3'b000,
mem_rdata_q[14:12] == 3'b010,
mem_rdata_q[14:12] == 3'b011,
mem_rdata_q[14:12] == 3'b100,
mem_rdata_q[14:12] == 3'b110,
mem_rdata_q[14:12] == 3'b111
};
is_sll_srl_sra <= is_alu_reg_reg && |{
mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000,
mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000,
mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000
};
is_lui_auipc_jal_jalr_addi_add_sub <= 0;
is_compare <= 0;
(* parallel_case *)
case (1'b1)
instr_jal:
decoded_imm <= decoded_imm_j;
|{instr_lui, instr_auipc}:
decoded_imm <= mem_rdata_q[31:12] << 12;
|{instr_jalr, is_lb_lh_lw_lbu_lhu, is_alu_reg_imm}:
decoded_imm <= $signed(mem_rdata_q[31:20]);
is_beq_bne_blt_bge_bltu_bgeu:
decoded_imm <= $signed({mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8], 1'b0});
is_sb_sh_sw:
decoded_imm <= $signed({mem_rdata_q[31:25], mem_rdata_q[11:7]});
default:
decoded_imm <= 1'bx;
endcase
end
if (!resetn) begin
is_beq_bne_blt_bge_bltu_bgeu <= 0;
is_compare <= 0;
instr_beq <= 0;
instr_bne <= 0;
instr_blt <= 0;
instr_bge <= 0;
instr_bltu <= 0;
instr_bgeu <= 0;
instr_addi <= 0;
instr_slti <= 0;
instr_sltiu <= 0;
instr_xori <= 0;
instr_ori <= 0;
instr_andi <= 0;
instr_add <= 0;
instr_sub <= 0;
instr_sll <= 0;
instr_slt <= 0;
instr_sltu <= 0;
instr_xor <= 0;
instr_srl <= 0;
instr_sra <= 0;
instr_or <= 0;
instr_and <= 0;
end
end
// Main State Machine
localparam cpu_state_trap = 8'b10000000;
localparam cpu_state_fetch = 8'b01000000;
localparam cpu_state_ld_rs1 = 8'b00100000;
localparam cpu_state_ld_rs2 = 8'b00010000;
localparam cpu_state_exec = 8'b00001000;
localparam cpu_state_shift = 8'b00000100;
localparam cpu_state_stmem = 8'b00000010;
localparam cpu_state_ldmem = 8'b00000001;
reg [7:0] cpu_state;
reg [1:0] irq_state;
`FORMAL_KEEP reg [127:0] dbg_ascii_state;
always @* begin
dbg_ascii_state = "";
if (cpu_state == cpu_state_trap) dbg_ascii_state = "trap";
if (cpu_state == cpu_state_fetch) dbg_ascii_state = "fetch";
if (cpu_state == cpu_state_ld_rs1) dbg_ascii_state = "ld_rs1";
if (cpu_state == cpu_state_ld_rs2) dbg_ascii_state = "ld_rs2";
if (cpu_state == cpu_state_exec) dbg_ascii_state = "exec";
if (cpu_state == cpu_state_shift) dbg_ascii_state = "shift";
if (cpu_state == cpu_state_stmem) dbg_ascii_state = "stmem";
if (cpu_state == cpu_state_ldmem) dbg_ascii_state = "ldmem";
end
reg set_mem_do_rinst;
reg set_mem_do_rdata;
reg set_mem_do_wdata;
reg latched_store;
reg latched_stalu;
reg latched_branch;
reg latched_compr;
reg latched_trace;
reg latched_is_lu;
reg latched_is_lh;
reg latched_is_lb;
reg [regindex_bits-1:0] latched_rd;
reg [31:0] current_pc;
assign next_pc = latched_store && latched_branch ? reg_out & ~1 : reg_next_pc;
reg [3:0] pcpi_timeout_counter;
reg pcpi_timeout;
reg [31:0] next_irq_pending;
reg do_waitirq;
reg [31:0] alu_out, alu_out_q;
reg alu_out_0, alu_out_0_q;
reg alu_wait, alu_wait_2;
reg [31:0] alu_add_sub;
reg [31:0] alu_shl, alu_shr;
reg alu_eq, alu_ltu, alu_lts;
generate if (TWO_CYCLE_ALU) begin
always @(posedge clk) begin
alu_add_sub <= instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
alu_eq <= reg_op1 == reg_op2;
alu_lts <= $signed(reg_op1) < $signed(reg_op2);
alu_ltu <= reg_op1 < reg_op2;
alu_shl <= reg_op1 << reg_op2[4:0];
alu_shr <= $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
end
end else begin
always @* begin
alu_add_sub = instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
alu_eq = reg_op1 == reg_op2;
alu_lts = $signed(reg_op1) < $signed(reg_op2);
alu_ltu = reg_op1 < reg_op2;
alu_shl = reg_op1 << reg_op2[4:0];
alu_shr = $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
end
end endgenerate
always @* begin
alu_out_0 = 'bx;
(* parallel_case, full_case *)
case (1'b1)
instr_beq:
alu_out_0 = alu_eq;
instr_bne:
alu_out_0 = !alu_eq;
instr_bge:
alu_out_0 = !alu_lts;
instr_bgeu:
alu_out_0 = !alu_ltu;
is_slti_blt_slt && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
alu_out_0 = alu_lts;
is_sltiu_bltu_sltu && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
alu_out_0 = alu_ltu;
endcase
alu_out = 'bx;
(* parallel_case, full_case *)
case (1'b1)
is_lui_auipc_jal_jalr_addi_add_sub:
alu_out = alu_add_sub;
is_compare:
alu_out = alu_out_0;
instr_xori || instr_xor:
alu_out = reg_op1 ^ reg_op2;
instr_ori || instr_or:
alu_out = reg_op1 | reg_op2;
instr_andi || instr_and:
alu_out = reg_op1 & reg_op2;
BARREL_SHIFTER && (instr_sll || instr_slli):
alu_out = alu_shl;
BARREL_SHIFTER && (instr_srl || instr_srli || instr_sra || instr_srai):
alu_out = alu_shr;
endcase
`ifdef RISCV_FORMAL_BLACKBOX_ALU
alu_out_0 = $anyseq;
alu_out = $anyseq;
`endif
end
reg clear_prefetched_high_word_q;
always @(posedge clk) clear_prefetched_high_word_q <= clear_prefetched_high_word;
always @* begin
clear_prefetched_high_word = clear_prefetched_high_word_q;
if (!prefetched_high_word)
clear_prefetched_high_word = 0;
if (latched_branch || irq_state || !resetn)
clear_prefetched_high_word = COMPRESSED_ISA;
end
reg cpuregs_write;
reg [31:0] cpuregs_wrdata;
reg [31:0] cpuregs_rs1;
reg [31:0] cpuregs_rs2;
reg [regindex_bits-1:0] decoded_rs;
always @* begin
cpuregs_write = 0;
cpuregs_wrdata = 'bx;
if (cpu_state == cpu_state_fetch) begin
(* parallel_case *)
case (1'b1)
latched_branch: begin
cpuregs_wrdata = reg_pc + (latched_compr ? 2 : 4);
cpuregs_write = 1;
end
latched_store && !latched_branch: begin
cpuregs_wrdata = latched_stalu ? alu_out_q : reg_out;
cpuregs_write = 1;
end
ENABLE_IRQ && irq_state[0]: begin
cpuregs_wrdata = reg_next_pc | latched_compr;
cpuregs_write = 1;
end
ENABLE_IRQ && irq_state[1]: begin
cpuregs_wrdata = irq_pending & ~irq_mask;
cpuregs_write = 1;
end
endcase
end
end
`ifndef PICORV32_REGS
always @(posedge clk) begin
if (resetn && cpuregs_write && latched_rd)
cpuregs[latched_rd] <= cpuregs_wrdata;
end
always @* begin
decoded_rs = 'bx;
if (ENABLE_REGS_DUALPORT) begin
`ifndef RISCV_FORMAL_BLACKBOX_REGS
cpuregs_rs1 = decoded_rs1 ? cpuregs[decoded_rs1] : 0;
cpuregs_rs2 = decoded_rs2 ? cpuregs[decoded_rs2] : 0;
`else
cpuregs_rs1 = decoded_rs1 ? $anyseq : 0;
cpuregs_rs2 = decoded_rs2 ? $anyseq : 0;
`endif
end else begin
decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
`ifndef RISCV_FORMAL_BLACKBOX_REGS
cpuregs_rs1 = decoded_rs ? cpuregs[decoded_rs] : 0;
`else
cpuregs_rs1 = decoded_rs ? $anyseq : 0;
`endif
cpuregs_rs2 = cpuregs_rs1;
end
end
`else
wire[31:0] cpuregs_rdata1;
wire[31:0] cpuregs_rdata2;
wire [5:0] cpuregs_waddr = latched_rd;
wire [5:0] cpuregs_raddr1 = ENABLE_REGS_DUALPORT ? decoded_rs1 : decoded_rs;
wire [5:0] cpuregs_raddr2 = ENABLE_REGS_DUALPORT ? decoded_rs2 : 0;
`PICORV32_REGS cpuregs (
.clk(clk),
.wen(resetn && cpuregs_write && latched_rd),
.waddr(cpuregs_waddr),
.raddr1(cpuregs_raddr1),
.raddr2(cpuregs_raddr2),
.wdata(cpuregs_wrdata),
.rdata1(cpuregs_rdata1),
.rdata2(cpuregs_rdata2)
);
always @* begin
decoded_rs = 'bx;
if (ENABLE_REGS_DUALPORT) begin
cpuregs_rs1 = decoded_rs1 ? cpuregs_rdata1 : 0;
cpuregs_rs2 = decoded_rs2 ? cpuregs_rdata2 : 0;
end else begin
decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
cpuregs_rs1 = decoded_rs ? cpuregs_rdata1 : 0;
cpuregs_rs2 = cpuregs_rs1;
end
end
`endif
assign launch_next_insn = cpu_state == cpu_state_fetch && decoder_trigger && (!ENABLE_IRQ || irq_delay || irq_active || !(irq_pending & ~irq_mask));
always @(posedge clk) begin
trap <= 0;
reg_sh <= 'bx;
reg_out <= 'bx;
set_mem_do_rinst = 0;
set_mem_do_rdata = 0;
set_mem_do_wdata = 0;
alu_out_0_q <= alu_out_0;
alu_out_q <= alu_out;
alu_wait <= 0;
alu_wait_2 <= 0;
if (launch_next_insn) begin
dbg_rs1val <= 'bx;
dbg_rs2val <= 'bx;
dbg_rs1val_valid <= 0;
dbg_rs2val_valid <= 0;
end
if (WITH_PCPI && CATCH_ILLINSN) begin
if (resetn && pcpi_valid && !pcpi_int_wait) begin
if (pcpi_timeout_counter)
pcpi_timeout_counter <= pcpi_timeout_counter - 1;
end else
pcpi_timeout_counter <= ~0;
pcpi_timeout <= !pcpi_timeout_counter;
end
if (ENABLE_COUNTERS) begin
count_cycle <= resetn ? count_cycle + 1 : 0;
if (!ENABLE_COUNTERS64) count_cycle[63:32] <= 0;
end else begin
count_cycle <= 'bx;
count_instr <= 'bx;
end
next_irq_pending = ENABLE_IRQ ? irq_pending & LATCHED_IRQ : 'bx;
if (ENABLE_IRQ && ENABLE_IRQ_TIMER && timer) begin
if (timer - 1 == 0)
next_irq_pending[irq_timer] = 1;
timer <= timer - 1;
end
if (ENABLE_IRQ) begin
next_irq_pending = next_irq_pending | irq;
end
decoder_trigger <= mem_do_rinst && mem_done;
decoder_trigger_q <= decoder_trigger;
decoder_pseudo_trigger <= 0;
decoder_pseudo_trigger_q <= decoder_pseudo_trigger;
do_waitirq <= 0;
trace_valid <= 0;
if (!ENABLE_TRACE)
trace_data <= 'bx;
if (!resetn) begin
reg_pc <= PROGADDR_RESET;
reg_next_pc <= PROGADDR_RESET;
if (ENABLE_COUNTERS)
count_instr <= 0;
latched_store <= 0;
latched_stalu <= 0;
latched_branch <= 0;
latched_trace <= 0;
latched_is_lu <= 0;
latched_is_lh <= 0;
latched_is_lb <= 0;
pcpi_valid <= 0;
pcpi_timeout <= 0;
irq_active <= 0;
irq_delay <= 0;
irq_mask <= ~0;
next_irq_pending = 0;
irq_state <= 0;
eoi <= 0;
timer <= 0;
if (~STACKADDR) begin
latched_store <= 1;
latched_rd <= 2;
reg_out <= STACKADDR;
end
cpu_state <= cpu_state_fetch;
end else
(* parallel_case, full_case *)
case (cpu_state)
cpu_state_trap: begin
trap <= 1;
end
cpu_state_fetch: begin
mem_do_rinst <= !decoder_trigger && !do_waitirq;
mem_wordsize <= 0;
current_pc = reg_next_pc;
(* parallel_case *)
case (1'b1)
latched_branch: begin
current_pc = latched_store ? (latched_stalu ? alu_out_q : reg_out) & ~1 : reg_next_pc;
`debug($display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + (latched_compr ? 2 : 4), current_pc);)
end
latched_store && !latched_branch: begin
`debug($display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out);)
end
ENABLE_IRQ && irq_state[0]: begin
current_pc = PROGADDR_IRQ;
irq_active <= 1;
mem_do_rinst <= 1;
end
ENABLE_IRQ && irq_state[1]: begin
eoi <= irq_pending & ~irq_mask;
next_irq_pending = next_irq_pending & irq_mask;
end
endcase
if (ENABLE_TRACE && latched_trace) begin
latched_trace <= 0;
trace_valid <= 1;
if (latched_branch)
trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_BRANCH | (current_pc & 32'hfffffffe);
else
trace_data <= (irq_active ? TRACE_IRQ : 0) | (latched_stalu ? alu_out_q : reg_out);
end
reg_pc <= current_pc;
reg_next_pc <= current_pc;
latched_store <= 0;
latched_stalu <= 0;
latched_branch <= 0;
latched_is_lu <= 0;
latched_is_lh <= 0;
latched_is_lb <= 0;
latched_rd <= decoded_rd;
latched_compr <= compressed_instr;
if (ENABLE_IRQ && ((decoder_trigger && !irq_active && !irq_delay && |(irq_pending & ~irq_mask)) || irq_state)) begin
irq_state <=
irq_state == 2'b00 ? 2'b01 :
irq_state == 2'b01 ? 2'b10 : 2'b00;
latched_compr <= latched_compr;
if (ENABLE_IRQ_QREGS)
latched_rd <= irqregs_offset | irq_state[0];
else
latched_rd <= irq_state[0] ? 4 : 3;
end else
if (ENABLE_IRQ && (decoder_trigger || do_waitirq) && instr_waitirq) begin
if (irq_pending) begin
latched_store <= 1;
reg_out <= irq_pending;
reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
mem_do_rinst <= 1;
end else
do_waitirq <= 1;
end else
if (decoder_trigger) begin
`debug($display("-- %-0t", $time);)
irq_delay <= irq_active;
reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
if (ENABLE_TRACE)
latched_trace <= 1;
if (ENABLE_COUNTERS) begin
count_instr <= count_instr + 1;
if (!ENABLE_COUNTERS64) count_instr[63:32] <= 0;
end
if (instr_jal) begin
mem_do_rinst <= 1;
reg_next_pc <= current_pc + decoded_imm_j;
latched_branch <= 1;
end else begin
mem_do_rinst <= 0;
mem_do_prefetch <= !instr_jalr && !instr_retirq;
cpu_state <= cpu_state_ld_rs1;
end
end
end
cpu_state_ld_rs1: begin
reg_op1 <= 'bx;
reg_op2 <= 'bx;
(* parallel_case *)
case (1'b1)
(CATCH_ILLINSN || WITH_PCPI) && instr_trap: begin
if (WITH_PCPI) begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
if (ENABLE_REGS_DUALPORT) begin
pcpi_valid <= 1;
`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
reg_sh <= cpuregs_rs2;
reg_op2 <= cpuregs_rs2;
dbg_rs2val <= cpuregs_rs2;
dbg_rs2val_valid <= 1;
if (pcpi_int_ready) begin
mem_do_rinst <= 1;
pcpi_valid <= 0;
reg_out <= pcpi_int_rd;
latched_store <= pcpi_int_wr;
cpu_state <= cpu_state_fetch;
end else
if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin
pcpi_valid <= 0;
`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
next_irq_pending[irq_ebreak] = 1;
cpu_state <= cpu_state_fetch;
end else
cpu_state <= cpu_state_trap;
end
end else begin
cpu_state <= cpu_state_ld_rs2;
end
end else begin
`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
next_irq_pending[irq_ebreak] = 1;
cpu_state <= cpu_state_fetch;
end else
cpu_state <= cpu_state_trap;
end
end
ENABLE_COUNTERS && is_rdcycle_rdcycleh_rdinstr_rdinstrh: begin
(* parallel_case, full_case *)
case (1'b1)
instr_rdcycle:
reg_out <= count_cycle[31:0];
instr_rdcycleh && ENABLE_COUNTERS64:
reg_out <= count_cycle[63:32];
instr_rdinstr:
reg_out <= count_instr[31:0];
instr_rdinstrh && ENABLE_COUNTERS64:
reg_out <= count_instr[63:32];
endcase
latched_store <= 1;
cpu_state <= cpu_state_fetch;
end
is_lui_auipc_jal: begin
reg_op1 <= instr_lui ? 0 : reg_pc;
reg_op2 <= decoded_imm;
if (TWO_CYCLE_ALU)
alu_wait <= 1;
else
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec;
end
ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_getq: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_out <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
latched_store <= 1;
cpu_state <= cpu_state_fetch;
end
ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_setq: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_out <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
latched_rd <= latched_rd | irqregs_offset;
latched_store <= 1;
cpu_state <= cpu_state_fetch;
end
ENABLE_IRQ && instr_retirq: begin
eoi <= 0;
irq_active <= 0;
latched_branch <= 1;
latched_store <= 1;
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_out <= CATCH_MISALIGN ? (cpuregs_rs1 & 32'h fffffffe) : cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
cpu_state <= cpu_state_fetch;
end
ENABLE_IRQ && instr_maskirq: begin
latched_store <= 1;
reg_out <= irq_mask;
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
irq_mask <= cpuregs_rs1 | MASKED_IRQ;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
cpu_state <= cpu_state_fetch;
end
ENABLE_IRQ && ENABLE_IRQ_TIMER && instr_timer: begin
latched_store <= 1;
reg_out <= timer;
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
timer <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
cpu_state <= cpu_state_fetch;
end
is_lb_lh_lw_lbu_lhu && !instr_trap: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
cpu_state <= cpu_state_ldmem;
mem_do_rinst <= 1;
end
is_slli_srli_srai && !BARREL_SHIFTER: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
reg_sh <= decoded_rs2;
cpu_state <= cpu_state_shift;
end
is_jalr_addi_slti_sltiu_xori_ori_andi, is_slli_srli_srai && BARREL_SHIFTER: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
reg_op2 <= is_slli_srli_srai && BARREL_SHIFTER ? decoded_rs2 : decoded_imm;
if (TWO_CYCLE_ALU)
alu_wait <= 1;
else
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec;
end
default: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
if (ENABLE_REGS_DUALPORT) begin
`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
reg_sh <= cpuregs_rs2;
reg_op2 <= cpuregs_rs2;
dbg_rs2val <= cpuregs_rs2;
dbg_rs2val_valid <= 1;
(* parallel_case *)
case (1'b1)
is_sb_sh_sw: begin
cpu_state <= cpu_state_stmem;
mem_do_rinst <= 1;
end
is_sll_srl_sra && !BARREL_SHIFTER: begin
cpu_state <= cpu_state_shift;
end
default: begin
if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
alu_wait <= 1;
end else
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec;
end
endcase
end else
cpu_state <= cpu_state_ld_rs2;
end
endcase
end
cpu_state_ld_rs2: begin
`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
reg_sh <= cpuregs_rs2;
reg_op2 <= cpuregs_rs2;
dbg_rs2val <= cpuregs_rs2;
dbg_rs2val_valid <= 1;
(* parallel_case *)
case (1'b1)
WITH_PCPI && instr_trap: begin
pcpi_valid <= 1;
if (pcpi_int_ready) begin
mem_do_rinst <= 1;
pcpi_valid <= 0;
reg_out <= pcpi_int_rd;
latched_store <= pcpi_int_wr;
cpu_state <= cpu_state_fetch;
end else
if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin
pcpi_valid <= 0;
`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
next_irq_pending[irq_ebreak] = 1;
cpu_state <= cpu_state_fetch;
end else
cpu_state <= cpu_state_trap;
end
end
is_sb_sh_sw: begin
cpu_state <= cpu_state_stmem;
mem_do_rinst <= 1;
end
is_sll_srl_sra && !BARREL_SHIFTER: begin
cpu_state <= cpu_state_shift;
end
default: begin
if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
alu_wait <= 1;
end else
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec;
end
endcase
end
cpu_state_exec: begin
reg_out <= reg_pc + decoded_imm;
if ((TWO_CYCLE_ALU || TWO_CYCLE_COMPARE) && (alu_wait || alu_wait_2)) begin
mem_do_rinst <= mem_do_prefetch && !alu_wait_2;
alu_wait <= alu_wait_2;
end else
if (is_beq_bne_blt_bge_bltu_bgeu) begin
latched_rd <= 0;
latched_store <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
latched_branch <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
if (mem_done)
cpu_state <= cpu_state_fetch;
if (TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0) begin
decoder_trigger <= 0;
set_mem_do_rinst = 1;
end
end else begin
latched_branch <= instr_jalr;
latched_store <= 1;
latched_stalu <= 1;
cpu_state <= cpu_state_fetch;
end
end
cpu_state_shift: begin
latched_store <= 1;
if (reg_sh == 0) begin
reg_out <= reg_op1;
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_fetch;
end else if (TWO_STAGE_SHIFT && reg_sh >= 4) begin
(* parallel_case, full_case *)
case (1'b1)
instr_slli || instr_sll: reg_op1 <= reg_op1 << 4;
instr_srli || instr_srl: reg_op1 <= reg_op1 >> 4;
instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 4;
endcase
reg_sh <= reg_sh - 4;
end else begin
(* parallel_case, full_case *)
case (1'b1)
instr_slli || instr_sll: reg_op1 <= reg_op1 << 1;
instr_srli || instr_srl: reg_op1 <= reg_op1 >> 1;
instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 1;
endcase
reg_sh <= reg_sh - 1;
end
end
cpu_state_stmem: begin
if (ENABLE_TRACE)
reg_out <= reg_op2;
if (!mem_do_prefetch || mem_done) begin
if (!mem_do_wdata) begin
(* parallel_case, full_case *)
case (1'b1)
instr_sb: mem_wordsize <= 2;
instr_sh: mem_wordsize <= 1;
instr_sw: mem_wordsize <= 0;
endcase
if (ENABLE_TRACE) begin
trace_valid <= 1;
trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff);
end
reg_op1 <= reg_op1 + decoded_imm;
set_mem_do_wdata = 1;
end
if (!mem_do_prefetch && mem_done) begin
cpu_state <= cpu_state_fetch;
decoder_trigger <= 1;
decoder_pseudo_trigger <= 1;
end
end
end
cpu_state_ldmem: begin
latched_store <= 1;
if (!mem_do_prefetch || mem_done) begin
if (!mem_do_rdata) begin
(* parallel_case, full_case *)
case (1'b1)
instr_lb || instr_lbu: mem_wordsize <= 2;
instr_lh || instr_lhu: mem_wordsize <= 1;
instr_lw: mem_wordsize <= 0;
endcase
latched_is_lu <= is_lbu_lhu_lw;
latched_is_lh <= instr_lh;
latched_is_lb <= instr_lb;
if (ENABLE_TRACE) begin
trace_valid <= 1;
trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff);
end
reg_op1 <= reg_op1 + decoded_imm;
set_mem_do_rdata = 1;
end
if (!mem_do_prefetch && mem_done) begin
(* parallel_case, full_case *)
case (1'b1)
latched_is_lu: reg_out <= mem_rdata_word;
latched_is_lh: reg_out <= $signed(mem_rdata_word[15:0]);
latched_is_lb: reg_out <= $signed(mem_rdata_word[7:0]);
endcase
decoder_trigger <= 1;
decoder_pseudo_trigger <= 1;
cpu_state <= cpu_state_fetch;
end
end
end
endcase
if (CATCH_MISALIGN && resetn && (mem_do_rdata || mem_do_wdata)) begin
if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin
`debug($display("MISALIGNED WORD: 0x%08x", reg_op1);)
if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
next_irq_pending[irq_buserror] = 1;
end else
cpu_state <= cpu_state_trap;
end
if (mem_wordsize == 1 && reg_op1[0] != 0) begin
`debug($display("MISALIGNED HALFWORD: 0x%08x", reg_op1);)
if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
next_irq_pending[irq_buserror] = 1;
end else
cpu_state <= cpu_state_trap;
end
end
if (CATCH_MISALIGN && resetn && mem_do_rinst && (COMPRESSED_ISA ? reg_pc[0] : |reg_pc[1:0])) begin
`debug($display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);)
if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
next_irq_pending[irq_buserror] = 1;
end else
cpu_state <= cpu_state_trap;
end
if (!CATCH_ILLINSN && decoder_trigger_q && !decoder_pseudo_trigger_q && instr_ecall_ebreak) begin
cpu_state <= cpu_state_trap;
end
if (!resetn || mem_done) begin
mem_do_prefetch <= 0;
mem_do_rinst <= 0;
mem_do_rdata <= 0;
mem_do_wdata <= 0;
end
if (set_mem_do_rinst)
mem_do_rinst <= 1;
if (set_mem_do_rdata)
mem_do_rdata <= 1;
if (set_mem_do_wdata)
mem_do_wdata <= 1;
irq_pending <= next_irq_pending & ~MASKED_IRQ;
if (!CATCH_MISALIGN) begin
if (COMPRESSED_ISA) begin
reg_pc[0] <= 0;
reg_next_pc[0] <= 0;
end else begin
reg_pc[1:0] <= 0;
reg_next_pc[1:0] <= 0;
end
end
current_pc = 'bx;
end
`ifdef RISCV_FORMAL
reg dbg_irq_call;
reg dbg_irq_enter;
reg [31:0] dbg_irq_ret;
always @(posedge clk) begin
rvfi_valid <= resetn && (launch_next_insn || trap) && dbg_valid_insn;
rvfi_order <= resetn ? rvfi_order + rvfi_valid : 0;
rvfi_insn <= dbg_insn_opcode;
rvfi_rs1_addr <= dbg_rs1val_valid ? dbg_insn_rs1 : 0;
rvfi_rs2_addr <= dbg_rs2val_valid ? dbg_insn_rs2 : 0;
rvfi_pc_rdata <= dbg_insn_addr;
rvfi_rs1_rdata <= dbg_rs1val_valid ? dbg_rs1val : 0;
rvfi_rs2_rdata <= dbg_rs2val_valid ? dbg_rs2val : 0;
rvfi_trap <= trap;
rvfi_halt <= trap;
rvfi_intr <= dbg_irq_enter;
rvfi_mode <= 3;
if (!resetn) begin
dbg_irq_call <= 0;
dbg_irq_enter <= 0;
end else
if (rvfi_valid) begin
dbg_irq_call <= 0;
dbg_irq_enter <= dbg_irq_call;
end else
if (irq_state == 1) begin
dbg_irq_call <= 1;
dbg_irq_ret <= next_pc;
end
if (!resetn) begin
rvfi_rd_addr <= 0;
rvfi_rd_wdata <= 0;
end else
if (cpuregs_write && !irq_state) begin
rvfi_rd_addr <= latched_rd;
rvfi_rd_wdata <= latched_rd ? cpuregs_wrdata : 0;
end else
if (rvfi_valid) begin
rvfi_rd_addr <= 0;
rvfi_rd_wdata <= 0;
end
casez (dbg_insn_opcode)
32'b 0000000_?????_000??_???_?????_0001011: begin // getq
rvfi_rs1_addr <= 0;
rvfi_rs1_rdata <= 0;
end
32'b 0000001_?????_?????_???_000??_0001011: begin // setq
rvfi_rd_addr <= 0;
rvfi_rd_wdata <= 0;
end
32'b 0000010_?????_00000_???_00000_0001011: begin // retirq
rvfi_rs1_addr <= 0;
rvfi_rs1_rdata <= 0;
end
endcase
if (!dbg_irq_call) begin
if (dbg_mem_instr) begin
rvfi_mem_addr <= 0;
rvfi_mem_rmask <= 0;
rvfi_mem_wmask <= 0;
rvfi_mem_rdata <= 0;
rvfi_mem_wdata <= 0;
end else
if (dbg_mem_valid && dbg_mem_ready) begin
rvfi_mem_addr <= dbg_mem_addr;
rvfi_mem_rmask <= dbg_mem_wstrb ? 0 : ~0;
rvfi_mem_wmask <= dbg_mem_wstrb;
rvfi_mem_rdata <= dbg_mem_rdata;
rvfi_mem_wdata <= dbg_mem_wdata;
end
end
end
always @* begin
rvfi_pc_wdata = dbg_irq_call ? dbg_irq_ret : dbg_insn_addr;
end
`endif
// Formal Verification
`ifdef FORMAL
reg [3:0] last_mem_nowait;
always @(posedge clk)
last_mem_nowait <= {last_mem_nowait, mem_ready || !mem_valid};
// stall the memory interface for max 4 cycles
restrict property (|last_mem_nowait || mem_ready || !mem_valid);
// resetn low in first cycle, after that resetn high
restrict property (resetn != $initstate);
// this just makes it much easier to read traces. uncomment as needed.
// assume property (mem_valid || !mem_ready);
reg ok;
always @* begin
if (resetn) begin
// instruction fetches are read-only
if (mem_valid && mem_instr)
assert (mem_wstrb == 0);
// cpu_state must be valid
ok = 0;
if (cpu_state == cpu_state_trap) ok = 1;
if (cpu_state == cpu_state_fetch) ok = 1;
if (cpu_state == cpu_state_ld_rs1) ok = 1;
if (cpu_state == cpu_state_ld_rs2) ok = !ENABLE_REGS_DUALPORT;
if (cpu_state == cpu_state_exec) ok = 1;
if (cpu_state == cpu_state_shift) ok = 1;
if (cpu_state == cpu_state_stmem) ok = 1;
if (cpu_state == cpu_state_ldmem) ok = 1;
assert (ok);
end
end
reg last_mem_la_read = 0;
reg last_mem_la_write = 0;
reg [31:0] last_mem_la_addr;
reg [31:0] last_mem_la_wdata;
reg [3:0] last_mem_la_wstrb = 0;
always @(posedge clk) begin
last_mem_la_read <= mem_la_read;
last_mem_la_write <= mem_la_write;
last_mem_la_addr <= mem_la_addr;
last_mem_la_wdata <= mem_la_wdata;
last_mem_la_wstrb <= mem_la_wstrb;
if (last_mem_la_read) begin
assert(mem_valid);
assert(mem_addr == last_mem_la_addr);
assert(mem_wstrb == 0);
end
if (last_mem_la_write) begin
assert(mem_valid);
assert(mem_addr == last_mem_la_addr);
assert(mem_wdata == last_mem_la_wdata);
assert(mem_wstrb == last_mem_la_wstrb);
end
if (mem_la_read || mem_la_write) begin
assert(!mem_valid || mem_ready);
end
end
`endif
endmodule
|
/***************************************************************
* picorv32_wb
***************************************************************/
module picorv32_top #(
parameter [ 0:0] ENABLE_COUNTERS = 1,
parameter [ 0:0] ENABLE_COUNTERS64 = 1,
parameter [ 0:0] ENABLE_REGS_16_31 = 1,
parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
parameter [ 0:0] TWO_STAGE_SHIFT = 1,
parameter [ 0:0] BARREL_SHIFTER = 0,
parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
parameter [ 0:0] TWO_CYCLE_ALU = 0,
parameter [ 0:0] COMPRESSED_ISA = 0,
parameter [ 0:0] CATCH_MISALIGN = 1,
parameter [ 0:0] CATCH_ILLINSN = 1,
parameter [ 0:0] ENABLE_PCPI = 0,
parameter [ 0:0] ENABLE_MUL = 0,
parameter [ 0:0] ENABLE_FAST_MUL = 0,
parameter [ 0:0] ENABLE_DIV = 0,
parameter [ 0:0] ENABLE_IRQ = 0,
parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
parameter [ 0:0] ENABLE_TRACE = 0,
parameter [ 0:0] REGS_INIT_ZERO = 0,
parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
parameter [31:0] STACKADDR = 32'h ffff_ffff
) (
output trap,
// Wishbone interfaces
input wb_rst_i,
input wb_clk_i,
output reg [31:0] wbm_adr_o,
output reg [31:0] wbm_dat_o,
input [31:0] wbm_dat_i,
output reg wbm_we_o,
output reg [3:0] wbm_sel_o,
output reg wbm_stb_o,
input wbm_ack_i,
output reg wbm_cyc_o,
// Pico Co-Processor Interface (PCPI)
output pcpi_valid,
output [31:0] pcpi_insn,
output [31:0] pcpi_rs1,
output [31:0] pcpi_rs2,
input pcpi_wr,
input [31:0] pcpi_rd,
input pcpi_wait,
input pcpi_ready,
// IRQ interface
input [31:0] irq,
output [31:0] eoi,
`ifdef RISCV_FORMAL
output rvfi_valid,
output [63:0] rvfi_order,
output [31:0] rvfi_insn,
output rvfi_trap,
output rvfi_halt,
output rvfi_intr,
output [ 4:0] rvfi_rs1_addr,
output [ 4:0] rvfi_rs2_addr,
output [31:0] rvfi_rs1_rdata,
output [31:0] rvfi_rs2_rdata,
output [ 4:0] rvfi_rd_addr,
output [31:0] rvfi_rd_wdata,
output [31:0] rvfi_pc_rdata,
output [31:0] rvfi_pc_wdata,
output [31:0] rvfi_mem_addr,
output [ 3:0] rvfi_mem_rmask,
output [ 3:0] rvfi_mem_wmask,
output [31:0] rvfi_mem_rdata,
output [31:0] rvfi_mem_wdata,
`endif
// Trace Interface
output trace_valid,
output [35:0] trace_data,
output mem_instr
);
wire mem_valid;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [ 3:0] mem_wstrb;
reg mem_ready;
reg [31:0] mem_rdata;
wire clk;
wire resetn;
assign clk = wb_clk_i;
assign resetn = ~wb_rst_i;
picorv32 #(
.ENABLE_COUNTERS (ENABLE_COUNTERS ),
.ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ),
.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
.TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
.BARREL_SHIFTER (BARREL_SHIFTER ),
.TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ),
.TWO_CYCLE_ALU (TWO_CYCLE_ALU ),
.COMPRESSED_ISA (COMPRESSED_ISA ),
.CATCH_MISALIGN (CATCH_MISALIGN ),
.CATCH_ILLINSN (CATCH_ILLINSN ),
.ENABLE_PCPI (ENABLE_PCPI ),
.ENABLE_MUL (ENABLE_MUL ),
.ENABLE_FAST_MUL (ENABLE_FAST_MUL ),
.ENABLE_DIV (ENABLE_DIV ),
.ENABLE_IRQ (ENABLE_IRQ ),
.ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
.ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
.ENABLE_TRACE (ENABLE_TRACE ),
.REGS_INIT_ZERO (REGS_INIT_ZERO ),
.MASKED_IRQ (MASKED_IRQ ),
.LATCHED_IRQ (LATCHED_IRQ ),
.PROGADDR_RESET (PROGADDR_RESET ),
.PROGADDR_IRQ (PROGADDR_IRQ ),
.STACKADDR (STACKADDR )
) picorv32_core (
.clk (clk ),
.resetn (resetn),
.trap (trap ),
.mem_valid(mem_valid),
.mem_addr (mem_addr ),
.mem_wdata(mem_wdata),
.mem_wstrb(mem_wstrb),
.mem_instr(mem_instr),
.mem_ready(mem_ready),
.mem_rdata(mem_rdata),
.pcpi_valid(pcpi_valid),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_wr ),
.pcpi_rd (pcpi_rd ),
.pcpi_wait (pcpi_wait ),
.pcpi_ready(pcpi_ready),
.irq(irq),
.eoi(eoi),
`ifdef RISCV_FORMAL
.rvfi_valid (rvfi_valid ),
.rvfi_order (rvfi_order ),
.rvfi_insn (rvfi_insn ),
.rvfi_trap (rvfi_trap ),
.rvfi_halt (rvfi_halt ),
.rvfi_intr (rvfi_intr ),
.rvfi_rs1_addr (rvfi_rs1_addr ),
.rvfi_rs2_addr (rvfi_rs2_addr ),
.rvfi_rs1_rdata(rvfi_rs1_rdata),
.rvfi_rs2_rdata(rvfi_rs2_rdata),
.rvfi_rd_addr (rvfi_rd_addr ),
.rvfi_rd_wdata (rvfi_rd_wdata ),
.rvfi_pc_rdata (rvfi_pc_rdata ),
.rvfi_pc_wdata (rvfi_pc_wdata ),
.rvfi_mem_addr (rvfi_mem_addr ),
.rvfi_mem_rmask(rvfi_mem_rmask),
.rvfi_mem_wmask(rvfi_mem_wmask),
.rvfi_mem_rdata(rvfi_mem_rdata),
.rvfi_mem_wdata(rvfi_mem_wdata),
`endif
.trace_valid(trace_valid),
.trace_data (trace_data)
);
localparam IDLE = 2'b00;
localparam WBSTART = 2'b01;
localparam WBEND = 2'b10;
reg [1:0] state;
wire we;
assign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]);
always @(posedge wb_clk_i) begin
if (wb_rst_i) begin
wbm_adr_o <= 0;
wbm_dat_o <= 0;
wbm_we_o <= 0;
wbm_sel_o <= 0;
wbm_stb_o <= 0;
wbm_cyc_o <= 0;
state <= IDLE;
end else begin
case (state)
IDLE: begin
if (mem_valid) begin
wbm_adr_o <= mem_addr;
wbm_dat_o <= mem_wdata;
wbm_we_o <= we;
wbm_sel_o <= mem_wstrb;
wbm_stb_o <= 1'b1;
wbm_cyc_o <= 1'b1;
state <= WBSTART;
end else begin
mem_ready <= 1'b0;
wbm_stb_o <= 1'b0;
wbm_cyc_o <= 1'b0;
wbm_we_o <= 1'b0;
end
end
WBSTART:begin
if (wbm_ack_i) begin
mem_rdata <= wbm_dat_i;
mem_ready <= 1'b1;
state <= WBEND;
wbm_stb_o <= 1'b0;
wbm_cyc_o <= 1'b0;
wbm_we_o <= 1'b0;
end
end
WBEND: begin
mem_ready <= 1'b0;
state <= IDLE;
end
default:
state <= IDLE;
endcase
end
end
endmodule
|
//*//***************************************************************
//* picorv32_wb
//***************************************************************//*
module picorv32_wb #(
parameter [ 0:0] ENABLE_COUNTERS = 1,
parameter [ 0:0] ENABLE_COUNTERS64 = 1,
parameter [ 0:0] ENABLE_REGS_16_31 = 1,
parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
parameter [ 0:0] TWO_STAGE_SHIFT = 1,
parameter [ 0:0] BARREL_SHIFTER = 0,
parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
parameter [ 0:0] TWO_CYCLE_ALU = 0,
parameter [ 0:0] COMPRESSED_ISA = 0,
parameter [ 0:0] CATCH_MISALIGN = 1,
parameter [ 0:0] CATCH_ILLINSN = 1,
parameter [ 0:0] ENABLE_PCPI = 0,
parameter [ 0:0] ENABLE_MUL = 0,
parameter [ 0:0] ENABLE_FAST_MUL = 0,
parameter [ 0:0] ENABLE_DIV = 0,
parameter [ 0:0] ENABLE_IRQ = 0,
parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
parameter [ 0:0] ENABLE_TRACE = 0,
parameter [ 0:0] REGS_INIT_ZERO = 0,
parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
parameter [31:0] STACKADDR = 32'h ffff_ffff
) (
output trap,
// Wishbone interfaces
input wb_rst_i,
input wb_clk_i,
output reg [31:0] wbm_adr_o,
output reg [31:0] wbm_dat_o,
input [31:0] wbm_dat_i,
output reg wbm_we_o,
output reg [3:0] wbm_sel_o,
output reg wbm_stb_o,
input wbm_ack_i,
output reg wbm_cyc_o,
// Pico Co-Processor Interface (PCPI)
output pcpi_valid,
output [31:0] pcpi_insn,
output [31:0] pcpi_rs1,
output [31:0] pcpi_rs2,
input pcpi_wr,
input [31:0] pcpi_rd,
input pcpi_wait,
input pcpi_ready,
// IRQ interface
input [31:0] irq,
output [31:0] eoi,
`ifdef RISCV_FORMAL
output rvfi_valid,
output [63:0] rvfi_order,
output [31:0] rvfi_insn,
output rvfi_trap,
output rvfi_halt,
output rvfi_intr,
output [ 4:0] rvfi_rs1_addr,
output [ 4:0] rvfi_rs2_addr,
output [31:0] rvfi_rs1_rdata,
output [31:0] rvfi_rs2_rdata,
output [ 4:0] rvfi_rd_addr,
output [31:0] rvfi_rd_wdata,
output [31:0] rvfi_pc_rdata,
output [31:0] rvfi_pc_wdata,
output [31:0] rvfi_mem_addr,
output [ 3:0] rvfi_mem_rmask,
output [ 3:0] rvfi_mem_wmask,
output [31:0] rvfi_mem_rdata,
output [31:0] rvfi_mem_wdata,
`endif
// Trace Interface
output trace_valid,
output [35:0] trace_data,
output mem_instr
);
wire mem_valid;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [ 3:0] mem_wstrb;
reg mem_ready;
reg [31:0] mem_rdata;
wire clk;
wire resetn;
assign clk = wb_clk_i;
assign resetn = ~wb_rst_i;
picorv32 #(
.ENABLE_COUNTERS (ENABLE_COUNTERS ),
.ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ),
.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
.TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
.BARREL_SHIFTER (BARREL_SHIFTER ),
.TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ),
.TWO_CYCLE_ALU (TWO_CYCLE_ALU ),
.COMPRESSED_ISA (COMPRESSED_ISA ),
.CATCH_MISALIGN (CATCH_MISALIGN ),
.CATCH_ILLINSN (CATCH_ILLINSN ),
.ENABLE_PCPI (ENABLE_PCPI ),
.ENABLE_MUL (ENABLE_MUL ),
.ENABLE_FAST_MUL (ENABLE_FAST_MUL ),
.ENABLE_DIV (ENABLE_DIV ),
.ENABLE_IRQ (ENABLE_IRQ ),
.ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
.ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
.ENABLE_TRACE (ENABLE_TRACE ),
.REGS_INIT_ZERO (REGS_INIT_ZERO ),
.MASKED_IRQ (MASKED_IRQ ),
.LATCHED_IRQ (LATCHED_IRQ ),
.PROGADDR_RESET (PROGADDR_RESET ),
.PROGADDR_IRQ (PROGADDR_IRQ ),
.STACKADDR (STACKADDR )
) picorv32_core (
.clk (clk ),
.resetn (resetn),
.trap (trap ),
.mem_valid(mem_valid),
.mem_addr (mem_addr ),
.mem_wdata(mem_wdata),
.mem_wstrb(mem_wstrb),
.mem_instr(mem_instr),
.mem_ready(mem_ready),
.mem_rdata(mem_rdata),
.pcpi_valid(pcpi_valid),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_wr ),
.pcpi_rd (pcpi_rd ),
.pcpi_wait (pcpi_wait ),
.pcpi_ready(pcpi_ready),
.irq(irq),
.eoi(eoi),
`ifdef RISCV_FORMAL
.rvfi_valid (rvfi_valid ),
.rvfi_order (rvfi_order ),
.rvfi_insn (rvfi_insn ),
.rvfi_trap (rvfi_trap ),
.rvfi_halt (rvfi_halt ),
.rvfi_intr (rvfi_intr ),
.rvfi_rs1_addr (rvfi_rs1_addr ),
.rvfi_rs2_addr (rvfi_rs2_addr ),
.rvfi_rs1_rdata(rvfi_rs1_rdata),
.rvfi_rs2_rdata(rvfi_rs2_rdata),
.rvfi_rd_addr (rvfi_rd_addr ),
.rvfi_rd_wdata (rvfi_rd_wdata ),
.rvfi_pc_rdata (rvfi_pc_rdata ),
.rvfi_pc_wdata (rvfi_pc_wdata ),
.rvfi_mem_addr (rvfi_mem_addr ),
.rvfi_mem_rmask(rvfi_mem_rmask),
.rvfi_mem_wmask(rvfi_mem_wmask),
.rvfi_mem_rdata(rvfi_mem_rdata),
.rvfi_mem_wdata(rvfi_mem_wdata),
`endif
.trace_valid(trace_valid),
.trace_data (trace_data)
);
localparam IDLE = 2'b00;
localparam WBSTART = 2'b01;
localparam WBEND = 2'b10;
reg [1:0] state;
wire we;
assign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]);
always @(posedge wb_clk_i) begin
if (wb_rst_i) begin
wbm_adr_o <= 0;
wbm_dat_o <= 0;
wbm_we_o <= 0;
wbm_sel_o <= 0;
wbm_stb_o <= 0;
wbm_cyc_o <= 0;
state <= IDLE;
end else begin
case (state)
IDLE: begin
if (mem_valid) begin
wbm_adr_o <= mem_addr;
wbm_dat_o <= mem_wdata;
wbm_we_o <= we;
wbm_sel_o <= mem_wstrb;
wbm_stb_o <= 1'b1;
wbm_cyc_o <= 1'b1;
state <= WBSTART;
end else begin
mem_ready <= 1'b0;
wbm_stb_o <= 1'b0;
wbm_cyc_o <= 1'b0;
wbm_we_o <= 1'b0;
end
end
WBSTART:begin
if (wbm_ack_i) begin
mem_rdata <= wbm_dat_i;
mem_ready <= 1'b1;
state <= WBEND;
wbm_stb_o <= 1'b0;
wbm_cyc_o <= 1'b0;
wbm_we_o <= 1'b0;
end
end
WBEND: begin
mem_ready <= 1'b0;
state <= IDLE;
end
default:
state <= IDLE;
endcase
end
end
endmodule
|
module ram_wb_01
#(//Wishbone parameters
parameter dw = 32,
parameter aw = 32,
// Memory parameters
parameter memory_file = "",
parameter mem_size_bytes = 32'h0000_5000, // 20KBytes
parameter mem_adr_width = 15) //(log2(mem_size_bytes));
(input wb_clk_i,
input wb_rst_i,
input [aw-1:0] wb_adr_i,
input [dw-1:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input [1:0] wb_bte_i,
input [2:0] wb_cti_i,
input wb_cyc_i,
input wb_stb_i,
output wb_ack_o,
output wb_err_o,
output wb_rty_o,
output [dw-1:0] wb_dat_o);
localparam bytes_per_dw = (dw/8);
localparam adr_width_for_num_word_bytes = 2; //(log2(bytes_per_dw))
localparam mem_words = (mem_size_bytes/bytes_per_dw);
// synthesis attribute ram_style of mem is block
reg [dw-1:0] mem [ 0 : mem_words-1 ] /* verilator public */ /* synthesis ram_style = no_rw_check */;
// Register to address internal memory array
reg [(mem_adr_width-adr_width_for_num_word_bytes)-1:0] addr_reg;
// Register to indicate if the cycle is a Wishbone B3-registered feedback
// type access
reg wb_b3_trans;
// Register to use for counting the addresses when doing burst accesses
reg [(mem_adr_width-adr_width_for_num_word_bytes)-1:0] burst_adr_r;
// Combinatorial next address calculation for bust accesses
reg [(mem_adr_width-adr_width_for_num_word_bytes)-1:0] adr;
// Logic to detect if there's a burst access going on
wire wb_b3_trans_start = ((wb_cti_i == 3'b001)|(wb_cti_i == 3'b010)) &
wb_stb_i & !wb_b3_trans & wb_cyc_i;
wire wb_b3_trans_stop = ((wb_cti_i == 3'b111) &
wb_stb_i & wb_b3_trans & wb_ack_o) | wb_err_o;
always @(posedge wb_clk_i)
if (wb_rst_i)
wb_b3_trans <= 0;
else if (wb_b3_trans_start)
wb_b3_trans <= 1;
else if (wb_b3_trans_stop)
wb_b3_trans <= 0;
// Register it locally
reg [1:0] wb_bte_i_r;
reg [2:0] wb_cti_i_r;
always @(posedge wb_clk_i) begin
wb_bte_i_r <= wb_bte_i;
wb_cti_i_r <= wb_cti_i;
end
// Burst address generation logic
always @(wb_ack_o or wb_b3_trans or wb_b3_trans_start
or wb_bte_i_r or wb_cti_i_r or wb_adr_i or burst_adr_r)
if (wb_b3_trans_start)
// Kick off adr, this assumes 4-byte words when getting
// address off incoming Wishbone bus address!
// So if dw is no longer 4 bytes, change this!
adr = wb_adr_i[mem_adr_width-1:2];
else if ((wb_cti_i_r == 3'b010) & wb_ack_o & wb_b3_trans) // Incrementing burst
case(wb_bte_i_r)
2'b00 : adr = burst_adr_r + 1; // Linear burst
2'b01 : begin
adr[1:0] = burst_adr_r[1:0] + 1; // 4-beat wrap burst
adr[(mem_adr_width-adr_width_for_num_word_bytes)-1:2] = burst_adr_r[(mem_adr_width-adr_width_for_num_word_bytes)-1:2];
end
2'b10 : begin
// 8-beat wrap burst
adr[2:0] = burst_adr_r[2:0] + 1;
adr[(mem_adr_width-adr_width_for_num_word_bytes)-1:3] = burst_adr_r[(mem_adr_width-adr_width_for_num_word_bytes)-1:3];
end
2'b11 : begin
// 16-beat wrap burst
adr[3:0] = burst_adr_r[3:0] + 1;
adr[(mem_adr_width-adr_width_for_num_word_bytes)-1:4] = burst_adr_r[(mem_adr_width-adr_width_for_num_word_bytes)-1:4];
end
default: adr = wb_adr_i[mem_adr_width-1:2];
endcase
else
adr = wb_adr_i[mem_adr_width-1:2];
wire using_burst_adr = wb_b3_trans;
wire burst_access_wrong_wb_adr = (using_burst_adr &
(burst_adr_r != wb_adr_i[mem_adr_width-1:2]));
// Address registering logic only for read
always@(posedge wb_clk_i)
if(wb_rst_i)
burst_adr_r <= 0;
else if (using_burst_adr)
burst_adr_r <= adr;
else if (wb_cyc_i & wb_stb_i)
burst_adr_r <= wb_adr_i[mem_adr_width-1:2];
assign wb_rty_o = 0;
// mux for data to ram, RMW on part sel != 4'hf
wire [31:0] wr_data;
assign wr_data[31:24] = wb_sel_i[3] ? wb_dat_i[31:24] : wb_dat_o[31:24];
assign wr_data[23:16] = wb_sel_i[2] ? wb_dat_i[23:16] : wb_dat_o[23:16];
assign wr_data[15: 8] = wb_sel_i[1] ? wb_dat_i[15: 8] : wb_dat_o[15: 8];
assign wr_data[ 7: 0] = wb_sel_i[0] ? wb_dat_i[ 7: 0] : wb_dat_o[ 7: 0];
wire ram_we = wb_we_i & wb_ack_o;
assign wb_dat_o = mem[addr_reg];
// Write logic
always @ (posedge wb_clk_i)
if (ram_we)
mem[adr] <= wr_data;
// Read logic
always @ (posedge wb_clk_i)
addr_reg <= adr;
// Ack Logic
reg wb_ack_o_r;
assign wb_ack_o = wb_ack_o_r & wb_stb_i & !burst_access_wrong_wb_adr;
//Handle wb_ack
always @ (posedge wb_clk_i)
if (wb_rst_i)
wb_ack_o_r <= 1'b0;
else if (wb_cyc_i) begin // We have bus
if (wb_cti_i == 3'b000) // Classic cycle acks
wb_ack_o_r <= wb_stb_i ^ wb_ack_o_r;
else if ((wb_cti_i == 3'b001) | (wb_cti_i == 3'b010)) // Increment/constant address bursts
wb_ack_o_r <= wb_stb_i;
else if (wb_cti_i == 3'b111) // End of cycle
wb_ack_o_r <= wb_stb_i & !wb_ack_o_r;
end else
wb_ack_o_r <= 0;
//
// Error signal generation
//
// OR in other errors here...
assign wb_err_o = wb_ack_o_r & wb_stb_i &
(burst_access_wrong_wb_adr);
//
// Access functions
//
/* Memory initialisation.
If not Verilator model, always do load, otherwise only load when called
from SystemC testbench.
*/
// Memory initialzation routine restored from old ram_wb component
integer k;
initial
begin
// synthesis translate_off
for(k = 0; k < (1 << mem_words); k = k + 1)
begin
mem[k] = 0;
end
// synthesis translate_on
$readmemh(memory_file, mem);
end
// synthesis translate_off
`ifdef verilator
// Function to access RAM (for use by Verilator).
function [31:0] get_mem32;
// verilator public
input [aw-1:0] addr;
get_mem32 = mem[addr];
endfunction // get_mem32
// Function to access RAM (for use by Verilator).
function [7:0] get_mem8;
// verilator public
input [aw-1:0] addr;
reg [31:0] temp_word;
begin
temp_word = mem[{addr[aw-1:2],2'd0}];
// Big endian mapping.
get_mem8 = (addr[1:0]==2'b00) ? temp_word[31:24] :
(addr[1:0]==2'b01) ? temp_word[23:16] :
(addr[1:0]==2'b10) ? temp_word[15:8] : temp_word[7:0];
end
endfunction // get_mem8
// Function to write RAM (for use by Verilator).
function set_mem32;
// verilator public
input [aw-1:0] addr;
input [dw-1:0] data;
begin
mem[addr] = data;
set_mem32 = data; // For avoiding ModelSim warning
end
endfunction // set_mem32
`endif // !`ifdef verilator
//synthesis translate_on
endmodule // ram_wb
|
module ram_wb_02
#(//Wishbone parameters
parameter dw = 32,
parameter aw = 32,
// Memory parameters
parameter memory_file = "",
parameter mem_size_bytes = 32'h0000_5000, // 20KBytes
parameter mem_adr_width = 15) //(log2(mem_size_bytes));
(input wb_clk_i,
input wb_rst_i,
input [aw-1:0] wb_adr_i,
input [dw-1:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input [1:0] wb_bte_i,
input [2:0] wb_cti_i,
input wb_cyc_i,
input wb_stb_i,
output wb_ack_o,
output wb_err_o,
output wb_rty_o,
output [dw-1:0] wb_dat_o);
localparam bytes_per_dw = (dw/8);
localparam adr_width_for_num_word_bytes = 2; //(log2(bytes_per_dw))
localparam mem_words = (mem_size_bytes/bytes_per_dw);
// synthesis attribute ram_style of mem is block
reg [dw-1:0] mem [ 0 : mem_words-1 ] /* verilator public */ /* synthesis ram_style = no_rw_check */;
// Register to address internal memory array
reg [(mem_adr_width-adr_width_for_num_word_bytes)-1:0] addr_reg;
// Register to indicate if the cycle is a Wishbone B3-registered feedback
// type access
reg wb_b3_trans;
// Register to use for counting the addresses when doing burst accesses
reg [(mem_adr_width-adr_width_for_num_word_bytes)-1:0] burst_adr_r;
// Combinatorial next address calculation for bust accesses
reg [(mem_adr_width-adr_width_for_num_word_bytes)-1:0] adr;
// Logic to detect if there's a burst access going on
wire wb_b3_trans_start = ((wb_cti_i == 3'b001)|(wb_cti_i == 3'b010)) &
wb_stb_i & !wb_b3_trans & wb_cyc_i;
wire wb_b3_trans_stop = ((wb_cti_i == 3'b111) &
wb_stb_i & wb_b3_trans & wb_ack_o) | wb_err_o;
always @(posedge wb_clk_i)
if (wb_rst_i)
wb_b3_trans <= 0;
else if (wb_b3_trans_start)
wb_b3_trans <= 1;
else if (wb_b3_trans_stop)
wb_b3_trans <= 0;
// Register it locally
reg [1:0] wb_bte_i_r;
reg [2:0] wb_cti_i_r;
always @(posedge wb_clk_i) begin
wb_bte_i_r <= wb_bte_i;
wb_cti_i_r <= wb_cti_i;
end
// Burst address generation logic
always @(wb_ack_o or wb_b3_trans or wb_b3_trans_start
or wb_bte_i_r or wb_cti_i_r or wb_adr_i or burst_adr_r)
if (wb_b3_trans_start)
// Kick off adr, this assumes 4-byte words when getting
// address off incoming Wishbone bus address!
// So if dw is no longer 4 bytes, change this!
adr = wb_adr_i[mem_adr_width-1:2];
else if ((wb_cti_i_r == 3'b010) & wb_ack_o & wb_b3_trans) // Incrementing burst
case(wb_bte_i_r)
2'b00 : adr = burst_adr_r + 1; // Linear burst
2'b01 : begin
adr[1:0] = burst_adr_r[1:0] + 1; // 4-beat wrap burst
adr[(mem_adr_width-adr_width_for_num_word_bytes)-1:2] = burst_adr_r[(mem_adr_width-adr_width_for_num_word_bytes)-1:2];
end
2'b10 : begin
// 8-beat wrap burst
adr[2:0] = burst_adr_r[2:0] + 1;
adr[(mem_adr_width-adr_width_for_num_word_bytes)-1:3] = burst_adr_r[(mem_adr_width-adr_width_for_num_word_bytes)-1:3];
end
2'b11 : begin
// 16-beat wrap burst
adr[3:0] = burst_adr_r[3:0] + 1;
adr[(mem_adr_width-adr_width_for_num_word_bytes)-1:4] = burst_adr_r[(mem_adr_width-adr_width_for_num_word_bytes)-1:4];
end
default: adr = wb_adr_i[mem_adr_width-1:2];
endcase
else
adr = wb_adr_i[mem_adr_width-1:2];
wire using_burst_adr = wb_b3_trans;
wire burst_access_wrong_wb_adr = (using_burst_adr &
(burst_adr_r != wb_adr_i[mem_adr_width-1:2]));
// Address registering logic only for read
always@(posedge wb_clk_i)
if(wb_rst_i)
burst_adr_r <= 0;
else if (using_burst_adr)
burst_adr_r <= adr;
else if (wb_cyc_i & wb_stb_i)
burst_adr_r <= wb_adr_i[mem_adr_width-1:2];
assign wb_rty_o = 0;
// mux for data to ram, RMW on part sel != 4'hf
wire [31:0] wr_data;
assign wr_data[31:24] = wb_sel_i[3] ? wb_dat_i[31:24] : wb_dat_o[31:24];
assign wr_data[23:16] = wb_sel_i[2] ? wb_dat_i[23:16] : wb_dat_o[23:16];
assign wr_data[15: 8] = wb_sel_i[1] ? wb_dat_i[15: 8] : wb_dat_o[15: 8];
assign wr_data[ 7: 0] = wb_sel_i[0] ? wb_dat_i[ 7: 0] : wb_dat_o[ 7: 0];
wire ram_we = wb_we_i & wb_ack_o;
assign wb_dat_o = mem[addr_reg];
// Write logic
always @ (posedge wb_clk_i)
if (ram_we)
mem[adr] <= wr_data;
// Read logic
always @ (posedge wb_clk_i)
addr_reg <= adr;
// Ack Logic
reg wb_ack_o_r;
assign wb_ack_o = wb_ack_o_r & wb_stb_i & !burst_access_wrong_wb_adr;
//Handle wb_ack
always @ (posedge wb_clk_i)
if (wb_rst_i)
wb_ack_o_r <= 1'b0;
else if (wb_cyc_i) begin // We have bus
if (wb_cti_i == 3'b000) // Classic cycle acks
wb_ack_o_r <= wb_stb_i ^ wb_ack_o_r;
else if ((wb_cti_i == 3'b001) | (wb_cti_i == 3'b010)) // Increment/constant address bursts
wb_ack_o_r <= wb_stb_i;
else if (wb_cti_i == 3'b111) // End of cycle
wb_ack_o_r <= wb_stb_i & !wb_ack_o_r;
end else
wb_ack_o_r <= 0;
//
// Error signal generation
//
// OR in other errors here...
assign wb_err_o = wb_ack_o_r & wb_stb_i &
(burst_access_wrong_wb_adr);
//
// Access functions
//
/* Memory initialisation.
If not Verilator model, always do load, otherwise only load when called
from SystemC testbench.
*/
// Memory initialzation routine restored from old ram_wb component
integer k;
initial
begin
// synthesis translate_off
for(k = 0; k < (1 << mem_words); k = k + 1)
begin
mem[k] = 0;
end
// synthesis translate_on
$readmemh(memory_file, mem);
end
// synthesis translate_off
`ifdef verilator
// Function to access RAM (for use by Verilator).
function [31:0] get_mem32;
// verilator public
input [aw-1:0] addr;
get_mem32 = mem[addr];
endfunction // get_mem32
// Function to access RAM (for use by Verilator).
function [7:0] get_mem8;
// verilator public
input [aw-1:0] addr;
reg [31:0] temp_word;
begin
temp_word = mem[{addr[aw-1:2],2'd0}];
// Big endian mapping.
get_mem8 = (addr[1:0]==2'b00) ? temp_word[31:24] :
(addr[1:0]==2'b01) ? temp_word[23:16] :
(addr[1:0]==2'b10) ? temp_word[15:8] : temp_word[7:0];
end
endfunction // get_mem8
// Function to write RAM (for use by Verilator).
function set_mem32;
// verilator public
input [aw-1:0] addr;
input [dw-1:0] data;
begin
mem[addr] = data;
set_mem32 = data; // For avoiding ModelSim warning
end
endfunction // set_mem32
`endif // !`ifdef verilator
//synthesis translate_on
endmodule // ram_wb
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is a round-robin arbiter for N participants, which is a
* parameter. The arbiter itself contains no register but is purely
* combinational which allows for various use cases. It simply
* calculates the next grant (nxt_gnt) based on the current grant
* (gnt) and the requests (req).
*
* That means, the gnt should in general be a register and especially
* there must be no combinational path from nxt_gnt to gnt!
*
* The normal usage is something like registering the gnt from
* nxt_gnt. Furthermore it is important that the gnt has an initial
* value which also must be one hot!
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module arb_rr
#(parameter N = 2)
(
input [N-1:0] req,
input en,
input [N-1:0] gnt,
output [N-1:0] nxt_gnt
);
// At a first glance, the computation of the nxt_gnt signal looks
// strange, but the principle is easy:
//
// * For each participant we compute a mask of width N. Based on
// the current gnt signal the mask contains a 1 at the position
// of other participants that will be served in round robin
// before the participant in case they request it.
//
// * The mask is 0 on all positions for the participant "left" of
// the currently granted participant as no other has precedence
// over this one. The mask has all one except the participant
// itself for the currently arbitrated participant.
//
// * From the mask and the request the nxt_gnt is calculated,
// roughly said as: if there is no other participant which has a
// higher precedence that also requests, the participant gets
// granted.
//
// Example 1:
// req = 1010
// gnt = 1000
// nxt_gnt = 0010
//
// mask[0] = 0000
// mask[1] = 0001
// mask[2] = 0011
// mask[3] = 0111
//
// Example 2:
// req = 1010
// gnt = 0100
// nxt_gnt = 1000
//
// mask[0] = 1000
// mask[1] = 1001
// mask[2] = 1011
// mask[3] = 0000
// Mask net
reg [N-1:0] mask [0:N-1];
// Calculate the mask
always @(*) begin : calc_mask
integer i,j;
for (i=0;i<N;i=i+1) begin
// Initialize mask as 0
mask[i] = {N{1'b0}};
// All participants to the "right" up to the current grant
// holder have precendence and therefore a 1 in the mask.
// First check if the next right from us has the grant.
// Afterwards the mask is calculated iteratively based on
// this.
if(i>0)
// For i=N:1 the next right is i-1
mask[i][i-1] = ~gnt[i-1];
else
// For i=0 the next right is N-1
mask[i][N-1] = ~gnt[N-1];
// Now the mask contains a 1 when the next right to us is not
// the grant holder. If it is the grant holder that means,
// that we are the next served (if necessary) as no other has
// higher precendence, which is then calculated in the
// following by filling up 1s up to the grant holder. To stop
// filling up there and not fill up any after this is
// iterative by always checking if the one before was not
// before the grant holder.
for (j=2;j<N;j=j+1) begin
if (i-j>=0)
mask[i][i-j] = mask[i][i-j+1] & ~gnt[i-j];
else if(i-j+1>=0)
mask[i][i-j+N] = mask[i][i-j+1] & ~gnt[i-j+N];
else
mask[i][i-j+N] = mask[i][i-j+N+1] & ~gnt[i-j+N];
end
end
end // always @ (*)
// Calculate the nxt_gnt
genvar k;
generate
for (k=0;k<N;k=k+1) begin : gen_nxt_gnt
// (mask[k] & req) masks all requests with higher precendence
// Example 1: 0: 0000 1: 0000 2: 0010 3: 0010
// Example 2: 0: 1000 1: 1000 2: 1010 3: 0000
//
// ~|(mask[k] & req) is there is none of them
// Example 1: 0: 1 1: 1 2: 0 3: 0
// Example 2: 1: 0 1: 0 2: 0 3: 1
//
// One might expect at this point that there was only one of
// them that matches, but this is guaranteed by the last part
// that is checking if this one has a request itself. In
// example 1, k=0 does not have a request, if it had, the
// result of the previous calculation would be 0 for k=1.
// Therefore: (~|(mask[k] & req) & req[k]) selects the next one.
// Example 1: 0: 0 1: 1 2: 0 3: 0
// Example 2: 0: 0 1: 0 2: 0 3: 1
//
// This is already the result. (0010 and 1000). Nevertheless,
// it is necessary to capture the case of no request at all
// (~|req). In that case, nxt_gnt would be 0, what iself
// leads to a problem in the next cycle (always grants).
// Therefore the current gnt is hold in case of no request by
// (~|req & gnt[k]).
//
// Finally, we only arbitrate when enable is set.
assign nxt_gnt[k] = en ? (~|(mask[k] & req) & req[k]) | (~|req & gnt[k])
: gnt[k];
end
endgenerate
endmodule // arb_rr
|
// Copyright 2016 by the authors
//
// Copyright and related rights are licensed under the Solderpad
// Hardware License, Version 0.51 (the "License"); you may not use
// this file except in compliance with the License. You may obtain a
// copy of the License at http://solderpad.org/licenses/SHL-0.51.
// Unless required by applicable law or agreed to in writing,
// software, hardware and materials distributed under this License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
// OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the
// License.
//
// Authors:
// Wei Song <[email protected]>
// Stefan Wallentowitz <[email protected]>
package dii_package;
typedef struct packed unsigned {
logic valid;
logic last;
logic [15:0] data;
} dii_flit;
function dii_flit
dii_flit_assemble(
input logic m_valid,
input logic m_last,
input logic [15:0] m_data
);
return dii_flit'{m_valid, m_last, m_data};
endfunction
endpackage // dii_package
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* As SystemVerilog allows for better definition of datatypes than
* the macros in lisnoc_def.vh this is provided for convenience.
* You always must assure that the settings correspond to the ones
* in Verilog.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
* Andreas Lankes <[email protected]>
* Michael Tempelmeier <[email protected]>
*/
typedef enum bit[4:0] {SELECT_NONE=0,SELECT_NORTH=1,SELECT_EAST=2,SELECT_SOUTH=4,SELECT_WEST=8,SELECT_LOCAL=16} dir_select_t;
`define NORTH 0
`define EAST 1
`define SOUTH 2
`define WEST 3
`define LOCAL 4
typedef enum bit [1:0] { HEADER=2'b01, SINGLE=2'b11, PAYLOAD=2'b00, LAST=2'b10 } flit_type_t;
class flit_t #(int data_width=32,int type_width=2);
bit [type_width-1:0] ftype;
bit [data_width-1:0] content;
endclass
class flit_header_t #(int data_width=32);
bit [4:0] dest;
bit [3:0] prio;
bit [2:0] packet_class;
bit [data_width-13:0] class_specific;
endclass
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This module implements the round robin scheme.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
* Andreas Lankes <[email protected]>
*
*/
`include "lisnoc_def.vh"
module lisnoc_arb_prio_rr(/*AUTOARG*/
// Outputs
nxt_gnt,
// Inputs
req, gnt
);
// Number of input ports in the design
parameter N = 2;
// inputs
input [N-1:0] req;
input [N-1:0] gnt;
// outputs
output reg [N-1:0] nxt_gnt;
// registers
reg [N-1:0] mask [0:N-1];
// wires
wire [N-1:0] nxt_gnt_tmp;
wire [N-1:0] msr;
integer i,j;
always @(*) begin
for (i=0;i<N;i=i+1) begin
mask[i] = {N{1'b0}};
if(i>0) begin
mask[i][i-1] = ~gnt[i-1];
end else begin
mask[i][N-1] = ~gnt[N-1];
end
for (j=2;j<N;j=j+1) begin
if (i-j>=0) begin
mask[i][i-j] = mask[i][i-j+1] & ~gnt[i-j];
end else if(i-j+1>=0) begin
mask[i][i-j+N] = mask[i][i-j+1] & ~gnt[i-j+N];
end else begin
mask[i][i-j+N] = mask[i][i-j+N+1] & ~gnt[i-j+N];
end
end
end
end
always @(*) begin
if (|nxt_gnt_tmp == 1) begin
nxt_gnt = nxt_gnt_tmp;
end else begin
nxt_gnt = msr;
end
end
genvar k;
generate
for (k=0;k<N;k=k+1) begin: nxtGnt
assign nxt_gnt_tmp[k] = (~|(mask[k] & req) & req[k]);
end
endgenerate
generate
for (k=0;k<N;k=k+1) begin: mostSignRequest
if (k==0) begin
assign msr[k] = req[k];
end else begin
assign msr[k] = req[k] & (~|req[k-1:0]);
end
end
endgenerate
endmodule // lisnoc_arb_prio_rr
`include "lisnoc_undef.vh"
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* Generic round robin arbiter.
*
* (c) 2011-2013 by the author(s)
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*
*/
module lisnoc_arb_rr(/*AUTOARG*/
// Outputs
nxt_gnt,
// Inputs
req, gnt
);
parameter N = 2;
input [N-1:0] req;
input [N-1:0] gnt;
output [N-1:0] nxt_gnt;
reg [N-1:0] mask [0:N-1];
integer i,j;
always @(*) begin
for (i=0;i<N;i=i+1) begin
mask[i] = {N{1'b0}};
if(i>0)
mask[i][i-1] = ~gnt[i-1];
else
mask[i][N-1] = ~gnt[N-1];
for (j=2;j<N;j=j+1) begin
if (i-j>=0)
mask[i][i-j] = mask[i][i-j+1] & ~gnt[i-j];
else if(i-j+1>=0)
mask[i][i-j+N] = mask[i][i-j+1] & ~gnt[i-j+N];
else
mask[i][i-j+N] = mask[i][i-j+N+1] & ~gnt[i-j+N];
end
end
end // always @ (*)
genvar k;
generate
for (k=0;k<N;k=k+1) begin
assign nxt_gnt[k] = (~|(mask[k] & req) & req[k]) | (~|req & gnt[k]);
end
endgenerate
endmodule // lisnoc_arb_rr
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the definition file. All Verilog macros are defined here.
* Please note, that it is not intended to be used for configuration
* (which should be done via parameters) but more for specific
* constants, that might change over longer time periods.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
* Andreas Lankes <[email protected]>
* Michael Tempelmeier <[email protected]>
*/
`define FLIT_TYPE_PAYLOAD 2'b00
`define FLIT_TYPE_HEADER 2'b01
`define FLIT_TYPE_LAST 2'b10
`define FLIT_TYPE_SINGLE 2'b11
// Convenience definitions for mesh
`define SELECT_NONE 5'b00000
`define SELECT_NORTH 5'b00001
`define SELECT_EAST 5'b00010
`define SELECT_SOUTH 5'b00100
`define SELECT_WEST 5'b01000
`define SELECT_LOCAL 5'b10000
`define NORTH 0
`define EAST 1
`define SOUTH 2
`define WEST 3
`define LOCAL 4
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the toplevel file of the DMA controller.
*
* Author(s):
* Michael Tempelmeier <[email protected]>
* Stefan Wallentowitz <[email protected]>
*/
`include "lisnoc_dma_def.vh"
module lisnoc_dma(/*AUTOARG*/
// Outputs
noc_in_req_ready, noc_in_resp_ready, noc_out_req_flit,
noc_out_req_valid, noc_out_resp_flit, noc_out_resp_valid,
wb_if_dat_o, wb_if_ack_o, wb_if_err_o, wb_if_rty_o, wb_adr_o,
wb_dat_o, wb_cyc_o, wb_stb_o, wb_sel_o, wb_we_o, wb_cab_o,
wb_cti_o, wb_bte_o, irq,
// Inputs
clk, rst, noc_in_req_flit, noc_in_req_valid, noc_in_resp_flit,
noc_in_resp_valid, noc_out_req_ready, noc_out_resp_ready,
wb_if_adr_i, wb_if_dat_i, wb_if_cyc_i, wb_if_stb_i, wb_if_we_i,
wb_dat_i, wb_ack_i
);
parameter table_entries = 4;
localparam table_entries_ptrwidth = $clog2(table_entries);
parameter tileid = 0;
parameter noc_packet_size = 16;
parameter generate_interrupt = 1;
input clk;
input rst;
input [`FLIT_WIDTH-1:0] noc_in_req_flit;
input noc_in_req_valid;
output noc_in_req_ready;
input [`FLIT_WIDTH-1:0] noc_in_resp_flit;
input noc_in_resp_valid;
output noc_in_resp_ready;
output [`FLIT_WIDTH-1:0] noc_out_req_flit;
output noc_out_req_valid;
input noc_out_req_ready;
output [`FLIT_WIDTH-1:0] noc_out_resp_flit;
output noc_out_resp_valid;
input noc_out_resp_ready;
input [31:0] wb_if_adr_i;
input [31:0] wb_if_dat_i;
input wb_if_cyc_i;
input wb_if_stb_i;
input wb_if_we_i;
output [31:0] wb_if_dat_o;
output wb_if_ack_o;
output wb_if_err_o;
output wb_if_rty_o;
output reg [31:0] wb_adr_o;
output reg [31:0] wb_dat_o;
output reg wb_cyc_o;
output reg wb_stb_o;
output reg [3:0] wb_sel_o;
output reg wb_we_o;
output wb_cab_o;
output reg [2:0] wb_cti_o;
output reg [1:0] wb_bte_o;
input [31:0] wb_dat_i;
input wb_ack_i;
output [table_entries-1:0] irq;
assign wb_if_err_o = 1'b0;
assign wb_if_rty_o = 1'b0;
wire [31:0] wb_req_adr_o;
wire [31:0] wb_req_dat_o;
wire wb_req_cyc_o;
wire wb_req_stb_o;
wire wb_req_we_o;
wire [3:0] wb_req_sel_o;
wire [2:0] wb_req_cti_o;
wire [1:0] wb_req_bte_o;
reg [31:0] wb_req_dat_i;
reg wb_req_ack_i;
wire [31:0] wb_resp_adr_o;
wire [31:0] wb_resp_dat_o;
wire wb_resp_cyc_o;
wire wb_resp_stb_o;
wire wb_resp_we_o;
wire [3:0] wb_resp_sel_o;
wire [2:0] wb_resp_cti_o;
wire [1:0] wb_resp_bte_o;
reg [31:0] wb_resp_dat_i;
reg wb_resp_ack_i;
wire [31:0] wb_target_adr_o;
wire [31:0] wb_target_dat_o;
wire wb_target_cyc_o;
wire wb_target_stb_o;
wire wb_target_we_o;
wire [2:0] wb_target_cti_o;
wire [1:0] wb_target_bte_o;
reg [31:0] wb_target_dat_i;
reg wb_target_ack_i;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire ctrl_done_en; // From ctrl_initiator of lisnoc_dma_initiator.v
wire [table_entries_ptrwidth-1:0] ctrl_done_pos;// From ctrl_initiator of lisnoc_dma_initiator.v
wire [table_entries_ptrwidth-1:0] ctrl_read_pos;// From ctrl_initiator of lisnoc_dma_initiator.v
wire [`DMA_REQUEST_WIDTH-1:0] ctrl_read_req; // From request_table of lisnoc_dma_request_table.v
wire [table_entries-1:0] done; // From request_table of lisnoc_dma_request_table.v
wire if_valid_en; // From wbinterface of lisnoc_dma_wbinterface.v
wire [table_entries_ptrwidth-1:0] if_valid_pos;// From wbinterface of lisnoc_dma_wbinterface.v
wire if_valid_set; // From wbinterface of lisnoc_dma_wbinterface.v
wire if_validrd_en; // From wbinterface of lisnoc_dma_wbinterface.v
wire if_write_en; // From wbinterface of lisnoc_dma_wbinterface.v
wire [table_entries_ptrwidth-1:0] if_write_pos;// From wbinterface of lisnoc_dma_wbinterface.v
wire [`DMA_REQUEST_WIDTH-1:0] if_write_req; // From wbinterface of lisnoc_dma_wbinterface.v
wire [`DMA_REQMASK_WIDTH-1:0] if_write_select;// From wbinterface of lisnoc_dma_wbinterface.v
wire [table_entries-1:0] valid; // From request_table of lisnoc_dma_request_table.v
wire [3:0] wb_target_sel_o; // From target of lisnoc_dma_target.v
// End of automatics
wire [table_entries_ptrwidth-1:0] ctrl_out_read_pos;
wire [table_entries_ptrwidth-1:0] ctrl_in_read_pos;
wire [table_entries_ptrwidth-1:0] ctrl_write_pos;
assign ctrl_out_read_pos = 0;
assign ctrl_in_read_pos = 0;
assign ctrl_write_pos = 0;
lisnoc_dma_wbinterface
#(.tileid(tileid))
wbinterface(/*AUTOINST*/
// Outputs
.wb_if_dat_o (wb_if_dat_o[31:0]),
.wb_if_ack_o (wb_if_ack_o),
.if_write_req (if_write_req[`DMA_REQUEST_WIDTH-1:0]),
.if_write_pos (if_write_pos[table_entries_ptrwidth-1:0]),
.if_write_select (if_write_select[`DMA_REQMASK_WIDTH-1:0]),
.if_write_en (if_write_en),
.if_valid_pos (if_valid_pos[table_entries_ptrwidth-1:0]),
.if_valid_set (if_valid_set),
.if_valid_en (if_valid_en),
.if_validrd_en (if_validrd_en),
// Inputs
.clk (clk),
.rst (rst),
.wb_if_adr_i (wb_if_adr_i[31:0]),
.wb_if_dat_i (wb_if_dat_i[31:0]),
.wb_if_cyc_i (wb_if_cyc_i),
.wb_if_stb_i (wb_if_stb_i),
.wb_if_we_i (wb_if_we_i),
.done (done[table_entries-1:0]));
lisnoc_dma_request_table
#(.generate_interrupt(generate_interrupt))
request_table(/*AUTOINST*/
// Outputs
.ctrl_read_req (ctrl_read_req[`DMA_REQUEST_WIDTH-1:0]),
.valid (valid[table_entries-1:0]),
.done (done[table_entries-1:0]),
.irq (irq[table_entries-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.if_write_req (if_write_req[`DMA_REQUEST_WIDTH-1:0]),
.if_write_pos (if_write_pos[table_entries_ptrwidth-1:0]),
.if_write_select (if_write_select[`DMA_REQMASK_WIDTH-1:0]),
.if_write_en (if_write_en),
.if_valid_pos (if_valid_pos[table_entries_ptrwidth-1:0]),
.if_valid_set (if_valid_set),
.if_valid_en (if_valid_en),
.if_validrd_en (if_validrd_en),
.ctrl_read_pos (ctrl_read_pos[table_entries_ptrwidth-1:0]),
.ctrl_done_pos (ctrl_done_pos[table_entries_ptrwidth-1:0]),
.ctrl_done_en (ctrl_done_en));
/* lisnoc_dma_initiator AUTO_TEMPLATE(
.noc_out_\(.*\) (noc_out_req_\1[]),
.noc_in_\(.*\) (noc_in_resp_\1[]),
); */
lisnoc_dma_initiator
#(.tileid(tileid))
ctrl_initiator(/*AUTOINST*/
// Outputs
.ctrl_read_pos (ctrl_read_pos[table_entries_ptrwidth-1:0]),
.ctrl_done_pos (ctrl_done_pos[table_entries_ptrwidth-1:0]),
.ctrl_done_en (ctrl_done_en),
.noc_out_flit (noc_out_req_flit[`FLIT_WIDTH-1:0]), // Templated
.noc_out_valid (noc_out_req_valid), // Templated
.noc_in_ready (noc_in_resp_ready), // Templated
.wb_req_cyc_o (wb_req_cyc_o),
.wb_req_stb_o (wb_req_stb_o),
.wb_req_we_o (wb_req_we_o),
.wb_req_dat_o (wb_req_dat_o[31:0]),
.wb_req_adr_o (wb_req_adr_o[31:0]),
.wb_req_cti_o (wb_req_cti_o[2:0]),
.wb_req_bte_o (wb_req_bte_o[1:0]),
.wb_req_sel_o (wb_req_sel_o[3:0]),
.wb_resp_cyc_o (wb_resp_cyc_o),
.wb_resp_stb_o (wb_resp_stb_o),
.wb_resp_we_o (wb_resp_we_o),
.wb_resp_dat_o (wb_resp_dat_o[31:0]),
.wb_resp_adr_o (wb_resp_adr_o[31:0]),
.wb_resp_cti_o (wb_resp_cti_o[2:0]),
.wb_resp_bte_o (wb_resp_bte_o[1:0]),
.wb_resp_sel_o (wb_resp_sel_o[3:0]),
// Inputs
.clk (clk),
.rst (rst),
.ctrl_read_req (ctrl_read_req[`DMA_REQUEST_WIDTH-1:0]),
.valid (valid[table_entries-1:0]),
.noc_out_ready (noc_out_req_ready), // Templated
.noc_in_flit (noc_in_resp_flit[`FLIT_WIDTH-1:0]), // Templated
.noc_in_valid (noc_in_resp_valid), // Templated
.wb_req_ack_i (wb_req_ack_i),
.wb_req_dat_i (wb_req_dat_i[31:0]),
.wb_resp_ack_i (wb_resp_ack_i),
.wb_resp_dat_i (wb_resp_dat_i[31:0]));
/* lisnoc_dma_target AUTO_TEMPLATE(
.noc_out_\(.*\) (noc_out_resp_\1[]),
.noc_in_\(.*\) (noc_in_req_\1[]),
.wb_\(.*\) (wb_target_\1[]),
); */
lisnoc_dma_target
#(.tileid(tileid),.noc_packet_size(noc_packet_size))
target(/*AUTOINST*/
// Outputs
.noc_out_flit (noc_out_resp_flit[`FLIT_WIDTH-1:0]), // Templated
.noc_out_valid (noc_out_resp_valid), // Templated
.noc_in_ready (noc_in_req_ready), // Templated
.wb_cyc_o (wb_target_cyc_o), // Templated
.wb_stb_o (wb_target_stb_o), // Templated
.wb_we_o (wb_target_we_o), // Templated
.wb_dat_o (wb_target_dat_o[31:0]), // Templated
.wb_adr_o (wb_target_adr_o[31:0]), // Templated
.wb_sel_o (wb_target_sel_o[3:0]), // Templated
.wb_cti_o (wb_target_cti_o[2:0]), // Templated
.wb_bte_o (wb_target_bte_o[1:0]), // Templated
// Inputs
.clk (clk),
.rst (rst),
.noc_out_ready (noc_out_resp_ready), // Templated
.noc_in_flit (noc_in_req_flit[`FLIT_WIDTH-1:0]), // Templated
.noc_in_valid (noc_in_req_valid), // Templated
.wb_ack_i (wb_target_ack_i), // Templated
.wb_dat_i (wb_target_dat_i[31:0])); // Templated
localparam wb_arb_req = 2'b00, wb_arb_resp = 2'b01, wb_arb_target = 2'b10;
reg [1:0] wb_arb;
reg [1:0] nxt_wb_arb;
always @(posedge clk) begin
if (rst) begin
wb_arb <= wb_arb_target;
end else begin
wb_arb <= nxt_wb_arb;
end
end
wire wb_arb_active;
assign wb_arb_active = ((wb_arb == wb_arb_req) & wb_req_cyc_o) |
((wb_arb == wb_arb_resp) & wb_resp_cyc_o) |
((wb_arb == wb_arb_target) & wb_target_cyc_o);
always @(*) begin
if (wb_arb_active) begin
nxt_wb_arb = wb_arb;
end else begin
if (wb_target_cyc_o) begin
nxt_wb_arb = wb_arb_target;
end else if (wb_resp_cyc_o) begin
nxt_wb_arb = wb_arb_resp;
end else if (wb_req_cyc_o) begin
nxt_wb_arb = wb_arb_req;
end else begin
nxt_wb_arb = wb_arb_target;
end
end
end
assign wb_cab_o = 1'b0;
always @(*) begin
if (wb_arb == wb_arb_target) begin
wb_adr_o = wb_target_adr_o;
wb_dat_o = wb_target_dat_o;
wb_cyc_o = wb_target_cyc_o;
wb_stb_o = wb_target_stb_o;
wb_sel_o = wb_target_sel_o;
wb_we_o = wb_target_we_o;
wb_bte_o = wb_target_bte_o;
wb_cti_o = wb_target_cti_o;
wb_target_ack_i = wb_ack_i;
wb_target_dat_i = wb_dat_i;
wb_req_ack_i = 1'b0;
wb_req_dat_i = 32'hx;
wb_resp_ack_i = 1'b0;
wb_resp_dat_i = 32'hx;
end else if (wb_arb == wb_arb_resp) begin
wb_adr_o = wb_resp_adr_o;
wb_dat_o = wb_resp_dat_o;
wb_cyc_o = wb_resp_cyc_o;
wb_stb_o = wb_resp_stb_o;
wb_sel_o = wb_resp_sel_o;
wb_we_o = wb_resp_we_o;
wb_bte_o = wb_resp_bte_o;
wb_cti_o = wb_resp_cti_o;
wb_resp_ack_i = wb_ack_i;
wb_resp_dat_i = wb_dat_i;
wb_req_ack_i = 1'b0;
wb_req_dat_i = 32'hx;
wb_target_ack_i = 1'b0;
wb_target_dat_i = 32'hx;
end else if (wb_arb == wb_arb_req) begin
wb_adr_o = wb_req_adr_o;
wb_dat_o = wb_req_dat_o;
wb_cyc_o = wb_req_cyc_o;
wb_stb_o = wb_req_stb_o;
wb_sel_o = wb_req_sel_o;
wb_we_o = wb_req_we_o;
wb_bte_o = wb_req_bte_o;
wb_cti_o = wb_req_cti_o;
wb_req_ack_i = wb_ack_i;
wb_req_dat_i = wb_dat_i;
wb_resp_ack_i = 1'b0;
wb_resp_dat_i = 32'hx;
wb_target_ack_i = 1'b0;
wb_target_dat_i = 32'hx;
end else begin // if (wb_arb == wb_arb_req)
wb_adr_o = 32'h0;
wb_dat_o = 32'h0;
wb_cyc_o = 1'b0;
wb_stb_o = 1'b0;
wb_sel_o = 4'h0;
wb_we_o = 1'b0;
wb_bte_o = 2'b00;
wb_cti_o = 3'b000;
wb_req_ack_i = 1'b0;
wb_req_dat_i = 32'hx;
wb_resp_ack_i = 1'b0;
wb_resp_dat_i = 32'hx;
wb_target_ack_i = 1'b0;
wb_target_dat_i = 32'hx;
end
end
endmodule // lisnoc_dma
`include "lisnoc_dma_undef.vh"
|
`include "lisnoc_def.vh"
`define FLIT_WIDTH 34
// Type of flit
// The coding is chosen, so that
// type[0] signals that this is the first flit of a packet
// type[1] signals that this is the last flit of a packet
`define FLIT_TYPE_MSB (`FLIT_WIDTH - 1)
`define FLIT_TYPE_WIDTH 2
`define FLIT_TYPE_LSB (`FLIT_TYPE_MSB - `FLIT_TYPE_WIDTH + 1)
// This is the flit content size
`define FLIT_CONTENT_WIDTH 32
`define FLIT_CONTENT_MSB 31
`define FLIT_CONTENT_LSB 0
// The following fields are only valid for header flits
`define FLIT_DEST_WIDTH 5
// destination address field of header flit
`define FLIT_DEST_MSB `FLIT_CONTENT_MSB
`define FLIT_DEST_LSB `FLIT_DEST_MSB - `FLIT_DEST_WIDTH + 1
// packet type field of header flit
`define PACKET_CLASS_MSB (`FLIT_DEST_LSB - 1)
`define PACKET_CLASS_WIDTH 3
`define PACKET_CLASS_LSB (`PACKET_CLASS_MSB - `PACKET_CLASS_WIDTH + 1)
`define PACKET_CLASS_DMA 3'b010
// source address field of header flit
`define SOURCE_MSB 23
`define SOURCE_WIDTH 5
`define SOURCE_LSB 19
// packet id field of header flit
`define PACKET_ID_MSB 18
`define PACKET_ID_WIDTH 4
`define PACKET_ID_LSB 15
`define PACKET_TYPE_MSB 14
`define PACKET_TYPE_WIDTH 2
`define PACKET_TYPE_LSB 13
`define PACKET_TYPE_L2R_REQ 2'b00
`define PACKET_TYPE_R2L_REQ 2'b01
`define PACKET_TYPE_L2R_RESP 2'b10
`define PACKET_TYPE_R2L_RESP 2'b11
`define PACKET_REQ_LAST 12
`define PACKET_RESP_LAST 12
`define SIZE_MSB 31
`define SIZE_WIDTH 32
`define SIZE_LSB 0
`define DMA_REQUEST_WIDTH 103
`define DMA_REQFIELD_LADDR_WIDTH 32
`define DMA_REQFIELD_SIZE_WIDTH 32
`define DMA_REQFIELD_RTILE_WIDTH 5
`define DMA_REQFIELD_RADDR_WIDTH 32
`define DMA_REQFIELD_LADDR_MSB 102
`define DMA_REQFIELD_LADDR_LSB 70
`define DMA_REQFIELD_SIZE_MSB 69
`define DMA_REQFIELD_SIZE_LSB 38
`define DMA_REQFIELD_RTILE_MSB 37
`define DMA_REQFIELD_RTILE_LSB 33
`define DMA_REQFIELD_RADDR_MSB 32
`define DMA_REQFIELD_RADDR_LSB 1
`define DMA_REQFIELD_DIR 0
`define DMA_REQUEST_INVALID 1'b0
`define DMA_REQUEST_VALID 1'b1
`define DMA_REQUEST_L2R 1'b0
`define DMA_REQUEST_R2L 1'b1
`define DMA_REQMASK_WIDTH 5
`define DMA_REQMASK_LADDR 0
`define DMA_REQMASK_SIZE 1
`define DMA_REQMASK_RTILE 2
`define DMA_REQMASK_RADDR 3
`define DMA_REQMASK_DIR 4
`define DMA_RESPFIELD_SIZE_WIDTH 14
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* The module behaving as initiator in DMA transfers.
*
* (c) 2011-2013 by the author(s)
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*
*/
`include "lisnoc_def.vh"
`include "lisnoc_dma_def.vh"
module lisnoc_dma_initiator (/*AUTOARG*/
// Outputs
ctrl_read_pos, ctrl_done_pos, ctrl_done_en, noc_out_flit,
noc_out_valid, noc_in_ready, wb_req_cyc_o, wb_req_stb_o,
wb_req_we_o, wb_req_dat_o, wb_req_adr_o, wb_req_cti_o,
wb_req_bte_o, wb_req_sel_o, wb_resp_cyc_o, wb_resp_stb_o,
wb_resp_we_o, wb_resp_dat_o, wb_resp_adr_o, wb_resp_cti_o,
wb_resp_bte_o, wb_resp_sel_o,
// Inputs
clk, rst, ctrl_read_req, valid, noc_out_ready, noc_in_flit,
noc_in_valid, wb_req_ack_i, wb_req_dat_i, wb_resp_ack_i,
wb_resp_dat_i
);
//parameters
parameter table_entries = 4;
localparam table_entries_ptrwidth = $clog2(table_entries);
parameter tileid = 0;
parameter noc_packet_size = 16;
input clk;
input rst;
// Control read (request) interface
output [table_entries_ptrwidth-1:0] ctrl_read_pos;
input [`DMA_REQUEST_WIDTH-1:0] ctrl_read_req;
output [table_entries_ptrwidth-1:0] ctrl_done_pos;
output ctrl_done_en;
input [table_entries-1:0] valid;
// NOC-Interface
output [`FLIT_WIDTH-1:0] noc_out_flit;
output noc_out_valid;
input noc_out_ready;
input [`FLIT_WIDTH-1:0] noc_in_flit;
input noc_in_valid;
output noc_in_ready;
// Wishbone interface for L2R data fetch
input wb_req_ack_i;
output wb_req_cyc_o, wb_req_stb_o;
output wb_req_we_o;
input [31:0] wb_req_dat_i;
output [31:0] wb_req_dat_o;
output [31:0] wb_req_adr_o;
output [2:0] wb_req_cti_o;
output [1:0] wb_req_bte_o;
output [3:0] wb_req_sel_o;
// Wishbone interface for L2R data fetch
input wb_resp_ack_i;
output wb_resp_cyc_o, wb_resp_stb_o;
output wb_resp_we_o;
input [31:0] wb_resp_dat_i;
output [31:0] wb_resp_dat_o;
output [31:0] wb_resp_adr_o;
output [2:0] wb_resp_cti_o;
output [1:0] wb_resp_bte_o;
output [3:0] wb_resp_sel_o;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] req_data; // From u_wbreq of lisnoc_dma_initiator_wbreq.v
wire req_data_ready; // From u_nocreq of lisnoc_dma_initiator_nocreq.v
wire req_data_valid; // From u_wbreq of lisnoc_dma_initiator_wbreq.v
wire req_is_l2r; // From u_nocreq of lisnoc_dma_initiator_nocreq.v
wire [31:0] req_laddr; // From u_nocreq of lisnoc_dma_initiator_nocreq.v
wire [`DMA_REQFIELD_SIZE_WIDTH-3:0] req_size;// From u_nocreq of lisnoc_dma_initiator_nocreq.v
wire req_start; // From u_nocreq of lisnoc_dma_initiator_nocreq.v
// End of automatics
lisnoc_dma_initiator_wbreq
u_wbreq(/*AUTOINST*/
// Outputs
.wb_req_cyc_o (wb_req_cyc_o),
.wb_req_stb_o (wb_req_stb_o),
.wb_req_we_o (wb_req_we_o),
.wb_req_dat_o (wb_req_dat_o[31:0]),
.wb_req_adr_o (wb_req_adr_o[31:0]),
.wb_req_cti_o (wb_req_cti_o[2:0]),
.wb_req_bte_o (wb_req_bte_o[1:0]),
.wb_req_sel_o (wb_req_sel_o[3:0]),
.req_data_valid (req_data_valid),
.req_data (req_data[31:0]),
// Inputs
.clk (clk),
.rst (rst),
.wb_req_ack_i (wb_req_ack_i),
.wb_req_dat_i (wb_req_dat_i[31:0]),
.req_start (req_start),
.req_is_l2r (req_is_l2r),
.req_size (req_size[`DMA_REQFIELD_SIZE_WIDTH-3:0]),
.req_laddr (req_laddr[31:0]),
.req_data_ready (req_data_ready));
lisnoc_dma_initiator_nocreq
#(.tileid(tileid),.noc_packet_size(noc_packet_size))
u_nocreq(/*AUTOINST*/
// Outputs
.noc_out_flit (noc_out_flit[`FLIT_WIDTH-1:0]),
.noc_out_valid (noc_out_valid),
.ctrl_read_pos (ctrl_read_pos[table_entries_ptrwidth-1:0]),
.req_start (req_start),
.req_laddr (req_laddr[31:0]),
.req_data_ready (req_data_ready),
.req_is_l2r (req_is_l2r),
.req_size (req_size[`DMA_REQFIELD_SIZE_WIDTH-3:0]),
// Inputs
.clk (clk),
.rst (rst),
.noc_out_ready (noc_out_ready),
.ctrl_read_req (ctrl_read_req[`DMA_REQUEST_WIDTH-1:0]),
.valid (valid[table_entries-1:0]),
.ctrl_done_pos (ctrl_done_pos[table_entries_ptrwidth-1:0]),
.ctrl_done_en (ctrl_done_en),
.req_data_valid (req_data_valid),
.req_data (req_data[31:0]));
/* lisnoc_dma_initiator_nocresp AUTO_TEMPLATE(
.wb_\(.*\) (wb_resp_\1[]),
); */
lisnoc_dma_initiator_nocresp
#(.noc_packet_size(noc_packet_size))
u_nocresp(/*AUTOINST*/
// Outputs
.noc_in_ready (noc_in_ready),
.wb_cyc_o (wb_resp_cyc_o), // Templated
.wb_stb_o (wb_resp_stb_o), // Templated
.wb_we_o (wb_resp_we_o), // Templated
.wb_dat_o (wb_resp_dat_o[31:0]), // Templated
.wb_adr_o (wb_resp_adr_o[31:0]), // Templated
.wb_cti_o (wb_resp_cti_o[2:0]), // Templated
.wb_bte_o (wb_resp_bte_o[1:0]), // Templated
.wb_sel_o (wb_resp_sel_o[3:0]), // Templated
.ctrl_done_pos (ctrl_done_pos[table_entries_ptrwidth-1:0]),
.ctrl_done_en (ctrl_done_en),
// Inputs
.clk (clk),
.rst (rst),
.noc_in_flit (noc_in_flit[`FLIT_WIDTH-1:0]),
.noc_in_valid (noc_in_valid),
.wb_ack_i (wb_resp_ack_i), // Templated
.wb_dat_i (wb_resp_dat_i[31:0])); // Templated
endmodule // lisnoc_dma_ctrl_req
`include "lisnoc_undef.vh"
`include "lisnoc_dma_undef.vh"
// Local Variables:
// verilog-library-directories:("." "../" "../infrastructure")
// verilog-auto-inst-param-value: t
// End:
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This modules generates the requests for DMA transfers.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*
*/
`include "lisnoc_def.vh"
`include "lisnoc_dma_def.vh"
module lisnoc_dma_initiator_nocreq (/*AUTOARG*/
// Outputs
noc_out_flit, noc_out_valid, ctrl_read_pos, req_start, req_laddr,
req_data_ready, req_is_l2r, req_size,
// Inputs
clk, rst, noc_out_ready, ctrl_read_req, valid, ctrl_done_pos,
ctrl_done_en, req_data_valid, req_data
);
parameter table_entries = 4;
localparam table_entries_ptrwidth = $clog2(table_entries);
parameter tileid = 0;
parameter noc_packet_size = 16; // flits per packet
input clk, rst;
// NOC-Interface
output reg [`FLIT_WIDTH-1:0] noc_out_flit;
output reg noc_out_valid;
input noc_out_ready;
// Control read (request) interface
output reg [table_entries_ptrwidth-1:0] ctrl_read_pos;
input [`DMA_REQUEST_WIDTH-1:0] ctrl_read_req;
input [table_entries-1:0] valid;
// Feedback from response path
input [table_entries_ptrwidth-1:0] ctrl_done_pos;
input ctrl_done_en;
// Interface to wishbone request
output reg req_start;
output [31:0] req_laddr;
input req_data_valid;
output reg req_data_ready;
input [31:0] req_data;
output req_is_l2r;
output [`DMA_REQFIELD_SIZE_WIDTH-3:0] req_size;
//
// NOC request
//
localparam NOC_REQ_WIDTH = 4;
localparam NOC_REQ_IDLE = 4'b0000;
localparam NOC_REQ_L2R_GENHDR = 4'b0001;
localparam NOC_REQ_L2R_GENADDR = 4'b0010;
localparam NOC_REQ_L2R_DATA = 4'b0011;
localparam NOC_REQ_L2R_WAITDATA = 4'b0100;
localparam NOC_REQ_R2L_GENHDR = 4'b0101;
localparam NOC_REQ_R2L_GENSIZE = 4'b1000;
localparam NOC_REQ_R2L_GENRADDR = 4'b0110;
localparam NOC_REQ_R2L_GENLADDR = 4'b0111;
// State logic
reg [NOC_REQ_WIDTH-1:0] noc_req_state;
reg [NOC_REQ_WIDTH-1:0] nxt_noc_req_state;
// Counter for payload flits/words in request
reg [`DMA_REQFIELD_SIZE_WIDTH-1:0] noc_req_counter;
reg [`DMA_REQFIELD_SIZE_WIDTH-1:0] nxt_noc_req_counter;
// Current packet payload flit/word counter
reg [4:0] noc_req_packet_count;
reg [4:0] nxt_noc_req_packet_count;
// Current packet total number of flits/words
reg [4:0] noc_req_packet_size;
reg [4:0] nxt_noc_req_packet_size;
/*
* Table entry selection logic
*
* The request table signals all open requests on the 'valid' bit vector.
* The selection logic arbitrates among those entries to determine the
* request to be handled next.
*
* The arbitration is not done for all entries marked as valid but only
* for those, that are additionally not marked in the open_responses
* bit vector.
*
* The selection signals only change after a transfer is started.
*/
// Selects the next entry from the table
reg [table_entries-1:0] select; // current grant of arbiter
wire [table_entries-1:0] nxt_select; // next grant of arbiter
// Store open responses: table entry valid is not sufficient, as
// current requests would be selected
reg [table_entries-1:0] open_responses;
reg [table_entries-1:0] nxt_open_responses;
wire [table_entries-1:0] requests;
assign requests = valid & ~open_responses & {table_entries{(noc_req_state == NOC_REQ_IDLE)}};
/* lisnoc_arb_rr AUTO_TEMPLATE(
.nxt_gnt (nxt_select),
.gnt (select),
.req (requests),
); */
// Round robin (rr) arbiter
lisnoc_arb_rr
#(.N(table_entries))
u_select(/*AUTOINST*/
// Outputs
.nxt_gnt (nxt_select), // Templated
// Inputs
.req (requests), // Templated
.gnt (select)); // Templated
// register next select to select
always @(posedge clk) begin
if (rst) begin
select <= 0;
end else begin
select <= nxt_select;
end
end
// Convert (one hot) select bit vector to binary
always @(*) begin : readpos_onehottobinary
integer d;
ctrl_read_pos = 0;
for (d=0;d<table_entries;d=d+1)
if (select[d])
ctrl_read_pos = ctrl_read_pos | d;
end
/*
*
* Request generation
*
*/
wire nxt_req_start;
// This is a pulse that signals the start of a request to the wishbone and noc
// part of the request generation.
assign nxt_req_start = // start when any is valid and not already in progress
(|(valid & ~open_responses) &
// and we are not currently generating a request (pulse)
(noc_req_state == NOC_REQ_IDLE));
// Convenience wires
wire [`DMA_REQFIELD_RTILE_WIDTH-1:0] req_rtile;
wire [31:0] req_raddr;
assign req_is_l2r = (ctrl_read_req[`DMA_REQFIELD_DIR] == `DMA_REQUEST_L2R);
assign req_laddr = ctrl_read_req[`DMA_REQFIELD_LADDR_MSB:`DMA_REQFIELD_LADDR_LSB];
assign req_size = ctrl_read_req[`DMA_REQFIELD_SIZE_MSB:`DMA_REQFIELD_SIZE_LSB];
assign req_rtile = ctrl_read_req[`DMA_REQFIELD_RTILE_MSB:`DMA_REQFIELD_RTILE_LSB];
assign req_raddr = ctrl_read_req[`DMA_REQFIELD_RADDR_MSB:`DMA_REQFIELD_RADDR_LSB];
//
// NoC side request generation
//
// next state logic, counters, control signals
always @(*) begin
// Default is not generating flits
noc_out_valid = 1'b0;
noc_out_flit = 34'h0;
// Only pop when successfull transfer
req_data_ready = 1'b0;
// Counters stay old value
nxt_noc_req_counter = noc_req_counter;
nxt_noc_req_packet_count = noc_req_packet_count;
nxt_noc_req_packet_size = noc_req_packet_size;
// Open response only changes when request generated
nxt_open_responses = open_responses;
case(noc_req_state)
NOC_REQ_IDLE: begin
// Idle'ing
if (req_start)
// A valid request exists, that is not open
if (req_is_l2r)
// L2R
nxt_noc_req_state = NOC_REQ_L2R_GENHDR;
else
// R2L
nxt_noc_req_state = NOC_REQ_R2L_GENHDR;
else
// wait for request
nxt_noc_req_state = NOC_REQ_IDLE;
// Reset counter
nxt_noc_req_counter = 0;
end
NOC_REQ_L2R_GENHDR: begin
noc_out_valid = 1'b1;
noc_out_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB] = `FLIT_TYPE_HEADER;
noc_out_flit[`FLIT_DEST_MSB:`FLIT_DEST_LSB] = req_rtile;
noc_out_flit[`PACKET_CLASS_MSB:`PACKET_CLASS_LSB] = `PACKET_CLASS_DMA;
noc_out_flit[`PACKET_ID_MSB:`PACKET_ID_LSB] = ctrl_read_pos;
noc_out_flit[`SOURCE_MSB:`SOURCE_LSB] = tileid;
noc_out_flit[`PACKET_TYPE_MSB:`PACKET_TYPE_LSB] = `PACKET_TYPE_L2R_REQ;
if ((noc_req_counter + (noc_packet_size-2)) < req_size) begin
// This is not the last packet in the request (noc_packet_size-2)
noc_out_flit[`SIZE_MSB:`SIZE_LSB] = noc_packet_size-2;
noc_out_flit[`PACKET_REQ_LAST] = 1'b0;
nxt_noc_req_packet_size = noc_packet_size-2;
// count is the current transfer number
nxt_noc_req_packet_count = 5'd1;
end else begin
// This is the last packet in the request
noc_out_flit[`SIZE_MSB:`SIZE_LSB] = req_size - noc_req_counter;
noc_out_flit[`PACKET_REQ_LAST] = 1'b1;
nxt_noc_req_packet_size = req_size - noc_req_counter;
// count is the current transfer number
nxt_noc_req_packet_count = 5'd1;
end // else: !if((noc_req_counter + (noc_packet_size-2)) < req_size)
// change to next state if successful
if (noc_out_ready)
nxt_noc_req_state = NOC_REQ_L2R_GENADDR;
else
nxt_noc_req_state = NOC_REQ_L2R_GENHDR;
end // case: NOC_REQ_GENHDR
NOC_REQ_L2R_GENADDR: begin
noc_out_valid = 1'b1;
noc_out_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB] = `FLIT_TYPE_PAYLOAD;
noc_out_flit[`FLIT_CONTENT_MSB:`FLIT_CONTENT_LSB] = req_raddr + (noc_req_counter << 2);
if (noc_out_ready) begin
nxt_noc_req_state = NOC_REQ_L2R_DATA;
end else begin
nxt_noc_req_state = NOC_REQ_L2R_GENADDR;
end
end
NOC_REQ_L2R_DATA: begin
// transfer data to noc if available
noc_out_valid = req_data_valid;
// Signal last flit for this transfer
if (noc_req_packet_count==noc_req_packet_size) begin
noc_out_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB] = `FLIT_TYPE_LAST;
end else begin
noc_out_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB] = `FLIT_TYPE_PAYLOAD;
end
noc_out_flit[`FLIT_CONTENT_MSB:`FLIT_CONTENT_LSB] = req_data;
if (noc_out_ready & noc_out_valid) begin
// transfer was successful
// signal to data fifo
req_data_ready = 1'b1;
// increment the counter for this packet
nxt_noc_req_packet_count = noc_req_packet_count + 1;
if (noc_req_packet_count == noc_req_packet_size) begin
// This was the last flit in this packet
if (noc_req_packet_count+noc_req_counter == req_size) begin
// .. and the last flit for the request
// keep open_responses and "add" currently selected request to it
nxt_open_responses = open_responses | select;
// back to IDLE
nxt_noc_req_state = NOC_REQ_IDLE;
end else begin
// .. and other packets to transfer
// Start with next header
nxt_noc_req_state = NOC_REQ_L2R_GENHDR;
// add the current counter to overall counter
nxt_noc_req_counter = noc_req_counter + noc_req_packet_count;
end
end else begin // if (noc_req_packet_count == noc_req_packet_size)
// we transfered a flit inside the packet
nxt_noc_req_state = NOC_REQ_L2R_DATA;
end
end else begin // if (noc_out_ready & noc_out_valid)
// no success
nxt_noc_req_state = NOC_REQ_L2R_DATA;
end
end // case: NOC_REQ_L2R_DATA
NOC_REQ_R2L_GENHDR: begin
noc_out_valid = 1'b1;
noc_out_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB] = `FLIT_TYPE_HEADER;
noc_out_flit[`FLIT_DEST_MSB:`FLIT_DEST_LSB] = req_rtile;
noc_out_flit[`PACKET_CLASS_MSB:`PACKET_CLASS_LSB] = `PACKET_CLASS_DMA;
noc_out_flit[`PACKET_ID_MSB:`PACKET_ID_LSB] = ctrl_read_pos;
noc_out_flit[`SOURCE_MSB:`SOURCE_LSB] = tileid;
noc_out_flit[`PACKET_TYPE_MSB:`PACKET_TYPE_LSB] = `PACKET_TYPE_R2L_REQ;
noc_out_flit[11:0] = 0;
// There's only one packet needed for the request
noc_out_flit[`PACKET_REQ_LAST] = 1'b1;
// change to next state if successful
if (noc_out_ready)
nxt_noc_req_state = NOC_REQ_R2L_GENSIZE;
else
nxt_noc_req_state = NOC_REQ_R2L_GENHDR;
end // case: NOC_REQ_GENHDR
NOC_REQ_R2L_GENSIZE: begin
noc_out_valid = 1'b1;
noc_out_flit[`SIZE_MSB:`SIZE_LSB] = req_size;
// change to next state if successful
if (noc_out_ready)
nxt_noc_req_state = NOC_REQ_R2L_GENRADDR;
else
nxt_noc_req_state = NOC_REQ_R2L_GENSIZE;
end // case: NOC_REQ_R2L_GENSIZE
NOC_REQ_R2L_GENRADDR: begin
noc_out_valid = 1'b1;
noc_out_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB] = `FLIT_TYPE_PAYLOAD;
noc_out_flit[`FLIT_CONTENT_MSB:`FLIT_CONTENT_LSB] = ctrl_read_req[`DMA_REQFIELD_RADDR_MSB:`DMA_REQFIELD_RADDR_LSB];
if (noc_out_ready) begin
// keep open_responses and "add" currently selected request to it
nxt_noc_req_state = NOC_REQ_R2L_GENLADDR;
end else begin
nxt_noc_req_state = NOC_REQ_R2L_GENRADDR;
end
end // case: NOC_REQ_R2L_GENRADDR
NOC_REQ_R2L_GENLADDR: begin
noc_out_valid = 1'b1;
noc_out_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB] = `FLIT_TYPE_LAST;
noc_out_flit[`FLIT_CONTENT_MSB:`FLIT_CONTENT_LSB] = ctrl_read_req[`DMA_REQFIELD_LADDR_MSB:`DMA_REQFIELD_LADDR_LSB];
if (noc_out_ready) begin
// keep open_responses and "add" currently selected request to it
nxt_open_responses = open_responses | select;
nxt_noc_req_state = NOC_REQ_IDLE;
end else begin
nxt_noc_req_state = NOC_REQ_R2L_GENLADDR;
end
end // case: NOC_REQ_R2L_GENLADDR
default: begin
nxt_noc_req_state = NOC_REQ_IDLE;
end
endcase // case (noc_req_state)
// Process done information from response
if (ctrl_done_en) begin
nxt_open_responses[ctrl_done_pos] = 1'b0;
end
end
// sequential part of NoC interface
always @(posedge clk) begin
if (rst) begin
noc_req_state <= NOC_REQ_IDLE;
noc_req_counter <= 0;
noc_req_packet_size <= 5'h0;
noc_req_packet_count <= 5'h0;
open_responses <= 0;
req_start <= 1'b0;
end else begin
noc_req_counter <= nxt_noc_req_counter;
noc_req_packet_size <= nxt_noc_req_packet_size;
noc_req_packet_count <= nxt_noc_req_packet_count;
noc_req_state <= nxt_noc_req_state;
open_responses <= nxt_open_responses;
req_start <= nxt_req_start;
end
end
endmodule // lisnoc_dma_initiator_noc_req
`include "lisnoc_undef.vh"
`include "lisnoc_dma_undef.vh"
// Local Variables:
// verilog-library-directories:("." "../" "../infrastructure")
// verilog-auto-inst-param-value: t
// End:
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This module processes the responses of DMA requests.
*
* (c) 2011-2013 by the author(s)
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*
*/
`include "lisnoc_def.vh"
`include "lisnoc_dma_def.vh"
module lisnoc_dma_initiator_nocresp(/*AUTOARG*/
// Outputs
noc_in_ready, wb_cyc_o, wb_stb_o, wb_we_o, wb_dat_o, wb_adr_o,
wb_cti_o, wb_bte_o, wb_sel_o, ctrl_done_pos, ctrl_done_en,
// Inputs
clk, rst, noc_in_flit, noc_in_valid, wb_ack_i, wb_dat_i
);
//parameters
parameter flit_width = `FLIT_WIDTH;
parameter table_entries = 4;
localparam table_entries_ptrwidth = $clog2(table_entries);
parameter noc_packet_size = 16;
localparam STATE_WIDTH = 2;
localparam STATE_IDLE = 2'b00;
localparam STATE_GET_ADDR = 2'b01;
localparam STATE_DATA = 2'b10;
localparam STATE_GET_SIZE = 2'b11;
input clk, rst;
input [`FLIT_WIDTH-1:0] noc_in_flit;
input noc_in_valid;
output noc_in_ready;
// Wishbone interface for L2R data fetch
input wb_ack_i;
output reg wb_cyc_o, wb_stb_o;
output reg wb_we_o;
input [31:0] wb_dat_i;
output [31:0] wb_dat_o;
output [31:0] wb_adr_o;
output reg [2:0] wb_cti_o;
output reg [1:0] wb_bte_o;
output [3:0] wb_sel_o;
output reg [table_entries_ptrwidth-1:0] ctrl_done_pos;
output reg ctrl_done_en;
// State registers and next state logic
reg [STATE_WIDTH-1:0] state;
reg [STATE_WIDTH-1:0] nxt_state;
reg [31:0] resp_address;
reg [31:0] nxt_resp_address;
reg last_packet_of_response;
reg nxt_last_packet_of_response;
reg [table_entries_ptrwidth-1:0] resp_id;
reg [table_entries_ptrwidth-1:0] nxt_resp_id;
// There is a buffer between the NoC input and the wishbone
// handling by the state machine. Those are the connection signals
// from buffer to wishbone
wire [`FLIT_WIDTH-1:0] buf_flit;
wire buf_valid;
reg buf_ready;
/* lisnoc_packet_buffer AUTO_TEMPLATE(
.in_\(.*\) (noc_in_\1[]),
.out_size (),
.out_\(.*\) (buf_\1[]),
); */
lisnoc_packet_buffer
#(.fifo_depth(noc_packet_size))
u_buf(/*AUTOINST*/
// Outputs
.in_ready (noc_in_ready), // Templated
.out_flit (buf_flit[flit_width-1:0]), // Templated
.out_valid (buf_valid), // Templated
.out_size (), // Templated
// Inputs
.clk (clk),
.rst (rst),
.in_flit (noc_in_flit[flit_width-1:0]), // Templated
.in_valid (noc_in_valid), // Templated
.out_ready (buf_ready)); // Templated
// Is this the last flit of a packet?
wire buf_last_flit;
assign buf_last_flit = (buf_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB]==`FLIT_TYPE_LAST) |
(buf_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB]==`FLIT_TYPE_SINGLE);
assign wb_adr_o = resp_address; //alias
assign wb_dat_o = buf_flit[`FLIT_CONTENT_MSB:`FLIT_CONTENT_LSB];
// We only do word transfers
assign wb_sel_o = 4'hf;
// Next state, wishbone combinatorial signals and counting
always @(*) begin
// Signal defaults
wb_stb_o = 1'b0;
wb_cyc_o = 1'b0;
wb_we_o = 1'b0;
wb_bte_o = 2'b00;
wb_cti_o = 3'b000;
ctrl_done_en = 1'b0;
ctrl_done_pos = 0;
// Default values are old values
nxt_resp_id = resp_id;
nxt_resp_address = resp_address;
nxt_last_packet_of_response = last_packet_of_response;
buf_ready = 1'b0;
case (state)
STATE_IDLE: begin
buf_ready = 1'b1;
if (buf_valid) begin
nxt_resp_id = buf_flit[`PACKET_ID_MSB:`PACKET_ID_LSB];
nxt_last_packet_of_response = buf_flit[`PACKET_RESP_LAST];
if (buf_flit[`PACKET_TYPE_MSB:`PACKET_TYPE_LSB] == `PACKET_TYPE_L2R_RESP) begin
nxt_state = STATE_IDLE;
ctrl_done_en = 1'b1;
ctrl_done_pos = nxt_resp_id;
end else if(buf_flit[`PACKET_TYPE_MSB:`PACKET_TYPE_LSB] == `PACKET_TYPE_R2L_RESP) begin
nxt_state = STATE_GET_SIZE;
end else begin
// now we have a problem...
// must not happen
nxt_state = STATE_IDLE;
end
end else begin // if (buf_valid)
nxt_state = STATE_IDLE;
end
end
STATE_GET_SIZE: begin
buf_ready = 1'b1;
nxt_state = STATE_GET_ADDR;
end
STATE_GET_ADDR: begin
buf_ready = 1'b1;
nxt_resp_address = buf_flit[`FLIT_CONTENT_MSB:`FLIT_CONTENT_LSB];
nxt_state = STATE_DATA;
end
STATE_DATA: begin
if (buf_last_flit) begin
wb_cti_o = 3'b111;
end else begin
wb_cti_o = 3'b010;
end
wb_bte_o = 2'b00;
wb_cyc_o = 1'b1;
wb_stb_o = 1'b1;
wb_we_o = 1'b1;
if (wb_ack_i) begin
nxt_resp_address = resp_address + 4;
buf_ready = 1'b1;
if (buf_last_flit) begin
nxt_state = STATE_IDLE;
if (last_packet_of_response) begin
ctrl_done_en = 1'b1;
ctrl_done_pos = resp_id;
end
end else begin
nxt_state = STATE_DATA;
end
end else begin
buf_ready = 1'b0;
nxt_state = STATE_DATA;
end
end
default: begin
nxt_state = STATE_IDLE;
end
endcase // case (state)
end // always @ (*)
always @(posedge clk) begin
if (rst) begin
state <= STATE_IDLE;
resp_address <= 0;
last_packet_of_response <= 0;
resp_id <= 0;
end else begin
state <= nxt_state;
resp_address <= nxt_resp_address;
last_packet_of_response <= nxt_last_packet_of_response;
resp_id <= nxt_resp_id;
end
end
endmodule // lisnoc_dma_initiator_nocresp
`include "lisnoc_undef.vh"
`include "lisnoc_dma_undef.vh"
// Local Variables:
// verilog-library-directories:("." "../" "../infrastructure")
// verilog-auto-inst-param-value: t
// End:
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* The wishbone master of the initiator.
*
* (c) 2011-2013 by the author(s)
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*
*/
`include "lisnoc_def.vh"
`include "lisnoc_dma_def.vh"
module lisnoc_dma_initiator_wbreq(/*AUTOARG*/
// Outputs
wb_req_cyc_o, wb_req_stb_o, wb_req_we_o, wb_req_dat_o,
wb_req_adr_o, wb_req_cti_o, wb_req_bte_o, wb_req_sel_o,
req_data_valid, req_data,
// Inputs
clk, rst, wb_req_ack_i, wb_req_dat_i, req_start, req_is_l2r,
req_size, req_laddr, req_data_ready
);
input clk, rst;
input wb_req_ack_i;
output reg wb_req_cyc_o, wb_req_stb_o;
output wb_req_we_o;
input [31:0] wb_req_dat_i;
output [31:0] wb_req_dat_o;
output reg [31:0] wb_req_adr_o;
output reg [2:0] wb_req_cti_o;
output [1:0] wb_req_bte_o;
output [3:0] wb_req_sel_o;
input req_start;
input req_is_l2r;
input [`DMA_REQFIELD_SIZE_WIDTH-3:0] req_size;
input [31:0] req_laddr;
output req_data_valid;
output [31:0] req_data;
input req_data_ready;
//
// Wishbone state machine
//
`define WB_REQ_WIDTH 2
`define WB_REQ_IDLE 2'b00
`define WB_REQ_DATA 2'b01
`define WB_REQ_WAIT 2'b10
// State logic
reg [`WB_REQ_WIDTH-1:0] wb_req_state;
reg [`WB_REQ_WIDTH-1:0] nxt_wb_req_state;
// Counter for the state machine for loaded words
reg [`DMA_REQFIELD_SIZE_WIDTH-3:0] wb_req_count;
reg [`DMA_REQFIELD_SIZE_WIDTH-3:0] nxt_wb_req_count;
/*
* The wishbone data fetch and the NoC interface are seperated by a FIFO.
* This FIFO relaxes problems with bursts and their termination and decouples
* the timing of the NoC side and the wishbone side (in terms of termination).
*/
// The intermediate store a FIFO of three elements
//
// There should be no combinatorial path from input to output, so
// that it takes one cycle before the wishbone interface knows
// about back pressure from the NoC. Additionally, the wishbone
// interface needs one extra cycle for burst termination. The data
// should be stored and not discarded. Finally, there is one
// element in the FIFO that is the normal timing decoupling.
reg [31:0] data_fifo [0:2]; // data storage
wire data_fifo_pop; // NoC pops
reg data_fifo_push; // WB pushes
wire [31:0] data_fifo_out; // Current first element
wire [31:0] data_fifo_in; // Push element
// Shift register for current position (4th bit is full mark)
reg [3:0] data_fifo_pos;
wire data_fifo_empty; // FIFO empty
wire data_fifo_ready; // FIFO accepts new elements
// Connect the fifo signals to the ports
assign data_fifo_pop = req_data_ready;
assign req_data_valid = ~data_fifo_empty;
assign req_data = data_fifo_out;
assign data_fifo_empty = data_fifo_pos[0]; // Empty when pushing to first one
assign data_fifo_out = data_fifo[0]; // First element is out
// FIFO is not ready when back-pressure would result in discarded data,
// that is, we need one store element (high-water).
assign data_fifo_ready = ~|data_fifo_pos[3:2];
// FIFO position pointer logic
always @(posedge clk) begin
if (rst) begin
data_fifo_pos <= 4'b001;
end else begin
if (data_fifo_push & ~data_fifo_pop) begin
// push and no pop
data_fifo_pos <= data_fifo_pos << 1;
end else if (~data_fifo_push & data_fifo_pop) begin
// pop and no push
data_fifo_pos <= data_fifo_pos >> 1;
end else begin
// * no push or pop or
// * both push and pop
data_fifo_pos <= data_fifo_pos;
end
end
end
// FIFO data shifting logic
always @(posedge clk) begin : data_fifo_shift
integer i;
// Iterate all fifo elements, starting from lowest
for (i=0;i<3;i=i+1) begin
if (data_fifo_pop) begin
// when popping data..
if (data_fifo_push & data_fifo_pos[i+1])
// .. and we also push this cycle, we need to check
// whether the pointer was on the next one
data_fifo[i] <= data_fifo_in;
else if (i<2)
// .. otherwise shift if not last
data_fifo[i] <= data_fifo[i+1];
else
// the last stays static
data_fifo[i] <= data_fifo[i];
end else if (data_fifo_push & data_fifo_pos[i]) begin
// when pushing only and this is the current write
// position
data_fifo[i] <= data_fifo_in;
end else begin
// else just keep
data_fifo[i] <= data_fifo[i];
end
end
end
//
// Wishbone interface logic
//
// Statically zero (this interface reads)
assign wb_req_dat_o = 32'h0000_0000;
assign wb_req_we_o = 1'b0;
// We only support full (aligned) word transfers
assign wb_req_sel_o = 4'b1111;
// We only need linear bursts
assign wb_req_bte_o = 2'b00;
// The input to the fifo is the data from the bus
assign data_fifo_in = wb_req_dat_i;
// Next state, wishbone combinatorial signals and counting
always @(*) begin
// Signal defaults
nxt_wb_req_count = wb_req_count;
wb_req_stb_o = 1'b0;
wb_req_cyc_o = 1'b0;
data_fifo_push = 1'b0;
wb_req_adr_o = 32'hx;
wb_req_cti_o = 3'b000;
case (wb_req_state)
`WB_REQ_IDLE: begin
// We are idle'ing
// Always reset counter
nxt_wb_req_count = 0;
if (req_start & req_is_l2r)
// start when new request is handled and it is a L2R
// request. Direct transition to data fetching from bus,
// as the FIFO is always empty at this point.
nxt_wb_req_state = `WB_REQ_DATA;
else
// otherwise keep idle'ing
nxt_wb_req_state = `WB_REQ_IDLE;
end
`WB_REQ_DATA: begin
// We get data from the bus
// Signal cycle and strobe. We do bursts, but don't insert
// wait states, so both of them are always equal.
wb_req_stb_o = 1'b1;
wb_req_cyc_o = 1'b1;
// The address is the base address plus the counter
// Counter counts words, not bytes
wb_req_adr_o = req_laddr + (wb_req_count << 2);
if (~data_fifo_ready | (wb_req_count==req_size-1)) begin
// If fifo gets full next cycle, do cycle termination
wb_req_cti_o = 3'b111;
end else begin
// As long as we can also store the _next_ element in
// the fifo, signal we are in an incrementing burst
wb_req_cti_o = 3'b010;
end
if (wb_req_ack_i) begin
// When this request was successfull..
// increment word counter
nxt_wb_req_count = wb_req_count + 1;
// signal push to data fifo
data_fifo_push = 1'b1;
if (wb_req_count==req_size-1)
// This was the last word
nxt_wb_req_state = `WB_REQ_IDLE;
else if (data_fifo_ready)
// when FIFO can still get data, we stay here
nxt_wb_req_state = `WB_REQ_DATA;
else
// .. otherwise we wait for FIFO to become ready
nxt_wb_req_state = `WB_REQ_WAIT;
end else begin // if (wb_req_ack_i)
// ..otherwise we still wait for the acknowledgement
nxt_wb_req_state = `WB_REQ_DATA;
end
end
`WB_REQ_WAIT: begin
// Waiting for FIFO to accept new data
if (data_fifo_ready)
// FIFO ready, restart burst
nxt_wb_req_state = `WB_REQ_DATA;
else
// wait
nxt_wb_req_state = `WB_REQ_WAIT;
end
default: begin
nxt_wb_req_state = `WB_REQ_IDLE;
end
endcase
end
// Sequential part of the state machine
always @(posedge clk) begin
if (rst) begin
wb_req_state <= `WB_REQ_IDLE;
wb_req_count <= 0;
end else begin
wb_req_state <= nxt_wb_req_state;
wb_req_count <= nxt_wb_req_count;
end
end
endmodule // lisnoc_dma_initiator_wbreq
`include "lisnoc_dma_undef.vh"
// Local Variables:
// verilog-library-directories:("../" "../infrastructure")
// verilog-auto-inst-param-value: t
// End:
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* DMA transfer table
* The DMA transfer table holds all requests and their corresponding
* life-cycle between the interface and the control handler. To save
* ports on the memory, each the request and status are dual ported,
* so that the interface can't read back the values. The only
* exception is the valid signal, that is a dedicated register for
* each request. All request valid signals are also provided in an
* output.
*
* (c) 2011-2013 by the author(s)
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*
*/
`include "lisnoc_dma_def.vh"
module lisnoc_dma_request_table(/*AUTOARG*/
// Outputs
ctrl_read_req, valid, done, irq,
// Inputs
clk, rst, if_write_req, if_write_pos, if_write_select, if_write_en,
if_valid_pos, if_valid_set, if_valid_en, if_validrd_en,
ctrl_read_pos, ctrl_done_pos, ctrl_done_en
);
parameter table_entries = 4;
localparam table_entries_ptrwidth = $clog2(table_entries);
parameter generate_interrupt = 1;
input clk, rst;
// Interface write (request) interface
input [`DMA_REQUEST_WIDTH-1:0] if_write_req;
input [table_entries_ptrwidth-1:0] if_write_pos;
input [`DMA_REQMASK_WIDTH-1:0] if_write_select;
input if_write_en;
input [table_entries_ptrwidth-1:0] if_valid_pos;
input if_valid_set;
input if_valid_en;
input if_validrd_en;
// Control read (request) interface
output [`DMA_REQUEST_WIDTH-1:0] ctrl_read_req;
input [table_entries_ptrwidth-1:0] ctrl_read_pos;
// Control write (status) interface
input [table_entries_ptrwidth-1:0] ctrl_done_pos;
input ctrl_done_en;
// All valid bits of the entries
output [table_entries-1:0] valid;
output [table_entries-1:0] done;
output [table_entries-1:0] irq;
// The storage of the requests ..
reg [`DMA_REQUEST_WIDTH-1:0] transfer_request_table[0:table_entries-1];
reg [table_entries-1:0] transfer_valid;
reg [table_entries-1:0] transfer_done;
wire [`DMA_REQUEST_WIDTH-1:0] if_write_mask;
assign if_write_mask[`DMA_REQFIELD_LADDR_MSB:`DMA_REQFIELD_LADDR_LSB] = {`DMA_REQFIELD_LADDR_WIDTH{if_write_select[`DMA_REQMASK_LADDR]}};
assign if_write_mask[`DMA_REQFIELD_SIZE_MSB:`DMA_REQFIELD_SIZE_LSB] = {`DMA_REQFIELD_SIZE_WIDTH{if_write_select[`DMA_REQMASK_SIZE]}};
assign if_write_mask[`DMA_REQFIELD_RTILE_MSB:`DMA_REQFIELD_RTILE_LSB] = {`DMA_REQFIELD_RTILE_WIDTH{if_write_select[`DMA_REQMASK_RTILE]}};
assign if_write_mask[`DMA_REQFIELD_RADDR_MSB:`DMA_REQFIELD_RADDR_LSB] = {`DMA_REQFIELD_RADDR_WIDTH{if_write_select[`DMA_REQMASK_RADDR]}};
assign if_write_mask[`DMA_REQFIELD_DIR] = if_write_select[`DMA_REQMASK_DIR];
// Write to the request table
always @(posedge clk) begin : proc_request_table
integer i;
if (rst) begin : reset
//reset
for (i = 0; i < table_entries; i = i+1) begin
{ transfer_valid[i], transfer_done[i] } <= 2'b00;
end //for
end else begin
if (if_write_en) begin
transfer_request_table[if_write_pos] <= (~if_write_mask & transfer_request_table[if_write_pos]) | (if_write_mask & if_write_req);
end
for (i = 0; i<table_entries; i=i+1 ) begin
if (if_valid_en && (if_valid_pos == i)) begin
// Start transfer
transfer_valid[i] <= if_valid_set;
transfer_done[i] <= 1'b0;
end else if (if_validrd_en && (if_valid_pos==i) && (transfer_done[i])) begin
// Check transfer and was done
transfer_done[i] <= 1'b0;
transfer_valid[i] <= 1'b0;
end else if (ctrl_done_en && (ctrl_done_pos==i)) begin
// Transfer is finished
transfer_done[i] <= 1'b1;
end
end
end
end
// Read interface to the request table
assign ctrl_read_req = transfer_request_table[ctrl_read_pos];
// Combine the valid and done bits to one signal
genvar i;
generate
for (i=0;i<table_entries;i=i+1) begin
assign valid[i] = transfer_valid[i] & ~transfer_done[i];
assign done[i] = transfer_done[i];
end
endgenerate
// The interrupt is set when any request is valid and done
assign irq = (transfer_valid & transfer_done) & {(table_entries){1'b1}};
endmodule // dma_transfer_table
// Local Variables:
// verilog-typedef-regexp:"_t$"
// End:
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* The module behaving as target in DMA transfers.
*
* (c) 2011-2013 by the author(s)
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*
*/
`include "lisnoc_def.vh"
`include "lisnoc_dma_def.vh"
module lisnoc_dma_target (/*AUTOARG*/
// Outputs
noc_out_flit, noc_out_valid, noc_in_ready, wb_cyc_o, wb_stb_o,
wb_we_o, wb_dat_o, wb_adr_o, wb_sel_o, wb_cti_o, wb_bte_o,
// Inputs
clk, rst, noc_out_ready, noc_in_flit, noc_in_valid, wb_ack_i,
wb_dat_i
);
parameter flit_width = `FLIT_WIDTH;
localparam STATE_WIDTH = 4;
localparam STATE_IDLE = 4'b0000;
localparam STATE_L2R_GETADDR = 4'b0001;
localparam STATE_L2R_DATA = 4'b0010;
localparam STATE_L2R_SENDRESP = 4'b0011;
localparam STATE_R2L_GETLADDR = 4'b0100;
localparam STATE_R2L_GETRADDR = 4'b0101;
localparam STATE_R2L_GENHDR = 4'b0110;
localparam STATE_R2L_GENADDR = 4'b0111;
localparam STATE_R2L_DATA = 4'b1000;
//TODO: set nxt_wb_waiting = 1'b0 in certain states like idle, or genheader.
// Not important since we just loose one cycle in the worst case
parameter table_entries = 4;
localparam table_entries_ptrwidth = $clog2(table_entries);
parameter tileid = 0;
parameter noc_packet_size = 16;
input clk;
input rst;
// NOC-Interface
output reg [`FLIT_WIDTH-1:0] noc_out_flit;
output reg noc_out_valid;
input noc_out_ready;
input [`FLIT_WIDTH-1:0] noc_in_flit;
input noc_in_valid;
output noc_in_ready;
// Wishbone interface for L2R data store
input wb_ack_i;
output reg wb_cyc_o, wb_stb_o, wb_we_o;
input [31:0] wb_dat_i;
output [31:0] wb_dat_o;
output [31:0] wb_adr_o;
output [3:0] wb_sel_o;
output reg [2:0] wb_cti_o;
output reg [1:0] wb_bte_o;
// There is a buffer between the NoC input and the wishbone
// handling by the state machine. Those are the connection signals
// from buffer to wishbone
wire [`FLIT_WIDTH-1:0] buf_flit;
wire buf_valid;
reg buf_ready;
/*
* One FSM that handles the flow from the input
* buffer to the wishbone interface
*/
// FSM state
reg [STATE_WIDTH-1:0] state;
reg [STATE_WIDTH-1:0] nxt_state;
//FSM hidden state
reg wb_waiting;
reg nxt_wb_waiting;
// Store request parameters: address, last packet and source
reg [31:0] src_address;
reg [31:0] nxt_src_address;
reg [31:0] address;
reg [31:0] nxt_address;
reg end_of_request;
reg nxt_end_of_request;
reg [`SOURCE_WIDTH-1:0] src_tile;
reg [`SOURCE_WIDTH-1:0] nxt_src_tile;
reg [`PACKET_ID_WIDTH-1:0] packet_id;
reg [`PACKET_ID_WIDTH-1:0] nxt_packet_id;
// Counter for flits/words in request
reg [`SIZE_WIDTH-1:0] noc_resp_wcounter;
reg [`SIZE_WIDTH-1:0] nxt_noc_resp_wcounter;
// Current packet flit/word counter
reg [4:0] noc_resp_packet_wcount;
reg [4:0] nxt_noc_resp_packet_wcount;
// Current packet total number of flits/words
reg [4:0] noc_resp_packet_wsize;
reg [4:0] nxt_noc_resp_packet_wsize;
// TODO: correct define!
reg [`DMA_REQFIELD_SIZE_WIDTH-3:0] resp_wsize;
reg [`DMA_REQFIELD_SIZE_WIDTH-3:0] nxt_resp_wsize;
reg [`DMA_RESPFIELD_SIZE_WIDTH-3:0] wb_resp_count;
reg [`DMA_RESPFIELD_SIZE_WIDTH-3:0] nxt_wb_resp_count;
//FIFO-Stuff
wire data_fifo_valid;
reg [31:0] data_fifo [0:2]; // data storage
reg data_fifo_pop; // NOC pushes
reg data_fifo_push; // WB pops
wire [31:0] data_fifo_out; // Current first element
wire [31:0] data_fifo_in; // Push element
// Shift register for current position (4th bit is full mark)
reg [3:0] data_fifo_pos;
wire data_fifo_empty; // FIFO empty
wire data_fifo_ready; // FIFO accepts new elements
//
// Input buffer that stores flits until we have one complete packet
//
/* lisnoc_packet_buffer AUTO_TEMPLATE(
.in_\(.*\) (noc_in_\1[]),
.out_size (),
.out_\(.*\) (buf_\1[]),
); */
lisnoc_packet_buffer
#(.fifo_depth(noc_packet_size))
u_buf(/*AUTOINST*/
// Outputs
.in_ready (noc_in_ready), // Templated
.out_flit (buf_flit[flit_width-1:0]), // Templated
.out_valid (buf_valid), // Templated
.out_size (), // Templated
// Inputs
.clk (clk),
.rst (rst),
.in_flit (noc_in_flit[flit_width-1:0]), // Templated
.in_valid (noc_in_valid), // Templated
.out_ready (buf_ready)); // Templated
// Is this the last flit of a packet?
wire buf_last_flit;
assign buf_last_flit = (buf_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB]==`FLIT_TYPE_LAST) |
(buf_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB]==`FLIT_TYPE_SINGLE);
// The intermediate store a FIFO of three elements
//
// There should be no combinatorial path from input to output, so
// that it takes one cycle before the wishbone interface knows
// about back pressure from the NoC. Additionally, the wishbone
// interface needs one extra cycle for burst termination. The data
// should be stored and not discarded. Finally, there is one
// element in the FIFO that is the normal timing decoupling.
// Connect the fifo signals to the ports
// assign data_fifo_pop = resp_data_ready;
assign data_fifo_valid = ~data_fifo_empty;
assign data_fifo_empty = data_fifo_pos[0]; // Empty when pushing to first one
assign data_fifo_ready = ~|data_fifo_pos[3:2]; //equal to not full
assign data_fifo_in = wb_dat_i;
assign data_fifo_out = data_fifo[0]; // First element is out
// FIFO position pointer logic
always @(posedge clk) begin
if (rst) begin
data_fifo_pos <= 4'b001;
end else begin
if (data_fifo_push & ~data_fifo_pop) begin
// push and no pop
data_fifo_pos <= data_fifo_pos << 1;
end else if (~data_fifo_push & data_fifo_pop) begin
// pop and no push
data_fifo_pos <= data_fifo_pos >> 1;
end else begin
// * no push or pop or
// * both push and pop
data_fifo_pos <= data_fifo_pos;
end
end
end
// FIFO data shifting logic
always @(posedge clk) begin : data_fifo_shift
integer i;
// Iterate all fifo elements, starting from lowest
for (i=0;i<3;i=i+1) begin
if (data_fifo_pop) begin
// when popping data..
if (data_fifo_push & data_fifo_pos[i+1])
// .. and we also push this cycle, we need to check
// whether the pointer was on the next one
data_fifo[i] <= data_fifo_in;
else if (i<2)
// .. otherwise shift if not last
data_fifo[i] <= data_fifo[i+1];
else
// the last stays static
data_fifo[i] <= data_fifo[i];
end else if (data_fifo_push & data_fifo_pos[i]) begin
// when pushing only and this is the current write
// position
data_fifo[i] <= data_fifo_in;
end else begin
// else just keep
data_fifo[i] <= data_fifo[i];
end
end
end
// Wishbone signal generation
// We only do word transfers
assign wb_sel_o = 4'hf;
// The data of the payload flits
assign wb_dat_o = buf_flit[`FLIT_CONTENT_MSB:`FLIT_CONTENT_LSB];
// Assign stored (and incremented) address to wishbone interface
assign wb_adr_o = address;
//FSM
// Next state, counting, control signals
always @(*) begin
// Default values are old values
nxt_address = address;
nxt_resp_wsize = resp_wsize;
nxt_end_of_request = end_of_request;
nxt_src_address = src_address;
nxt_src_tile = src_tile;
nxt_end_of_request = end_of_request;
nxt_packet_id = packet_id;
nxt_wb_resp_count = wb_resp_count;
nxt_noc_resp_packet_wcount = noc_resp_packet_wcount;
nxt_noc_resp_packet_wsize = noc_resp_packet_wsize;
nxt_wb_waiting = wb_waiting;
nxt_noc_resp_wcounter = noc_resp_wcounter;
// Default control signals
wb_cyc_o = 1'b0;
wb_stb_o = 1'b0;
wb_we_o = 1'b0;
wb_bte_o = 2'b00;
wb_cti_o = 3'b000;
noc_out_valid = 1'b0;
noc_out_flit = 34'h0;
data_fifo_push = 1'b0;
data_fifo_pop = 1'b0;
buf_ready = 1'b0;
case (state)
STATE_IDLE: begin
buf_ready= 1'b1;
nxt_end_of_request = buf_flit[`PACKET_REQ_LAST];
nxt_src_tile = buf_flit[`SOURCE_MSB:`SOURCE_LSB];
nxt_resp_wsize = buf_flit[`SIZE_MSB:`SIZE_LSB];
nxt_packet_id = buf_flit[`PACKET_ID_MSB:`PACKET_ID_LSB];
nxt_noc_resp_wcounter = 0;
nxt_wb_resp_count = 1;
if (buf_valid) begin
if (buf_flit[`PACKET_TYPE_MSB:`PACKET_TYPE_LSB] == `PACKET_TYPE_L2R_REQ) begin
nxt_state = STATE_L2R_GETADDR;
end else if(buf_flit[`PACKET_TYPE_MSB:`PACKET_TYPE_LSB] == `PACKET_TYPE_R2L_REQ) begin
nxt_state = STATE_R2L_GETLADDR;
end else begin
// now we have a problem...
// must not happen
nxt_state = STATE_IDLE;
end
end else begin
nxt_state = STATE_IDLE;
end
end // case: STATE_IDLE
//L2R-handling
STATE_L2R_GETADDR: begin
buf_ready = 1'b1;
nxt_address = buf_flit[`FLIT_CONTENT_MSB:`FLIT_CONTENT_LSB];
if (buf_valid) begin
nxt_state = STATE_L2R_DATA;
end else begin
nxt_state = STATE_L2R_GETADDR;
end
end
STATE_L2R_DATA: begin
if (buf_last_flit)
wb_cti_o = 3'b111;
else
wb_cti_o = 3'b010;
wb_cyc_o = 1'b1;
wb_stb_o = 1'b1;
wb_we_o = 1'b1;
if (wb_ack_i) begin
nxt_address = address + 4;
buf_ready = 1'b1;
if (buf_last_flit) begin
if (end_of_request) begin
nxt_state = STATE_L2R_SENDRESP;
end else begin
nxt_state = STATE_IDLE;
end
end else begin
nxt_state = STATE_L2R_DATA;
end
end else begin
buf_ready = 1'b0;
nxt_state = STATE_L2R_DATA;
end
end // case: STATE_L2R_DATA
STATE_L2R_SENDRESP: begin
noc_out_valid = 1'b1;
noc_out_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB] = `FLIT_TYPE_SINGLE;
noc_out_flit[`FLIT_DEST_MSB:`FLIT_DEST_LSB] = src_tile;
noc_out_flit[`PACKET_CLASS_MSB:`PACKET_CLASS_LSB] = `PACKET_CLASS_DMA;
noc_out_flit[`PACKET_ID_MSB:`PACKET_ID_LSB] = packet_id;
noc_out_flit[`PACKET_TYPE_MSB:`PACKET_TYPE_LSB] = `PACKET_TYPE_L2R_RESP;
if (noc_out_ready) begin
nxt_state = STATE_IDLE;
end else begin
nxt_state = STATE_L2R_SENDRESP;
end
end // case: STATE_L2R_SENDRESP
//R2L handling
STATE_R2L_GETLADDR: begin
buf_ready = 1'b1;
nxt_address = buf_flit[`FLIT_CONTENT_MSB:`FLIT_CONTENT_LSB];
if (buf_valid) begin
nxt_state = STATE_R2L_GETRADDR;
end else begin
nxt_state = STATE_R2L_GETLADDR;
end
end
STATE_R2L_GETRADDR: begin
buf_ready = 1'b1;
nxt_src_address = buf_flit[`FLIT_CONTENT_MSB:`FLIT_CONTENT_LSB];
if (buf_valid) begin
nxt_state = STATE_R2L_GENHDR;
end else begin
nxt_state = STATE_R2L_GETRADDR;
end
end
STATE_R2L_GENHDR: begin
noc_out_valid = 1'b1;
noc_out_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB] = `FLIT_TYPE_HEADER;
noc_out_flit[`FLIT_DEST_MSB:`FLIT_DEST_LSB] = src_tile;
noc_out_flit[`PACKET_CLASS_MSB:`PACKET_CLASS_LSB] = `PACKET_CLASS_DMA;
noc_out_flit[`PACKET_ID_MSB:`PACKET_ID_LSB] = packet_id;
noc_out_flit[`SOURCE_MSB:`SOURCE_LSB] = tileid;
noc_out_flit[`PACKET_TYPE_MSB:`PACKET_TYPE_LSB] = `PACKET_TYPE_R2L_RESP;
if ((noc_resp_wcounter + (noc_packet_size -2)) < resp_wsize) begin
// This is not the last packet in the respuest ((noc_packet_size -2) words*4 bytes=120)
// Only (noc_packet_size -2) flits are availabel for the payload,
// because we need a header-flit and an address-flit, too.
noc_out_flit[`SIZE_MSB:`SIZE_LSB] = 7'd120;
noc_out_flit[`PACKET_RESP_LAST] = 1'b0;
nxt_noc_resp_packet_wsize = noc_packet_size -2;
// count is the current transfer number
nxt_noc_resp_packet_wcount = 5'd1;
end else begin
// This is the last packet in the respuest
noc_out_flit[`SIZE_MSB:`SIZE_LSB] = resp_wsize - noc_resp_wcounter;
noc_out_flit[`PACKET_RESP_LAST] = 1'b1;
nxt_noc_resp_packet_wsize = resp_wsize - noc_resp_wcounter;
// count is the current transfer number
nxt_noc_resp_packet_wcount = 5'd1;
end // else: !if((noc_resp_wcounter + (noc_packet_size -2)) < resp_wsize)
// change to next state if successful
if (noc_out_ready)
nxt_state = STATE_R2L_GENADDR;
else
nxt_state = STATE_R2L_GENHDR;
end // case: STATE_R2L_GENHDR
STATE_R2L_GENADDR: begin
noc_out_valid = 1'b1;
noc_out_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB] = `FLIT_TYPE_PAYLOAD;
noc_out_flit[`FLIT_CONTENT_MSB:`FLIT_CONTENT_LSB] = src_address + (noc_resp_wcounter << 2);
if (noc_out_ready) begin
nxt_state = STATE_R2L_DATA;
end else begin
nxt_state = STATE_R2L_GENADDR;
end
end // case: `NOC_RESP_R2L_GENADDR
STATE_R2L_DATA: begin
// NOC-handling
// transfer data to noc if available
noc_out_valid = data_fifo_valid;
noc_out_flit[`FLIT_CONTENT_MSB:`FLIT_CONTENT_LSB] = data_fifo_out;
//TODO: Rearange ifs
if (noc_resp_packet_wcount==noc_resp_packet_wsize) begin
noc_out_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB] = `FLIT_TYPE_LAST;
if (noc_out_valid & noc_out_ready) begin
data_fifo_pop = 1'b1;
if ((noc_resp_wcounter + (noc_packet_size -2)) < resp_wsize) begin
// Only (noc_packet_size -2) flits are availabel for the payload,
// because we need a header-flit and an address-flit, too.
//this was not the last packet of the response
nxt_state = STATE_R2L_GENHDR;
nxt_noc_resp_wcounter = noc_resp_wcounter + noc_resp_packet_wcount;
end else begin
//this is the last packet of the response
nxt_state = STATE_IDLE;
end
end else begin
nxt_state = STATE_R2L_DATA;
end
end else begin //not LAST
noc_out_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB] = `FLIT_TYPE_PAYLOAD;
if (noc_out_valid & noc_out_ready) begin
data_fifo_pop = 1'b1;
nxt_noc_resp_packet_wcount = noc_resp_packet_wcount + 1;
end
nxt_state = STATE_R2L_DATA;
end
//FIFO-handling
if (wb_waiting) begin //hidden state
//don't get data from the bus
wb_stb_o = 1'b0;
wb_cyc_o = 1'b0;
data_fifo_push = 1'b0;
if (data_fifo_ready) begin
nxt_wb_waiting = 1'b0;
end else begin
nxt_wb_waiting = 1'b1;
end
end else begin //not wb_waiting
// Signal cycle and strobe. We do bursts, but don't insert
// wait states, so both of them are always equal.
if ((noc_resp_packet_wcount==noc_resp_packet_wsize) & noc_out_valid & noc_out_ready) begin
wb_stb_o = 1'b0;
wb_cyc_o = 1'b0;
end else begin
wb_stb_o = 1'b1;
wb_cyc_o = 1'b1;
end
// TODO: why not generate address from the base address + counter<<2?
if (~data_fifo_ready | (wb_resp_count==resp_wsize)) begin
wb_cti_o = 3'b111;
end else begin
wb_cti_o = 3'b111;
end
if (wb_ack_i) begin
// When this was successfull..
if (~data_fifo_ready | (wb_resp_count==resp_wsize)) begin
nxt_wb_waiting = 1'b1;
end else begin
nxt_wb_waiting = 1'b0;
end
nxt_wb_resp_count = wb_resp_count + 1;
nxt_address = address + 4;
data_fifo_push = 1'b1;
end else begin
// ..otherwise we still wait for the acknowledgement
nxt_wb_resp_count = wb_resp_count;
nxt_address = address;
data_fifo_push = 1'b0;
nxt_wb_waiting = 1'b0;
end
end // else: !if(wb_waiting)
end // case: STATE_R2L_DATA
default: begin
nxt_state = STATE_IDLE;
end
endcase // case (state)
end
always @(posedge clk) begin
if (rst) begin
state <= STATE_IDLE;
address <= 32'h0;
end_of_request <= 1'b0;
src_tile <= 0;
resp_wsize <= 0;
packet_id <= 0;
src_address <= 0;
noc_resp_wcounter <= 0;
noc_resp_packet_wsize <= 5'h0;
noc_resp_packet_wcount <= 5'h0;
noc_resp_packet_wcount <= 0;
wb_resp_count <= 0;
wb_waiting <= 0;
end else begin
state <= nxt_state;
address <= nxt_address;
end_of_request <= nxt_end_of_request;
src_tile <= nxt_src_tile;
resp_wsize <= nxt_resp_wsize;
packet_id <= nxt_packet_id;
src_address <= nxt_src_address;
noc_resp_wcounter <= nxt_noc_resp_wcounter;
noc_resp_packet_wsize <= nxt_noc_resp_packet_wsize;
noc_resp_packet_wcount <= nxt_noc_resp_packet_wcount;
wb_resp_count <= nxt_wb_resp_count;
wb_waiting <= nxt_wb_waiting;
end
end
endmodule // lisnoc_dma_target
// Local Variables:
// verilog-library-directories:("../infrastructure")
// verilog-auto-inst-param-value: t
// End:
|
`include "lisnoc_def.vh"
`undef FLIT_WIDTH
`undef FLIT_TYPE_MSB
`undef FLIT_TYPE_WIDTH
`undef FLIT_TYPE_LSB
`undef FLIT_CONTENT_WIDTH
`undef FLIT_CONTENT_MSB
`undef FLIT_CONTENT_LSB
`undef FLIT_DEST_WIDTH
`undef FLIT_DEST_MSB
`undef FLIT_DEST_LSB
`undef PACKET_CLASS_MSB
`undef PACKET_CLASS_WIDTH
`undef PACKET_CLASS_LSB
`undef PACKET_CLASS_DMA
// source address field of header flit
`undef SOURCE_MSB
`undef SOURCE_WIDTH
`undef SOURCE_LSB
// packet id field of header flit
`undef PACKET_ID_MSB
`undef PACKET_ID_WIDTH
`undef PACKET_ID_LSB
`undef PACKET_TYPE_MSB
`undef PACKET_TYPE_WIDTH
`undef PACKET_TYPE_LSB
`undef PACKET_TYPE_L2R_REQ
`undef PACKET_TYPE_R2L_REQ
`undef PACKET_TYPE_L2R_RESP
`undef PACKET_TYPE_R2L_RESP
`undef PACKET_REQ_LAST
`undef PACKET_RESP_LAST
`undef SIZE_MSB
`undef SIZE_WIDTH
`undef SIZE_LSB
`undef DMA_REQUEST_WIDTH
`undef DMA_REQFIELD_LADDR_WIDTH
`undef DMA_REQFIELD_SIZE_WIDTH
`undef DMA_REQFIELD_RTILE_WIDTH
`undef DMA_REQFIELD_RADDR_WIDTH
`undef DMA_REQFIELD_LADDR_MSB
`undef DMA_REQFIELD_LADDR_LSB
`undef DMA_REQFIELD_SIZE_MSB
`undef DMA_REQFIELD_SIZE_LSB
`undef DMA_REQFIELD_RTILE_MSB
`undef DMA_REQFIELD_RTILE_LSB
`undef DMA_REQFIELD_RADDR_MSB
`undef DMA_REQFIELD_RADDR_LSB
`undef DMA_REQFIELD_DIR
`undef DMA_REQUEST_INVALID
`undef DMA_REQUEST_VALID
`undef DMA_REQMASK_WIDTH
`undef DMA_REQMASK_LADDR
`undef DMA_REQMASK_SIZE
`undef DMA_REQMASK_RTILE
`undef DMA_REQMASK_RADDR
`undef DMA_REQMASK_DIR
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* The wishbone slave interface to configure the DMA module.
*
* (c) 2011-2013 by the author(s)
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*
*/
`include "lisnoc_dma_def.vh"
module lisnoc_dma_wbinterface(/*AUTOARG*/
// Outputs
wb_if_dat_o, wb_if_ack_o, if_write_req, if_write_pos,
if_write_select, if_write_en, if_valid_pos, if_valid_set,
if_valid_en, if_validrd_en,
// Inputs
clk, rst, wb_if_adr_i, wb_if_dat_i, wb_if_cyc_i, wb_if_stb_i,
wb_if_we_i, done
);
parameter table_entries = 4;
// localparam table_entries_ptrwidth = $clog2(table_entries);
localparam table_entries_ptrwidth = 2;
parameter tileid = 0; // TODO: remove
input clk,rst;
input [31:0] wb_if_adr_i;
input [31:0] wb_if_dat_i;
input wb_if_cyc_i;
input wb_if_stb_i;
input wb_if_we_i;
output reg [31:0] wb_if_dat_o;
output wb_if_ack_o;
output [`DMA_REQUEST_WIDTH-1:0] if_write_req;
output [table_entries_ptrwidth-1:0] if_write_pos;
output [`DMA_REQMASK_WIDTH-1:0] if_write_select;
output if_write_en;
// Interface read (status) interface
output [table_entries_ptrwidth-1:0] if_valid_pos;
output if_valid_set;
output if_valid_en;
output if_validrd_en;
input [table_entries-1:0] done;
assign if_write_req = { wb_if_dat_i[`DMA_REQFIELD_LADDR_WIDTH-1:0],
wb_if_dat_i[`DMA_REQFIELD_SIZE_WIDTH-1:0],
wb_if_dat_i[`DMA_REQFIELD_RTILE_WIDTH-1:0],
wb_if_dat_i[`DMA_REQFIELD_RADDR_WIDTH-1:0],
wb_if_dat_i[0] };
assign if_write_pos = wb_if_adr_i[table_entries_ptrwidth+4:5]; // ptrwidth MUST be <= 7 (=128 entries)
assign if_write_en = wb_if_cyc_i & wb_if_stb_i & wb_if_we_i;
assign if_valid_pos = wb_if_adr_i[table_entries_ptrwidth+4:5]; // ptrwidth MUST be <= 7 (=128 entries)
assign if_valid_en = wb_if_cyc_i & wb_if_stb_i & (wb_if_adr_i[4:0] == 5'h14) & wb_if_we_i;
assign if_validrd_en = wb_if_cyc_i & wb_if_stb_i & (wb_if_adr_i[4:0] == 5'h14) & ~wb_if_we_i;
assign if_valid_set = wb_if_we_i | (~wb_if_we_i & ~done[if_valid_pos]);
assign wb_if_ack_o = wb_if_cyc_i & wb_if_stb_i;
always @(*) begin
if (wb_if_adr_i[4:0] == 5'h14) begin
wb_if_dat_o = {31'h0,done[if_valid_pos]};
end else begin
wb_if_dat_o = 32'h0;
end
end
genvar i;
// This assumes, that mask and address match
generate
for (i=0;i<`DMA_REQMASK_WIDTH;i=i+1) begin
assign if_write_select[i] = (wb_if_adr_i[4:2] == i);
end
endgenerate
endmodule // lisnoc_dma_wbinterface
`include "lisnoc_dma_undef.vh"
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* The packet buffer is similar to a FIFO but does only signal a flit
* at the output when a complete packet is in the buffer. This relaxes
* backpressure problems that may arise.
*
* (c) 2011-2013 by the author(s)
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*
*/
`include "lisnoc_def.vh"
module lisnoc_packet_buffer(/*AUTOARG*/
// Outputs
in_ready, out_flit, out_valid, out_size,
// Inputs
clk, rst, in_flit, in_valid, out_ready
);
parameter data_width = 32;
localparam flit_width = data_width+2;
parameter fifo_depth = 16;
localparam size_width = $clog2(fifo_depth+1);
localparam READY = 1'b0, BUSY = 1'b1;
//inputs
input clk, rst;
input [flit_width-1:0] in_flit;
input in_valid;
output in_ready;
output [flit_width-1:0] out_flit;
output out_valid;
input out_ready;
output reg [size_width-1:0] out_size;
// Signals for fifo
reg [flit_width-1:0] fifo_data [0:fifo_depth]; //actual fifo
reg [fifo_depth:0] fifo_write_ptr;
reg [fifo_depth:0] last_flits;
wire full_packet;
wire pop;
wire push;
wire [1:0] in_flit_type;
assign in_flit_type = in_flit[flit_width-1:flit_width-2];
wire in_is_last;
assign in_is_last = (in_flit_type == `FLIT_TYPE_LAST) || (in_flit_type == `FLIT_TYPE_SINGLE);
reg [fifo_depth-1:0] valid_flits;
always @(*) begin : valid_flits_comb
integer i;
// Set first element
valid_flits[fifo_depth-1] = fifo_write_ptr[fifo_depth];
for (i=fifo_depth-2;i>=0;i=i-1) begin
valid_flits[i] = fifo_write_ptr[i+1] | valid_flits[i+1];
end
end
assign full_packet = |(last_flits[fifo_depth-1:0] & valid_flits);
assign pop = out_valid & out_ready;
assign push = in_valid & in_ready;
assign out_flit = fifo_data[0];
assign out_valid = full_packet;
assign in_ready = !fifo_write_ptr[fifo_depth];
always @(*) begin : findfirstlast
reg [size_width-1:0] i;
reg [size_width-1:0] s;
reg found;
s = 0;
found = 0;
for (i=0;i<fifo_depth;i=i+1) begin
if (last_flits[i] && !found) begin
s = i+1;
found = 1;
end
end
out_size = s;
end
always @(posedge clk) begin
if (rst) begin
fifo_write_ptr <= {{fifo_depth{1'b0}},1'b1};
end else if (push & !pop) begin
fifo_write_ptr <= fifo_write_ptr << 1;
end else if (!push & pop) begin
fifo_write_ptr <= fifo_write_ptr >> 1;
end
end
always @(posedge clk) begin : shift_register
if (rst) begin
last_flits <= {fifo_depth+1{1'b0}};
end else begin : shift
integer i;
for (i=0;i<fifo_depth-1;i=i+1) begin
if (pop) begin
if (push & fifo_write_ptr[i+1]) begin
fifo_data[i] <= in_flit;
last_flits[i] <= in_is_last;
end else begin
fifo_data[i] <= fifo_data[i+1];
last_flits[i] <= last_flits[i+1];
end
end else if (push & fifo_write_ptr[i]) begin
fifo_data[i] <= in_flit;
last_flits[i] <= in_is_last;
end
end // for (i=0;i<fifo_depth-1;i=i+1)
// Handle last element
if (pop & push & fifo_write_ptr[i+1]) begin
fifo_data[i] <= in_flit;
last_flits[i] <= in_is_last;
end else if (push & fifo_write_ptr[i]) begin
fifo_data[i] <= in_flit;
last_flits[i] <= in_is_last;
end
end
end // block: shift_register
endmodule
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This file should be included at the end of every file that
* includes lisnoc_def.vh. It avoids any conflicts with your system.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
* Andreas Lankes <[email protected]>
* Michael Tempelmeier <[email protected]>
*/
`undef FLIT_TYPE_PAYLOAD
`undef FLIT_TYPE_HEADER
`undef FLIT_TYPE_LAST
`undef FLIT_TYPE_SINGLE
`undef SELECT_NORTH
`undef SELECT_EAST
`undef SELECT_SOUTH
`undef SELECT_WEST
`undef SELECT_LOCAL
`undef NORTH
`undef EAST
`undef SOUTH
`undef WEST
`undef LOCAL
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is a deserializer for virtual channels
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
* Alexandra Weber <[email protected]>
*/
// TODO: Make more flexible by lookup vector class->vc
module lisnoc_vc_deserializer(
//output
flit_o, valid_o, ready_for_input,
//input
flit_i, valid_i, ready_for_output,
clk, rst
);
parameter flit_data_width = 32;
parameter flit_type_width = 2;
localparam flit_width = flit_data_width + flit_type_width;
parameter FLIT_TYPE_HEADER = 2'b01;
parameter FLIT_TYPE_PAYLOAD = 2'b00;
parameter FLIT_TYPE_LAST = 2'b10;
parameter FLIT_TYPE_SINGLE = 2'b11;
// every vchannel gets the packets of one class
parameter class_msb = 21;
parameter class_lsb = 20;
parameter class_width = 2;
// number of output vchannels
parameter vchannels = 2;
input clk;
input rst;
// array of readys from the vchannels
input [vchannels-1:0] ready_for_output;
// not-full signal from the fifo
output reg ready_for_input;
// one vchannel in (serialized)
input [flit_width-1:0] flit_i;
input valid_i;
// n-vchannel out (multiple vchannels)
output reg [flit_width-1:0] flit_o;
output reg [vchannels-1:0] valid_o;
reg [flit_width-1:0] nxt_flit_o;
reg [vchannels-1:0] nxt_valid_o;
reg [class_width-1:0] req_vchannel;
reg [class_width-1:0] nxt_req_vchannel;
reg state;
reg nxt_state;
always @ (*) begin: fsm
localparam WAITING = 1'b0;
localparam SENDING = 1'b1;
case (state)
WAITING: begin
nxt_flit_o = 'hx;
nxt_valid_o = {vchannels{1'b0}};
ready_for_input = 1'b0;
if(flit_i[flit_width-1:flit_width-2] == FLIT_TYPE_HEADER ||
flit_i[flit_width-1:flit_width-2] == FLIT_TYPE_SINGLE) begin
nxt_req_vchannel = flit_i[class_msb:class_lsb];
nxt_state = SENDING;
nxt_flit_o = flit_i;
ready_for_input = 1'b1;
nxt_valid_o[nxt_req_vchannel] = 1'b1;
end else begin
nxt_req_vchannel = req_vchannel;
nxt_state = WAITING;
ready_for_input = 1'b0;
end
end
SENDING: begin : sending
nxt_flit_o = flit_o;
nxt_valid_o[req_vchannel] = 1'b1;
if(ready_for_output[req_vchannel] == 1'b1) begin
ready_for_input = 1'b1;
nxt_flit_o = flit_i;
if(flit_o[flit_width-1:flit_width-2] == FLIT_TYPE_SINGLE ||
flit_o[flit_width-1:flit_width-2] == FLIT_TYPE_LAST) begin
nxt_state = WAITING;
nxt_valid_o[nxt_req_vchannel] = 1'b0;
end else begin
nxt_state = SENDING;
end
end else begin
ready_for_input = 1'b0;
nxt_state = state;
nxt_flit_o = flit_o;
end
end
endcase
end
always @ (posedge clk) begin
if(rst == 1'b1) begin
flit_o = 'hx;
valid_o = {vchannels{1'b0}};
state = 1'b0;
end else begin
flit_o = nxt_flit_o;
valid_o = nxt_valid_o;
req_vchannel = nxt_req_vchannel;
state = nxt_state;
end
end
endmodule
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is a multiplexer that muxes several incoming vchannels to a
* single one. It ensures wormhole forwarding in a first-come,
* first-served way. There must not be two valid vchannels at the
* same time, so it cannot be used as an arbiter!
*
* Author(s):
* Michael Tempelmeier <[email protected]>
*/
`include "lisnoc_def.vh"
module lisnoc_vc_multiplexer(/*AUTOARG*/
// Outputs
ready_o, valid_o, data_o,
// Inputs
clk, rst, valid_i, data_i, ready_i
);
parameter vchannels = 3;
parameter flit_width = 32;
input clk;
input rst;
//n-vchannel in
input [vchannels-1:0] valid_i;
output [vchannels-1:0] ready_o;
input [flit_width-1:0] data_i;
//one vchannel out
input ready_i;
output valid_o;
output [flit_width-1:0] data_o;
reg state;
reg nxt_state;
`define STATE_READY 1'b0
`define STATE_VALID 1'b1
reg [vchannels-1 :0] channel_mask;
reg [vchannels-1 :0] nxt_channel_mask;
assign data_o = data_i;
assign valid_o = |(valid_i & channel_mask);
assign ready_o = channel_mask & {vchannels{ready_i}};
always @ (*) begin : fsm_logic
//default:
nxt_state = state;
nxt_channel_mask = channel_mask;
case (state)
`STATE_READY: begin
if (ready_i) begin
if((data_i[flit_width-1:flit_width-2] == `FLIT_TYPE_HEADER) && (|valid_i)) begin
//save the current vchannel if a new packet arrives
//if the packet is a single-flit we don't need this information since there are no
//following flits that have to be served on the same vchannel
nxt_state = `STATE_VALID;
nxt_channel_mask = valid_i; //save the current channel;
end
end
end // case: `STATE_READY
`STATE_VALID: begin
if (ready_i) begin
if((data_i[flit_width-1:flit_width-2] == `FLIT_TYPE_LAST) && (valid_i & channel_mask)) begin
//end of packet - we are ready for a new one
nxt_state = `STATE_READY;
nxt_channel_mask = {vchannels{1'b1}};
end
end
end
default: begin
//nothing
end
endcase // case (state)
end // block: fsm_logic
always @ (posedge clk) begin : fsm_reg
if (rst) begin
state = `STATE_READY;
channel_mask = {vchannels{1'b1}};
end else begin
state = nxt_state;
channel_mask = nxt_channel_mask;
end
end
endmodule // lisnoc_vc_multiplexer
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is a serializer that serializes several incoming vchannels to a
* single one. It ensures wormhole forwarding in a first-come,
* first-served way. There must not be two valid vchannels at the
* same time, so it cannot be used as an arbiter!
*
* Author(s):
* Michael Tempelmeier <[email protected]>
*/
`include "lisnoc_def.vh"
module lisnoc_vc_serializer(/*AUTOARG*/
// Outputs
ready_mvc, valid_ser, data_ser,
// Inputs
clk, rst, valid_mvc, data_mvc, ready_ser
);
parameter vchannels = 3;
parameter flit_width = 32;
input clk;
input rst;
//n-vchannel in (multiple vchannels)
input [vchannels-1:0] valid_mvc;
output [vchannels-1:0] ready_mvc;
input [flit_width-1:0] data_mvc;
//one vchannel out (serialized)
input ready_ser;
output valid_ser;
output [flit_width-1:0] data_ser;
reg state;
reg nxt_state;
localparam STATE_READY = 1'b0;
localparam STATE_VALID = 1'b1;
reg [vchannels-1 :0] channel_mask;
reg [vchannels-1 :0] nxt_channel_mask;
assign data_ser = data_mvc;
assign valid_ser = |(valid_mvc & channel_mask);
assign ready_mvc = channel_mask & {vchannels{ready_ser}};
always @ (*) begin : fsm_logic
//default:
nxt_state = state;
nxt_channel_mask = channel_mask;
case (state)
STATE_READY: begin
if (ready_ser) begin
if((data_mvc[flit_width-1:flit_width-2] == `FLIT_TYPE_HEADER) && (|valid_mvc)) begin
//save the current vchannel if a new packet arrives
//if the packet is a single-flit we don't need this information since there are no
//following flits that have to be served on the same vchannel
nxt_state = STATE_VALID;
nxt_channel_mask = valid_mvc; //save the current channel;
end
end
end // case: STATE_READY
STATE_VALID: begin
if (ready_ser) begin
if((data_mvc[flit_width-1:flit_width-2] == `FLIT_TYPE_LAST) && (valid_mvc & channel_mask)) begin
//end of packet - we are ready for a new one
nxt_state = STATE_READY;
nxt_channel_mask = {vchannels{1'b1}};
end
end
end
default: begin
//nothing
end
endcase // case (state)
end // block: fsm_logic
always @ (posedge clk) begin : fsm_reg
if (rst) begin
state = STATE_READY;
channel_mask = {vchannels{1'b1}};
end else begin
state = nxt_state;
channel_mask = nxt_channel_mask;
end
end
endmodule // lisnoc_vc_multiplexer
|
/* Copyright (c) 2012-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* The wishbone slave interface to access the simple message passing.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*
*/
module mpbuffer
import optimsoc_config::*;
#(parameter config_t CONFIG = 'x,
parameter SIZE = 16,
parameter N = 1
)
(
input clk,
input rst,
output [N*CONFIG.NOC_FLIT_WIDTH-1:0] noc_out_flit,
output [N-1:0] noc_out_last,
output [N-1:0] noc_out_valid,
input [N-1:0] noc_out_ready,
input [N*CONFIG.NOC_FLIT_WIDTH-1:0] noc_in_flit,
input [N-1:0] noc_in_last,
input [N-1:0] noc_in_valid,
output [N-1:0] noc_in_ready,
// Bus side (generic)
input [31:0] bus_addr,
input bus_we,
input bus_en,
input [31:0] bus_data_in,
output reg [31:0] bus_data_out,
output bus_ack,
output bus_err,
output irq
);
wire [N:0] bus_sel_mod;
wire [N:0] bus_err_mod;
wire [N:0] bus_ack_mod;
wire [N:0][31:0] bus_data_mod;
wire [N-1:0] irq_mod;
genvar n;
generate
for (n = 0; n <= N; n++) begin
assign bus_sel_mod[n] = (bus_addr[19:13] == n);
end
endgenerate
always @(*) begin
bus_data_out = 32'hx;
for (int i = 0; i <= N; i++) begin
if (bus_sel_mod[i])
bus_data_out = bus_data_mod[i];
end
end
assign bus_ack = |bus_ack_mod;
assign bus_err = |bus_err_mod;
assign irq = |irq_mod;
assign bus_ack_mod[0] = bus_en & bus_sel_mod[0] & !bus_we & (bus_addr[12:0] == 0);
assign bus_err_mod[0] = bus_en & bus_sel_mod[0] & (bus_we | (bus_addr[12:0] != 0));
assign bus_data_mod[0] = N;
generate
for (n = 0; n < N; n++) begin
mpbuffer_endpoint
#(.CONFIG(CONFIG), .SIZE(SIZE))
u_endpoint
(.*,
.noc_out_flit (noc_out_flit[n*CONFIG.NOC_FLIT_WIDTH +: CONFIG.NOC_FLIT_WIDTH]),
.noc_out_last (noc_out_last[n]),
.noc_out_valid (noc_out_valid[n]),
.noc_out_ready (noc_out_ready[n]),
.noc_in_flit (noc_in_flit[n*CONFIG.NOC_FLIT_WIDTH +: CONFIG.NOC_FLIT_WIDTH]),
.noc_in_last (noc_in_last[n]),
.noc_in_valid (noc_in_valid[n]),
.noc_in_ready (noc_in_ready[n]),
.bus_en (bus_en & bus_sel_mod[n+1]),
.bus_data_out (bus_data_mod[n+1]),
.bus_ack (bus_ack_mod[n+1]),
.bus_err (bus_err_mod[n+1]),
.irq (irq_mod[n])
);
end
endgenerate
endmodule // mpbuffer
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* Simple (software-controlled) message passing module.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
/*
*
* +-> Input path <- packet buffer <-- Ingress
* | * raise interrupt (!empty)
* Bus interface --> + * read size flits from packet buffer
* |
* +-> Output path -> packet buffer --> Egress
* * set size
* * write flits to packet buffer
*
* Ingress <---+----- NoC
* |
* Handle control message
* |
* Egress ----+----> NoC
*/
module mpbuffer_endpoint
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
parameter SIZE = 16
)
(
input clk,
input rst,
output reg [CONFIG.NOC_FLIT_WIDTH-1:0] noc_out_flit,
output reg noc_out_last,
output reg noc_out_valid,
input noc_out_ready,
input [CONFIG.NOC_FLIT_WIDTH-1:0] noc_in_flit,
input noc_in_last,
input noc_in_valid,
output reg noc_in_ready,
// Bus side (generic)
input [31:0] bus_addr,
input bus_we,
input bus_en,
input [31:0] bus_data_in,
output reg [31:0] bus_data_out,
output reg bus_ack,
output reg bus_err,
output irq
);
import optimsoc_functions::*;
localparam SIZE_WIDTH = clog2_width(SIZE);
// Connect from the outgoing state machine to the packet buffer
wire [CONFIG.NOC_FLIT_WIDTH-1:0] out_flit;
reg out_last;
reg out_valid;
wire out_ready;
wire [CONFIG.NOC_FLIT_WIDTH-1:0] in_flit;
wire in_last;
wire in_valid;
reg in_ready;
reg enabled;
reg nxt_enabled;
assign irq = in_valid;
assign out_flit = bus_data_in;
reg if_fifo_in_en;
reg if_fifo_in_ack;
reg [31:0] if_fifo_in_data;
reg if_fifo_out_en;
reg if_fifo_out_ack;
/*
* +------+---+------------------------+
* | 0x0 | R | Read from Ingress FIFO |
* +------+---+------------------------+
* | | W | Write to Egress FIFO |
* +------+---+------------------------+
* | 0x4 | W | Enable interface |
* +------+---+------------------------+
* | | R | Status |
* +------+---+------------------------+
*
*/
always @(*) begin
bus_ack = 0;
bus_err = 0;
bus_data_out = 32'hx;
nxt_enabled = enabled;
if_fifo_in_en = 1'b0;
if_fifo_out_en = 1'b0;
if (bus_en) begin
if (bus_addr[5:2] == 4'h0) begin
if (!bus_we) begin
if_fifo_in_en = 1'b1;
bus_ack = if_fifo_in_ack;
bus_data_out = if_fifo_in_data;
end else begin
if_fifo_out_en = 1'b1;
bus_ack = if_fifo_out_ack;
end
end else if (bus_addr[5:2] == 4'h1) begin
bus_ack = 1'b1;
if (bus_we) begin
nxt_enabled = 1'b1;
end else begin
bus_data_out = {30'h0, noc_out_valid, in_valid};
end
end else begin
bus_err = 1'b1;
end
end // if (bus_en)
end // always @ begin
always @(posedge clk) begin
if (rst) begin
enabled <= 1'b0;
end else begin
enabled <= nxt_enabled;
end
end
/**
* Simple writes to 0x0
* * Start transfer and set size S
* * For S flits: Write flit
*/
// State register
reg [1:0] state_out;
reg [1:0] nxt_state_out;
reg state_in;
reg nxt_state_in;
// Size register that is also used to count down the remaining
// flits to be send out
reg [SIZE_WIDTH-1:0] size_out;
reg [SIZE_WIDTH-1:0] nxt_size_out;
wire [SIZE_WIDTH:0] size_in;
// States of output state machine
localparam OUT_IDLE = 0;
localparam OUT_FIRST = 1;
localparam OUT_PAYLOAD = 2;
// States of input state machine
localparam IN_IDLE = 0;
localparam IN_FLIT = 1;
// Combinational part of input state machine
always @(*) begin
in_ready = 1'b0;
if_fifo_in_ack = 1'b0;
if_fifo_in_data = 32'hx;
nxt_state_in = state_in;
case(state_in)
IN_IDLE: begin
if (if_fifo_in_en) begin
if (in_valid) begin
if_fifo_in_data = {{31-SIZE_WIDTH{1'b0}},size_in};
if_fifo_in_ack = 1'b1;
if (size_in!=0) begin
nxt_state_in = IN_FLIT;
end
end else begin
if_fifo_in_data = 0;
if_fifo_in_ack = 1'b1;
nxt_state_in = IN_IDLE;
end
end else begin
nxt_state_in = IN_IDLE;
end
end
IN_FLIT: begin
if (if_fifo_in_en) begin
if_fifo_in_data = in_flit[31:0];
in_ready = 1'b1;
if_fifo_in_ack = 1'b1;
if (size_in==1) begin
nxt_state_in = IN_IDLE;
end else begin
nxt_state_in = IN_FLIT;
end
end else begin
nxt_state_in = IN_FLIT;
end
end // case: IN_FLIT
default: begin
nxt_state_in = IN_IDLE;
end
endcase
end
// Combinational part of output state machine
always @(*) begin
// default values
out_valid = 1'b0; // no flit
nxt_size_out = size_out; // keep size
if_fifo_out_ack = 1'b0; // don't acknowledge
out_last = 1'bx; // Default is undefined
case(state_out)
OUT_IDLE: begin
// Transition from IDLE to FIRST
// when write on bus, which is the size
if (if_fifo_out_en) begin
// Store the written value as size
nxt_size_out = bus_data_in[SIZE_WIDTH-1:0];
// Acknowledge to the bus
if_fifo_out_ack = 1'b1;
nxt_state_out = OUT_FIRST;
end else begin
nxt_state_out = OUT_IDLE;
end
end
OUT_FIRST: begin
// The first flit is written from the bus now.
// This can be either the only flit (size==1)
// or a further flits will follow.
// Forward the flits to the packet buffer.
if (if_fifo_out_en) begin
// When the bus writes, the data is statically assigned
// to out_flit. Set out_valid to signal the flit should
// be output
out_valid = 1'b1;
if (size_out==1) begin
out_last = 1'b1;
end
if (out_ready) begin
// When the output packet buffer is ready this cycle
// the flit has been stored in the packet buffer
// Decrement size
nxt_size_out = size_out-1;
// Acknowledge to the bus
if_fifo_out_ack = 1'b1;
if (size_out==1) begin
// When this was the only flit, go to IDLE again
nxt_state_out = OUT_IDLE;
end else begin
// Otherwise accept further flis as payload
nxt_state_out = OUT_PAYLOAD;
end
end else begin // if (out_ready)
// If the packet buffer is not ready, we simply hold
// the data and valid and wait another cycle for the
// packet buffer to become ready
nxt_state_out = OUT_FIRST;
end
end else begin // if (bus_we && bus_en)
// Wait for the bus
nxt_state_out = OUT_FIRST;
end
end
OUT_PAYLOAD: begin
// After the first flit (HEADER) further flits are
// forwarded in this state. The essential difference to the
// FIRST state is in the output type which can here be
// PAYLOAD or LAST
if (bus_we && bus_en) begin
// When the bus writes, the data is statically assigned
// to out_flit. Set out_valid to signal the flit should
// be output
out_valid = 1'b1;
if (size_out==1) begin
out_last = 1'b1;
end
if (out_ready) begin
// When the output packet buffer is ready this cycle
// the flit has been stored in the packet buffer
// Decrement size
nxt_size_out = size_out-1;
// Acknowledge to the bus
if_fifo_out_ack = 1'b1;
if (size_out==1) begin
// When this was the last flit, go to IDLE again
nxt_state_out = OUT_IDLE;
end else begin
// Otherwise accept further flis as payload
nxt_state_out = OUT_PAYLOAD;
end
end else begin // if (out_ready)
// If the packet buffer is not ready, we simply hold
// the data and valid and wait another cycle for the
// packet buffer to become ready
nxt_state_out = OUT_PAYLOAD;
end
end else begin // if (bus_we && bus_en)
// Wait for the bus
nxt_state_out = OUT_PAYLOAD;
end
end
default: begin
// Defaulting to go to idle
nxt_state_out = OUT_IDLE;
end
endcase
end
// Sequential part of both state machines
always @(posedge clk) begin
if (rst) begin
state_out <= OUT_IDLE; // Start in idle state
// size does not require a reset value (not used before set)
state_in <= IN_IDLE;
end else begin
// Register combinational values
state_out <= nxt_state_out;
size_out <= nxt_size_out;
state_in <= nxt_state_in;
end
end
reg [CONFIG.NOC_FLIT_WIDTH-1:0] ingress_flit;
reg ingress_last;
reg ingress_valid;
wire ingress_ready;
wire [CONFIG.NOC_FLIT_WIDTH-1:0] egress_flit;
wire egress_last;
wire egress_valid;
reg egress_ready;
reg [CONFIG.NOC_FLIT_WIDTH-1:0] control_flit;
reg [CONFIG.NOC_FLIT_WIDTH-1:0] nxt_control_flit;
reg control_pending;
reg nxt_control_pending;
always @(*) begin
noc_in_ready = !control_pending & ingress_ready;
ingress_flit = noc_in_flit;
nxt_control_pending = control_pending;
nxt_control_flit = control_flit;
// Ingress part
ingress_valid = noc_in_valid;
ingress_last = noc_in_last;
if ((noc_in_valid & !control_pending) &&
(noc_in_flit[26:24] == 3'b111) &&
!noc_in_flit[0]) begin
nxt_control_pending = 1'b1;
nxt_control_flit[31:27] = noc_in_flit[23:19];
nxt_control_flit[26:24] = 3'b111;
nxt_control_flit[23:19] = noc_in_flit[31:27];
nxt_control_flit[18:2] = noc_in_flit[18:2];
nxt_control_flit[1] = enabled;
nxt_control_flit[0] = 1'b1;
ingress_valid = 1'b0;
ingress_last = 1'b1;
end
// Egress part
if (egress_valid & !egress_last) begin
egress_ready = noc_out_ready;
noc_out_valid = egress_valid;
noc_out_flit = egress_flit;
noc_out_last = egress_last;
end else if (control_pending) begin
egress_ready = 1'b0;
noc_out_valid = 1'b1;
noc_out_flit = control_flit;
noc_out_last = 1'b1;
if (noc_out_ready) begin
nxt_control_pending = 1'b0;
end
end else begin
egress_ready = noc_out_ready;
noc_out_valid = egress_valid;
noc_out_last = egress_last;
noc_out_flit = egress_flit;
end
end // always @ begin
always @(posedge clk) begin
if (rst) begin
control_pending <= 1'b0;
control_flit <= {CONFIG.NOC_FLIT_WIDTH{1'hx}};
end else begin
control_pending <= nxt_control_pending;
control_flit <= nxt_control_flit;
end
end
// The output packet buffer
noc_buffer
#(.DEPTH(SIZE), .FLIT_WIDTH(CONFIG.NOC_FLIT_WIDTH), .FULLPACKET(1))
u_packetbuffer_out(.*,
.in_ready (out_ready),
.in_flit (out_flit),
.in_last (out_last),
.in_valid (out_valid),
.packet_size (),
.out_flit (egress_flit),
.out_last (egress_last),
.out_valid (egress_valid),
.out_ready (egress_ready));
// The input packet buffer
noc_buffer
#(.DEPTH(SIZE), .FLIT_WIDTH(CONFIG.NOC_FLIT_WIDTH), .FULLPACKET(1))
u_packetbuffer_in(.*,
.in_ready (ingress_ready),
.in_flit (ingress_flit),
.in_last (ingress_last),
.in_valid (ingress_valid),
.packet_size (size_in),
.out_flit (in_flit),
.out_last (in_last),
.out_valid (in_valid),
.out_ready (in_ready));
endmodule // mpbuffer_endpoint
|
/* Copyright (c) 2012-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* The wishbone slave interface to access the simple message passing.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*
*/
module mpbuffer_wb
import optimsoc_config::*;
#(parameter config_t CONFIG = 'x,
parameter SIZE = 16,
parameter N = 1
)
(
input clk,
input rst,
output [N*CONFIG.NOC_FLIT_WIDTH-1:0] noc_out_flit,
output [N-1:0] noc_out_last,
output [N-1:0] noc_out_valid,
input [N-1:0] noc_out_ready,
input [N*CONFIG.NOC_FLIT_WIDTH-1:0] noc_in_flit,
input [N-1:0] noc_in_last,
input [N-1:0] noc_in_valid,
output [N-1:0] noc_in_ready,
input [31:0] wb_adr_i,
input wb_we_i,
input wb_cyc_i,
input wb_stb_i,
input [31:0] wb_dat_i,
output [31:0] wb_dat_o,
output wb_ack_o,
output wb_err_o,
output irq
);
// Bus side (generic)
wire [31:0] bus_addr;
wire bus_we;
wire bus_en;
wire [31:0] bus_data_in;
wire [31:0] bus_data_out;
wire bus_ack;
wire bus_err;
assign bus_addr = wb_adr_i;
assign bus_we = wb_we_i;
assign bus_en = wb_cyc_i & wb_stb_i;
assign bus_data_in = wb_dat_i;
assign wb_dat_o = bus_data_out;
assign wb_ack_o = bus_ack;
assign wb_err_o = bus_err;
mpbuffer
#(.CONFIG(CONFIG),
.SIZE(SIZE), .N(N))
u_buffer(.*);
endmodule // mpbuffer_wb
|
/* Copyright (c) 2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* Buffer for NoC packets
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
* Wei Song <[email protected]>
*/
module noc_buffer
#(parameter FLIT_WIDTH = 32,
parameter DEPTH = 16,
parameter FULLPACKET = 0,
localparam ID_W = $clog2(DEPTH) // the width of the index
)(
input clk,
input rst,
// FIFO input side
input [FLIT_WIDTH-1:0] in_flit,
input in_last,
input in_valid,
output in_ready,
//FIFO output side
output reg [FLIT_WIDTH-1:0] out_flit,
output reg out_last,
output reg out_valid,
input out_ready,
output [ID_W-1:0] packet_size
);
// internal shift register
reg [DEPTH-1:0][FLIT_WIDTH:0] data;
reg [ID_W:0] rp; // read pointer
logic reg_out_valid; // local output valid
logic in_fire, out_fire;
assign in_ready = (rp != DEPTH - 1) || !reg_out_valid;
assign in_fire = in_valid && in_ready;
assign out_fire = out_valid && out_ready;
always_ff @(posedge clk)
if(rst)
reg_out_valid <= 0;
else if(in_valid)
reg_out_valid <= 1;
else if(out_fire && rp == 0)
reg_out_valid <= 0;
always_ff @(posedge clk)
if(rst)
rp <= 0;
else if(in_fire && !out_fire && reg_out_valid)
rp <= rp + 1;
else if(out_fire && !in_fire && rp != 0)
rp <= rp - 1;
always @(posedge clk)
if(in_fire)
data <= {data, {in_last, in_flit}};
generate // SRL does not allow parallel read
if(FULLPACKET != 0) begin
logic [DEPTH-1:0] data_last_buf, data_last_shifted;
always @(posedge clk)
if(rst)
data_last_buf <= 0;
else if(in_fire)
data_last_buf <= {data_last_buf, in_last && in_valid};
// extra logic to get the packet size in a stable manner
assign data_last_shifted = data_last_buf << DEPTH - 1 - rp;
function logic [ID_W:0] find_first_one(input logic [DEPTH-1:0] data);
automatic int i;
for(i=DEPTH-1; i>=0; i--)
if(data[i]) return i;
return DEPTH;
endfunction // size_count
assign packet_size = DEPTH - find_first_one(data_last_shifted);
always_comb begin
out_flit = data[rp][FLIT_WIDTH-1:0];
out_last = data[rp][FLIT_WIDTH];
out_valid = reg_out_valid && |data_last_shifted;
end
end else begin // if (FULLPACKET)
assign packet_size = 0;
always_comb begin
out_flit = data[rp][FLIT_WIDTH-1:0];
out_last = data[rp][FLIT_WIDTH];
out_valid = reg_out_valid;
end
end
endgenerate
endmodule // noc_buffer
|
/* Copyright (c) 2015-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* Route packets to an output port depending on the class
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module noc_demux
import optimsoc_config::*;
import optimsoc_constants::*;
#(
parameter FLIT_WIDTH = 32,
parameter CHANNELS = 2,
parameter [63:0] MAPPING = 'x
)
(
input clk, rst,
input [FLIT_WIDTH-1:0] in_flit,
input in_last,
input in_valid,
output reg in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] out_flit,
output [CHANNELS-1:0] out_last,
output reg [CHANNELS-1:0] out_valid,
input [CHANNELS-1:0] out_ready
);
reg [CHANNELS-1:0] active;
reg [CHANNELS-1:0] nxt_active;
wire [2:0] packet_class;
reg [CHANNELS-1:0] select;
assign packet_class = in_flit[NOC_CLASS_MSB:NOC_CLASS_LSB];
always @(*) begin : gen_select
select = MAPPING[8*packet_class +: CHANNELS];
if (select == 0) begin
select = { {CHANNELS-1{1'b0}}, 1'b1};
end
end
assign out_flit = {CHANNELS{in_flit}};
assign out_last = {CHANNELS{in_last}};
always @(*) begin
nxt_active = active;
out_valid = 0;
in_ready = 0;
if (active == 0) begin
in_ready = |(select & out_ready);
out_valid = select & {CHANNELS{in_valid}};
if (in_valid & ~in_last) begin
nxt_active = select;
end
end else begin
in_ready = |(active & out_ready);
out_valid = active & {CHANNELS{in_valid}};
if (in_valid & in_last) begin
nxt_active = 0;
end
end
end
always @(posedge clk)
if (rst) begin
active <= '0;
end else begin
active <= nxt_active;
end
endmodule // noc_demux
|
/* Copyright (c) 2015-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* Arbitrate between different channels, don't break worms.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
* Andreas Lankes <[email protected]>
*/
module noc_mux
import optimsoc_config::*;
#(
parameter FLIT_WIDTH = 32,
parameter CHANNELS = 2
)
(
input clk, rst,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] in_flit,
input [CHANNELS-1:0] in_last,
input [CHANNELS-1:0] in_valid,
output reg [CHANNELS-1:0] in_ready,
output reg [FLIT_WIDTH-1:0] out_flit,
output reg out_last,
output reg out_valid,
input out_ready
);
wire [CHANNELS-1:0] select;
reg [CHANNELS-1:0] active;
reg activeroute, nxt_activeroute;
wire [CHANNELS-1:0] req_masked;
assign req_masked = {CHANNELS{~activeroute & out_ready}} & in_valid;
always @(*) begin
out_flit = {FLIT_WIDTH{1'b0}};
out_last = 1'b0;
for (int c = 0; c < CHANNELS; c = c + 1) begin
if (select[c]) begin
out_flit = in_flit[c];
out_last = in_last[c];
end
end
end
always @(*) begin
nxt_activeroute = activeroute;
in_ready = {CHANNELS{1'b0}};
if (activeroute) begin
if (|(in_valid & active) && out_ready) begin
in_ready = active;
out_valid = 1;
if (out_last)
nxt_activeroute = 0;
end else begin
out_valid = 1'b0;
in_ready = 0;
end
end else begin
out_valid = 0;
if (|in_valid) begin
out_valid = 1'b1;
nxt_activeroute = ~out_last;
in_ready = select & {CHANNELS{out_ready}};
end
end
end // always @ (*)
always @(posedge clk) begin
if (rst) begin
activeroute <= 0;
active <= {{CHANNELS-1{1'b0}},1'b1};
end else begin
activeroute <= nxt_activeroute;
active <= select;
end
end
arb_rr
#(.N(CHANNELS))
u_arb
(.nxt_gnt (select),
.req (req_masked),
.gnt (active),
.en (1));
endmodule // noc_mux
|
/* Copyright (c) 2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is a NoC router. It has a configurable number of input ports
* and output ports, that are not necessarily equal. It supports
* virtual channels, meaning that the flit signal between routers is
* shared logically.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module noc_router
#(parameter FLIT_WIDTH = 32,
parameter VCHANNELS = 1,
parameter INPUTS = 'x,
parameter OUTPUTS = 'x,
parameter BUFFER_SIZE_IN = 4,
parameter BUFFER_SIZE_OUT = 4,
parameter DESTS = 'x,
parameter [OUTPUTS*DESTS-1:0] ROUTES = {DESTS*OUTPUTS{1'b0}}
)
(
input clk, rst,
output [OUTPUTS-1:0][FLIT_WIDTH-1:0] out_flit,
output [OUTPUTS-1:0] out_last,
output [OUTPUTS-1:0][VCHANNELS-1:0] out_valid,
input [OUTPUTS-1:0][VCHANNELS-1:0] out_ready,
input [INPUTS-1:0][FLIT_WIDTH-1:0] in_flit,
input [INPUTS-1:0] in_last,
input [INPUTS-1:0][VCHANNELS-1:0] in_valid,
output [INPUTS-1:0][VCHANNELS-1:0] in_ready
);
// The "switch" is just wiring (all logic is in input and
// output). All inputs generate their requests for the outputs and
// the output arbitrate between the input requests.
// The input valid signals are one (or zero) hot and hence share
// the flit signal.
wire [INPUTS-1:0][VCHANNELS-1:0][FLIT_WIDTH-1:0] switch_in_flit;
wire [INPUTS-1:0][VCHANNELS-1:0] switch_in_last;
wire [INPUTS-1:0][VCHANNELS-1:0][OUTPUTS-1:0] switch_in_valid;
wire [INPUTS-1:0][VCHANNELS-1:0][OUTPUTS-1:0] switch_in_ready;
// Outputs are fully wired to receive all input requests.
wire [OUTPUTS-1:0][VCHANNELS-1:0][INPUTS-1:0][FLIT_WIDTH-1:0] switch_out_flit;
wire [OUTPUTS-1:0][VCHANNELS-1:0][INPUTS-1:0] switch_out_last;
wire [OUTPUTS-1:0][VCHANNELS-1:0][INPUTS-1:0] switch_out_valid;
wire [OUTPUTS-1:0][VCHANNELS-1:0][INPUTS-1:0] switch_out_ready;
genvar i, v, o;
generate
for (i = 0; i < INPUTS; i++) begin : inputs
// The input stages
noc_router_input
#(.FLIT_WIDTH(FLIT_WIDTH), .VCHANNELS(VCHANNELS),
.DESTS(DESTS), .OUTPUTS(OUTPUTS), .ROUTES(ROUTES),
.BUFFER_DEPTH (BUFFER_SIZE_IN))
u_input
(.*,
.in_flit (in_flit[i]),
.in_last (in_last[i]),
.in_valid (in_valid[i]),
.in_ready (in_ready[i]),
.out_flit (switch_in_flit[i]),
.out_last (switch_in_last[i]),
.out_valid (switch_in_valid[i]),
.out_ready (switch_in_ready[i])
);
end // block: inputs
// The switching logic
for (o = 0; o < OUTPUTS; o++) begin
for (v = 0; v < VCHANNELS; v++) begin
for (i = 0; i < INPUTS; i++) begin
assign switch_out_flit[o][v][i] = switch_in_flit[i][v];
assign switch_out_last[o][v][i] = switch_in_last[i][v];
assign switch_out_valid[o][v][i] = switch_in_valid[i][v][o];
assign switch_in_ready[i][v][o] = switch_out_ready[o][v][i];
end
end
end
for (o = 0; o < OUTPUTS; o++) begin : outputs
// The output stages
noc_router_output
#(.FLIT_WIDTH(FLIT_WIDTH), .VCHANNELS(VCHANNELS),
.INPUTS(INPUTS), .BUFFER_DEPTH(BUFFER_SIZE_OUT))
u_output
(.*,
.in_flit (switch_out_flit[o]),
.in_last (switch_out_last[o]),
.in_valid (switch_out_valid[o]),
.in_ready (switch_out_ready[o]),
.out_flit (out_flit[o]),
.out_last (out_last[o]),
.out_valid (out_valid[o]),
.out_ready (out_ready[o]));
end
endgenerate
endmodule // noc_router
|
/* Copyright (c) 2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the input stage of the router. It buffers the flits and
* routes them to the proper output.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module noc_router_input
#(parameter FLIT_WIDTH = 'x,
parameter VCHANNELS = 1,
parameter DESTS = 1,
parameter OUTPUTS = 1,
parameter [OUTPUTS*DESTS-1:0] ROUTES = {DESTS*OUTPUTS{1'b0}},
parameter BUFFER_DEPTH = 4
)
(
input clk,
input rst,
input [FLIT_WIDTH-1:0] in_flit,
input in_last,
input [VCHANNELS-1:0] in_valid,
output [VCHANNELS-1:0] in_ready,
output [VCHANNELS-1:0][OUTPUTS-1:0] out_valid,
output [VCHANNELS-1:0] out_last,
output [VCHANNELS-1:0][FLIT_WIDTH-1:0] out_flit,
input [VCHANNELS-1:0][OUTPUTS-1:0] out_ready
);
generate
genvar v;
for (v = 0; v < VCHANNELS; v++) begin : vc
wire [FLIT_WIDTH-1:0] buffer_flit;
wire buffer_last;
wire buffer_valid;
wire buffer_ready;
noc_buffer
#(.FLIT_WIDTH (FLIT_WIDTH),
.DEPTH (BUFFER_DEPTH))
u_buffer
(.*,
.in_valid (in_valid[v]),
.in_ready (in_ready[v]),
.out_flit (buffer_flit),
.out_last (buffer_last),
.out_valid (buffer_valid),
.out_ready (buffer_ready),
.packet_size ()
);
noc_router_lookup
#(.FLIT_WIDTH (FLIT_WIDTH), .DESTS (DESTS),
.OUTPUTS (OUTPUTS), .ROUTES (ROUTES))
u_lookup
(.*,
.in_flit (buffer_flit),
.in_last (buffer_last),
.in_valid (buffer_valid),
.in_ready (buffer_ready),
.out_flit (out_flit[v]),
.out_last (out_last[v]),
.out_valid (out_valid[v]),
.out_ready (out_ready[v])
);
end
endgenerate
endmodule // noc_router_input
|
/* Copyright (c) 2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the route lookup. It uses a given table of routes. It first
* extracts the destination of the incoming NoC packets and then looks
* the output port up. The output valid and ready signals contain bits
* for each output and the flit and last are shared by the outputs.
*
* The output of this module is registered, minimizing the critical
* path to the lookup function.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module noc_router_lookup
#(parameter FLIT_WIDTH = 32,
parameter DEST_WIDTH = 5,
parameter DESTS = 1,
parameter OUTPUTS = 1,
parameter [DESTS*OUTPUTS-1:0] ROUTES = {DESTS*OUTPUTS{1'b0}}
)
(
input clk,
input rst,
input [FLIT_WIDTH-1:0] in_flit,
input in_last,
input in_valid,
output in_ready,
output [OUTPUTS-1:0] out_valid,
output out_last,
output [FLIT_WIDTH-1:0] out_flit,
input [OUTPUTS-1:0] out_ready
);
// We need to track worms and directly encode the output of the
// current worm.
reg [OUTPUTS-1:0] worm;
logic [OUTPUTS-1:0] nxt_worm;
// This is high if we are in a worm
logic wormhole;
assign wormhole = |worm;
// Extract destination from flit
logic [DEST_WIDTH-1:0] dest;
assign dest = in_flit[FLIT_WIDTH-1 -: DEST_WIDTH];
// This is the selection signal of the slave, one hot so that it
// directly serves as flow control valid
logic [OUTPUTS-1:0] valid;
// Register slice at the output.
noc_router_lookup_slice
#(.FLIT_WIDTH (FLIT_WIDTH),
.OUTPUTS (OUTPUTS))
u_slice
(.*,
.in_valid (valid));
always_comb begin
nxt_worm = worm;
valid = 0;
if (!wormhole) begin
// We are waiting for a flit
if (in_valid) begin
// This is a header. Lookup output
valid = ROUTES[dest*OUTPUTS +: OUTPUTS];
if (in_ready & !in_last) begin
// If we can push it further and it is not the only
// flit, enter a worm and store the output
nxt_worm = ROUTES[dest*OUTPUTS +: OUTPUTS];
end
end
end else begin // if (!wormhole)
// We are in a worm
// The valid is set on the currently select output
valid = worm & {OUTPUTS{in_valid}};
if (in_ready & in_last) begin
// End of worm
nxt_worm = 0;
end
end
end
always_ff @(posedge clk) begin
if (rst) begin
worm <= 0;
end else begin
worm <= nxt_worm;
end
end
endmodule
|
/* Copyright (c) 2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
*
* This is a register slice at the routing stage of the router. It
* latches the current flit and decouples the outputs and the input
* entirely. That means that there is no combinational path from input
* to output and vice versa. Hence it allows for higher clock
* speeds. To avoid stop-and-go behavior it has a second register to
* be able to store the extra register on backpressure. The
* backpressure then manifests with one cycle delay.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module noc_router_lookup_slice
#(parameter FLIT_WIDTH = 32,
parameter OUTPUTS = 1
)
(
input clk,
input rst,
input [FLIT_WIDTH-1:0] in_flit,
input in_last,
input [OUTPUTS-1:0] in_valid,
output in_ready,
output reg [OUTPUTS-1:0] out_valid,
output reg out_last,
output reg [FLIT_WIDTH-1:0] out_flit,
input [OUTPUTS-1:0] out_ready
);
// This is an intermediate register that we use to avoid
// stop-and-go behavior
reg [FLIT_WIDTH-1:0] reg_flit;
reg reg_last;
reg [OUTPUTS-1:0] reg_valid;
// This signal selects where to store the next incoming flit
reg pressure;
// A backpressure in the output port leads to backpressure on the
// input with one cycle delay
assign in_ready = !pressure;
always_ff @(posedge clk) begin
if (rst) begin
pressure <= 0;
out_valid <= 0;
end else begin
if (!pressure) begin
// We are accepting the input in this cycle, determine
// where to store it..
if (// There is no flit waiting in the register, or
~|out_valid
// The current flit is transfered this cycle
| (|(out_ready & out_valid))) begin
out_flit <= in_flit;
out_last <= in_last;
out_valid <= in_valid;
end else if (|out_valid & ~|out_ready) begin
// Otherwise if there is a flit waiting and upstream
// not ready, push it to the second register. Enter the
// backpressure mode.
reg_flit <= in_flit;
reg_last <= in_last;
reg_valid <= in_valid;
pressure <= 1;
end
end else begin // if (!pressure)
// We can be sure that a flit is waiting now (don't need
// to check)
if (|out_ready) begin
// If the output accepted this flit, go back to
// accepting input flits.
out_flit <= reg_flit;
out_last <= reg_last;
out_valid <= reg_valid;
pressure <= 0;
end
end
end
end
endmodule // noc_router_lookup_slice
|
/* Copyright (c) 2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
*
* This is the output port. It muxes between concurrent input packets
* and buffers them before forwarding to the next router. If virtual
* channels are used, it muxes between the different virtual channels
* in this output port.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module noc_router_output
#(parameter FLIT_WIDTH = 'x,
parameter VCHANNELS = 1,
parameter INPUTS = 1,
parameter BUFFER_DEPTH = 4
)
(
input clk,
input rst,
input [VCHANNELS-1:0][INPUTS-1:0][FLIT_WIDTH-1:0] in_flit,
input [VCHANNELS-1:0][INPUTS-1:0] in_last,
input [VCHANNELS-1:0][INPUTS-1:0] in_valid,
output [VCHANNELS-1:0][INPUTS-1:0] in_ready,
output [FLIT_WIDTH-1:0] out_flit,
output out_last,
output [VCHANNELS-1:0] out_valid,
input [VCHANNELS-1:0] out_ready
);
genvar v;
wire [VCHANNELS-1:0][FLIT_WIDTH-1:0] channel_flit;
wire [VCHANNELS-1:0] channel_last;
wire [VCHANNELS-1:0] channel_valid;
wire [VCHANNELS-1:0] channel_ready;
generate
for (v = 0; v < VCHANNELS; v++) begin
wire [FLIT_WIDTH-1:0] buffer_flit;
wire buffer_last;
wire buffer_valid;
wire buffer_ready;
noc_mux
#(.FLIT_WIDTH (FLIT_WIDTH), .CHANNELS (INPUTS))
u_mux
(.*,
.in_flit (in_flit[v]),
.in_last (in_last[v]),
.in_valid (in_valid[v]),
.in_ready (in_ready[v]),
.out_flit (buffer_flit),
.out_last (buffer_last),
.out_valid (buffer_valid),
.out_ready (buffer_ready));
noc_buffer
#(.FLIT_WIDTH (FLIT_WIDTH), .DEPTH(BUFFER_DEPTH))
u_buffer
(.*,
.in_flit (buffer_flit),
.in_last (buffer_last),
.in_valid (buffer_valid),
.in_ready (buffer_ready),
.out_flit (channel_flit[v]),
.out_last (channel_last[v]),
.out_valid (channel_valid[v]),
.out_ready (channel_ready[v]),
.packet_size ()
);
end // for (v = 0; v < VCHANNELS; v++)
if (VCHANNELS > 1) begin : vc_mux
noc_vchannel_mux
#(.FLIT_WIDTH (FLIT_WIDTH), .CHANNELS(VCHANNELS))
u_mux
(.*,
.in_flit (channel_flit),
.in_last (channel_last),
.in_valid (channel_valid),
.in_ready (channel_ready)
);
end else begin // block: vc_mux
assign out_flit = channel_flit[0];
assign out_last = channel_last[0];
assign out_valid = channel_valid[0];
assign channel_ready[0] = out_ready;
end
endgenerate
endmodule // noc_router_output
|
/* Copyright (c) 2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* Mux virtual channels
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module noc_vchannel_mux
#(parameter FLIT_WIDTH = 32,
parameter CHANNELS = 2)
(
input clk,
input rst,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] in_flit,
input [CHANNELS-1:0] in_last,
input [CHANNELS-1:0] in_valid,
output [CHANNELS-1:0] in_ready,
output reg [FLIT_WIDTH-1:0] out_flit,
output reg out_last,
output [CHANNELS-1:0] out_valid,
input [CHANNELS-1:0] out_ready
);
reg [CHANNELS-1:0] select;
logic [CHANNELS-1:0] nxt_select;
assign out_valid = in_valid & select;
assign in_ready = out_ready & select;
always @(*) begin
out_flit = 'x;
out_last = 'x;
for (int c = 0; c < CHANNELS; c++) begin
if (select[c]) begin
out_flit = in_flit[c];
out_last = in_last[c];
end
end
end
arb_rr
#(.N (CHANNELS))
u_arbiter
(.req (in_valid & out_ready),
.en (1),
.gnt (select),
.nxt_gnt (nxt_select));
always_ff @(posedge clk) begin
if (rst) begin
select <= {{CHANNELS-1{1'b0}},1'b1};
end else begin
select <= nxt_select;
end
end
endmodule // noc_vchannel_mux
|
`include "dbg_config.vh"
module noc_soc_top
(
input clk,
input rst,
output[4 * 32 - 1:0] wb_ext_adr_i,
output[4 * 1 - 1:0] wb_ext_cyc_i,
output[4 * 32 - 1:0] wb_ext_dat_i,
output[4 * 4 - 1:0] wb_ext_sel_i,
output[4 * 1 - 1:0] wb_ext_stb_i,
output[4 * 1 - 1:0] wb_ext_we_i,
output[4 * 1 - 1:0] wb_ext_cab_i,
output[4 * 3 - 1:0] wb_ext_cti_i,
output[4 * 2 - 1:0] wb_ext_bte_i,
input[4 * 1 - 1:0] wb_ext_ack_o,
input[4 * 1 - 1:0] wb_ext_rty_o,
input[4 * 1 - 1:0] wb_ext_err_o,
input[4 * 32 - 1:0] wb_ext_dat_o
);
import dii_package::*;
import optimsoc_config:: *;
import optimsoc_functions:: *;
parameter config_t CONFIG = 'x;
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH;
localparam CHANNELS = CONFIG.NOC_CHANNELS;
localparam VCHANNELS = 2;
wire [3:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_in_flit_R_1_EP;
wire [3:0][CHANNELS-1:0]noc_in_last_R_1_EP;
wire [3:0][CHANNELS-1:0]noc_in_valid_R_1_EP;
wire [3:0][CHANNELS-1:0]noc_out_ready_R_1_EP;
wire [3:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_out_flit_R_1_EP;
wire [3:0][CHANNELS-1:0]noc_out_last_R_1_EP;
wire [3:0][CHANNELS-1:0]noc_out_valid_R_1_EP;
wire [3:0][CHANNELS-1:0]noc_in_ready_R_1_EP;
tile_picorv32_top
#(
.CONFIG(CONFIG)
)
tile_picorv32_top_inst(
.clk (clk),
.rst_sys (rst),
.noc_in_flit (noc_in_flit_R_1_EP[3]),
.noc_in_last (noc_in_last_R_1_EP[3]),
.noc_in_valid (noc_in_valid_R_1_EP[3]),
.noc_out_ready (noc_out_ready_R_1_EP[3]),
.noc_in_ready (noc_in_ready_R_1_EP[3]),
.noc_out_flit (noc_out_flit_R_1_EP[3]),
.noc_out_last (noc_out_last_R_1_EP[3]),
.noc_out_valid (noc_out_valid_R_1_EP[3]));
tile_dft_top_top
#(
.CONFIG(CONFIG)
)
tile_dft_top_top_inst(
.clk (clk),
.rst_sys (rst),
.noc_in_flit (noc_in_flit_R_1_EP[2]),
.noc_in_last (noc_in_last_R_1_EP[2]),
.noc_in_valid (noc_in_valid_R_1_EP[2]),
.noc_out_ready (noc_out_ready_R_1_EP[2]),
.noc_in_ready (noc_in_ready_R_1_EP[2]),
.noc_out_flit (noc_out_flit_R_1_EP[2]),
.noc_out_last (noc_out_last_R_1_EP[2]),
.noc_out_valid (noc_out_valid_R_1_EP[2]));
tile_idft_top_top
#(
.CONFIG(CONFIG)
)
tile_idft_top_top_inst(
.clk (clk),
.rst_sys (rst),
.noc_in_flit (noc_in_flit_R_1_EP[1]),
.noc_in_last (noc_in_last_R_1_EP[1]),
.noc_in_valid (noc_in_valid_R_1_EP[1]),
.noc_out_ready (noc_out_ready_R_1_EP[1]),
.noc_in_ready (noc_in_ready_R_1_EP[1]),
.noc_out_flit (noc_out_flit_R_1_EP[1]),
.noc_out_last (noc_out_last_R_1_EP[1]),
.noc_out_valid (noc_out_valid_R_1_EP[1]));
tile_fir_top
#(
.CONFIG(CONFIG)
)
tile_fir_top_inst(
.clk (clk),
.rst_sys (rst),
.noc_in_flit (noc_in_flit_R_1_EP[0]),
.noc_in_last (noc_in_last_R_1_EP[0]),
.noc_in_valid (noc_in_valid_R_1_EP[0]),
.noc_out_ready (noc_out_ready_R_1_EP[0]),
.noc_in_ready (noc_in_ready_R_1_EP[0]),
.noc_out_flit (noc_out_flit_R_1_EP[0]),
.noc_out_last (noc_out_last_R_1_EP[0]),
.noc_out_valid (noc_out_valid_R_1_EP[0]));
wire [FLIT_WIDTH-1:0]in_flit_R_1_2;
wire in_last_R_1_2;
wire [VCHANNELS-1:0]in_valid_R_1_2;
wire [VCHANNELS-1:0]out_ready_R_1_2;
wire [VCHANNELS-1:0]in_ready_R_1_2;
wire [FLIT_WIDTH-1:0]out_flit_R_1_2;
wire out_last_R_1_2;
wire [VCHANNELS-1:0]out_valid_R_1_2;
noc_router
#(
.INPUTS (9),
.OUTPUTS (9),
.DESTS (32)
)
noc_router_R_1_inst(
.clk (clk),
.rst (rst),
.in_flit ({noc_out_flit_R_1_EP[3],noc_out_flit_R_1_EP[2],noc_out_flit_R_1_EP[1],noc_out_flit_R_1_EP[0],in_flit_R_1_2}),
.in_last ({noc_out_last_R_1_EP[3],noc_out_last_R_1_EP[2],noc_out_last_R_1_EP[1],noc_out_last_R_1_EP[0],in_last_R_1_2}),
.in_valid ({noc_out_valid_R_1_EP[3],noc_out_valid_R_1_EP[2],noc_out_valid_R_1_EP[1],noc_out_valid_R_1_EP[0],in_valid_R_1_2}),
.out_ready ({noc_in_ready_R_1_EP[3],noc_in_ready_R_1_EP[2],noc_in_ready_R_1_EP[1],noc_in_ready_R_1_EP[0],out_ready_R_1_2}),
.out_flit ({noc_in_flit_R_1_EP[3],noc_in_flit_R_1_EP[2],noc_in_flit_R_1_EP[1],noc_in_flit_R_1_EP[0],out_flit_R_1_2}),
.out_last ({noc_in_last_R_1_EP[3],noc_in_last_R_1_EP[2],noc_in_last_R_1_EP[1],noc_in_last_R_1_EP[0],out_last_R_1_2}),
.out_valid ({noc_in_valid_R_1_EP[3],noc_in_valid_R_1_EP[2],noc_in_valid_R_1_EP[1],noc_in_valid_R_1_EP[0],out_valid_R_1_2}),
.in_ready ({noc_out_ready_R_1_EP[3],noc_out_ready_R_1_EP[2],noc_out_ready_R_1_EP[1],noc_out_ready_R_1_EP[0],in_ready_R_1_2}));
wire [1:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_in_flit_R_2_EP;
wire [1:0][CHANNELS-1:0]noc_in_last_R_2_EP;
wire [1:0][CHANNELS-1:0]noc_in_valid_R_2_EP;
wire [1:0][CHANNELS-1:0]noc_out_ready_R_2_EP;
wire [1:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_out_flit_R_2_EP;
wire [1:0][CHANNELS-1:0]noc_out_last_R_2_EP;
wire [1:0][CHANNELS-1:0]noc_out_valid_R_2_EP;
wire [1:0][CHANNELS-1:0]noc_in_ready_R_2_EP;
tile_ram_wb_02
#(
.CONFIG(CONFIG)
)
tile_ram_wb_02_inst(
.clk (clk),
.rst_sys (rst),
.noc_in_flit (noc_in_flit_R_2_EP[1]),
.noc_in_last (noc_in_last_R_2_EP[1]),
.noc_in_valid (noc_in_valid_R_2_EP[1]),
.noc_out_ready (noc_out_ready_R_2_EP[1]),
.noc_in_ready (noc_in_ready_R_2_EP[1]),
.noc_out_flit (noc_out_flit_R_2_EP[1]),
.noc_out_last (noc_out_last_R_2_EP[1]),
.noc_out_valid (noc_out_valid_R_2_EP[1]));
tile_ram_wb_01
#(
.CONFIG(CONFIG)
)
tile_ram_wb_01_inst(
.clk (clk),
.rst_sys (rst),
.noc_in_flit (noc_in_flit_R_2_EP[0]),
.noc_in_last (noc_in_last_R_2_EP[0]),
.noc_in_valid (noc_in_valid_R_2_EP[0]),
.noc_out_ready (noc_out_ready_R_2_EP[0]),
.noc_in_ready (noc_in_ready_R_2_EP[0]),
.noc_out_flit (noc_out_flit_R_2_EP[0]),
.noc_out_last (noc_out_last_R_2_EP[0]),
.noc_out_valid (noc_out_valid_R_2_EP[0]));
wire [FLIT_WIDTH-1:0]in_flit_R_2_3;
wire in_last_R_2_3;
wire [VCHANNELS-1:0]in_valid_R_2_3;
wire [VCHANNELS-1:0]out_ready_R_2_3;
wire [VCHANNELS-1:0]in_ready_R_2_3;
wire [FLIT_WIDTH-1:0]out_flit_R_2_3;
wire out_last_R_2_3;
wire [VCHANNELS-1:0]out_valid_R_2_3;
noc_router
#(
.INPUTS (6),
.OUTPUTS (6),
.DESTS (32)
)
noc_router_R_2_inst(
.clk (clk),
.rst (rst),
.in_flit ({noc_out_flit_R_2_EP[1],noc_out_flit_R_2_EP[0],out_flit_R_1_2,in_flit_R_2_3}),
.in_last ({noc_out_last_R_2_EP[1],noc_out_last_R_2_EP[0],out_last_R_1_2,in_last_R_2_3}),
.in_valid ({noc_out_valid_R_2_EP[1],noc_out_valid_R_2_EP[0],out_valid_R_1_2,in_valid_R_2_3}),
.out_ready ({noc_in_ready_R_2_EP[1],noc_in_ready_R_2_EP[0],in_ready_R_1_2,out_ready_R_2_3}),
.out_flit ({noc_in_flit_R_2_EP[1],noc_in_flit_R_2_EP[0],in_flit_R_1_2,out_flit_R_2_3}),
.out_last ({noc_in_last_R_2_EP[1],noc_in_last_R_2_EP[0],in_last_R_1_2,out_last_R_2_3}),
.out_valid ({noc_in_valid_R_2_EP[1],noc_in_valid_R_2_EP[0],in_valid_R_1_2,out_valid_R_2_3}),
.in_ready ({noc_out_ready_R_2_EP[1],noc_out_ready_R_2_EP[0],out_ready_R_1_2,in_ready_R_2_3}));
wire [0:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_in_flit_R_3_EP;
wire [0:0][CHANNELS-1:0]noc_in_last_R_3_EP;
wire [0:0][CHANNELS-1:0]noc_in_valid_R_3_EP;
wire [0:0][CHANNELS-1:0]noc_out_ready_R_3_EP;
wire [0:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_out_flit_R_3_EP;
wire [0:0][CHANNELS-1:0]noc_out_last_R_3_EP;
wire [0:0][CHANNELS-1:0]noc_out_valid_R_3_EP;
wire [0:0][CHANNELS-1:0]noc_in_ready_R_3_EP;
tile_md5_top
#(
.CONFIG(CONFIG)
)
tile_md5_top_inst(
.clk (clk),
.rst_sys (rst),
.noc_in_flit (noc_in_flit_R_3_EP[0]),
.noc_in_last (noc_in_last_R_3_EP[0]),
.noc_in_valid (noc_in_valid_R_3_EP[0]),
.noc_out_ready (noc_out_ready_R_3_EP[0]),
.noc_in_ready (noc_in_ready_R_3_EP[0]),
.noc_out_flit (noc_out_flit_R_3_EP[0]),
.noc_out_last (noc_out_last_R_3_EP[0]),
.noc_out_valid (noc_out_valid_R_3_EP[0]));
wire [FLIT_WIDTH-1:0]in_flit_R_3_4;
wire in_last_R_3_4;
wire [VCHANNELS-1:0]in_valid_R_3_4;
wire [VCHANNELS-1:0]out_ready_R_3_4;
wire [VCHANNELS-1:0]in_ready_R_3_4;
wire [FLIT_WIDTH-1:0]out_flit_R_3_4;
wire out_last_R_3_4;
wire [VCHANNELS-1:0]out_valid_R_3_4;
wire [FLIT_WIDTH-1:0]in_flit_R_3_5;
wire in_last_R_3_5;
wire [VCHANNELS-1:0]in_valid_R_3_5;
wire [VCHANNELS-1:0]out_ready_R_3_5;
wire [VCHANNELS-1:0]in_ready_R_3_5;
wire [FLIT_WIDTH-1:0]out_flit_R_3_5;
wire out_last_R_3_5;
wire [VCHANNELS-1:0]out_valid_R_3_5;
noc_router
#(
.INPUTS (5),
.OUTPUTS (5),
.DESTS (32)
)
noc_router_R_3_inst(
.clk (clk),
.rst (rst),
.in_flit ({noc_out_flit_R_3_EP[0],out_flit_R_2_3,in_flit_R_3_4,in_flit_R_3_5}),
.in_last ({noc_out_last_R_3_EP[0],out_last_R_2_3,in_last_R_3_4,in_last_R_3_5}),
.in_valid ({noc_out_valid_R_3_EP[0],out_valid_R_2_3,in_valid_R_3_4,in_valid_R_3_5}),
.out_ready ({noc_in_ready_R_3_EP[0],in_ready_R_2_3,out_ready_R_3_4,out_ready_R_3_5}),
.out_flit ({noc_in_flit_R_3_EP[0],in_flit_R_2_3,out_flit_R_3_4,out_flit_R_3_5}),
.out_last ({noc_in_last_R_3_EP[0],in_last_R_2_3,out_last_R_3_4,out_last_R_3_5}),
.out_valid ({noc_in_valid_R_3_EP[0],in_valid_R_2_3,out_valid_R_3_4,out_valid_R_3_5}),
.in_ready ({noc_out_ready_R_3_EP[0],out_ready_R_2_3,in_ready_R_3_4,in_ready_R_3_5}));
wire [1:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_in_flit_R_4_EP;
wire [1:0][CHANNELS-1:0]noc_in_last_R_4_EP;
wire [1:0][CHANNELS-1:0]noc_in_valid_R_4_EP;
wire [1:0][CHANNELS-1:0]noc_out_ready_R_4_EP;
wire [1:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_out_flit_R_4_EP;
wire [1:0][CHANNELS-1:0]noc_out_last_R_4_EP;
wire [1:0][CHANNELS-1:0]noc_out_valid_R_4_EP;
wire [1:0][CHANNELS-1:0]noc_in_ready_R_4_EP;
tile_aes_top
#(
.CONFIG(CONFIG)
)
tile_aes_top_inst(
.clk (clk),
.rst_sys (rst),
.noc_in_flit (noc_in_flit_R_4_EP[1]),
.noc_in_last (noc_in_last_R_4_EP[1]),
.noc_in_valid (noc_in_valid_R_4_EP[1]),
.noc_out_ready (noc_out_ready_R_4_EP[1]),
.noc_in_ready (noc_in_ready_R_4_EP[1]),
.noc_out_flit (noc_out_flit_R_4_EP[1]),
.noc_out_last (noc_out_last_R_4_EP[1]),
.noc_out_valid (noc_out_valid_R_4_EP[1]));
tile_des3_top
#(
.CONFIG(CONFIG)
)
tile_des3_top_inst(
.clk (clk),
.rst_sys (rst),
.noc_in_flit (noc_in_flit_R_4_EP[0]),
.noc_in_last (noc_in_last_R_4_EP[0]),
.noc_in_valid (noc_in_valid_R_4_EP[0]),
.noc_out_ready (noc_out_ready_R_4_EP[0]),
.noc_in_ready (noc_in_ready_R_4_EP[0]),
.noc_out_flit (noc_out_flit_R_4_EP[0]),
.noc_out_last (noc_out_last_R_4_EP[0]),
.noc_out_valid (noc_out_valid_R_4_EP[0]));
noc_router
#(
.INPUTS (5),
.OUTPUTS (5),
.DESTS (32)
)
noc_router_R_4_inst(
.clk (clk),
.rst (rst),
.in_flit ({noc_out_flit_R_4_EP[1],noc_out_flit_R_4_EP[0],out_flit_R_3_4}),
.in_last ({noc_out_last_R_4_EP[1],noc_out_last_R_4_EP[0],out_last_R_3_4}),
.in_valid ({noc_out_valid_R_4_EP[1],noc_out_valid_R_4_EP[0],out_valid_R_3_4}),
.out_ready ({noc_in_ready_R_4_EP[1],noc_in_ready_R_4_EP[0],in_ready_R_3_4}),
.out_flit ({noc_in_flit_R_4_EP[1],noc_in_flit_R_4_EP[0],in_flit_R_3_4}),
.out_last ({noc_in_last_R_4_EP[1],noc_in_last_R_4_EP[0],in_last_R_3_4}),
.out_valid ({noc_in_valid_R_4_EP[1],noc_in_valid_R_4_EP[0],in_valid_R_3_4}),
.in_ready ({noc_out_ready_R_4_EP[1],noc_out_ready_R_4_EP[0],out_ready_R_3_4}));
wire [0:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_in_flit_R_5_EP;
wire [0:0][CHANNELS-1:0]noc_in_last_R_5_EP;
wire [0:0][CHANNELS-1:0]noc_in_valid_R_5_EP;
wire [0:0][CHANNELS-1:0]noc_out_ready_R_5_EP;
wire [0:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_out_flit_R_5_EP;
wire [0:0][CHANNELS-1:0]noc_out_last_R_5_EP;
wire [0:0][CHANNELS-1:0]noc_out_valid_R_5_EP;
wire [0:0][CHANNELS-1:0]noc_in_ready_R_5_EP;
tile_uart_top
#(
.CONFIG(CONFIG)
)
tile_uart_top_inst(
.clk (clk),
.rst_sys (rst),
.noc_in_flit (noc_in_flit_R_5_EP[0]),
.noc_in_last (noc_in_last_R_5_EP[0]),
.noc_in_valid (noc_in_valid_R_5_EP[0]),
.noc_out_ready (noc_out_ready_R_5_EP[0]),
.noc_in_ready (noc_in_ready_R_5_EP[0]),
.noc_out_flit (noc_out_flit_R_5_EP[0]),
.noc_out_last (noc_out_last_R_5_EP[0]),
.noc_out_valid (noc_out_valid_R_5_EP[0]));
noc_router
#(
.INPUTS (3),
.OUTPUTS (3),
.DESTS (32)
)
noc_router_R_5_inst(
.clk (clk),
.rst (rst),
.in_flit ({noc_out_flit_R_5_EP[0],out_flit_R_3_5}),
.in_last ({noc_out_last_R_5_EP[0],out_last_R_3_5}),
.in_valid ({noc_out_valid_R_5_EP[0],out_valid_R_3_5}),
.out_ready ({noc_in_ready_R_5_EP[0],in_ready_R_3_5}),
.out_flit ({noc_in_flit_R_5_EP[0],in_flit_R_3_5}),
.out_last ({noc_in_last_R_5_EP[0],in_last_R_3_5}),
.out_valid ({noc_in_valid_R_5_EP[0],in_valid_R_3_5}),
.in_ready ({noc_out_ready_R_5_EP[0],out_ready_R_3_5}));
endmodule
|
/* Copyright (c) 2012-2016 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
*
*/
`include "dbg_config.vh"
module tb_system(
`ifdef verilator
input clk,
input rst
`endif
);
import dii_package::dii_flit;
import opensocdebug::mor1kx_trace_exec;
import optimsoc_config::*;
import optimsoc_functions::*;
parameter USE_DEBUG = 0;
parameter ENABLE_VCHANNELS = 1*1;
parameter integer NUM_CORES = 'x; // bug in verilator would give a warning
parameter integer LMEM_SIZE = 'x;
localparam base_config_t
BASE_CONFIG = '{ NUMTILES: 'x,
NUMCTS: 'x,
CTLIST:'x,
CORES_PER_TILE: 'x,
GMEM_SIZE: 0,
GMEM_TILE: 'x,
NOC_ENABLE_VCHANNELS: ENABLE_VCHANNELS,
LMEM_SIZE: LMEM_SIZE,
LMEM_STYLE: PLAIN,
ENABLE_BOOTROM: 0,
BOOTROM_SIZE: 0,
ENABLE_DM: 0,
DM_BASE: 32'h0,
DM_SIZE: LMEM_SIZE,
ENABLE_PGAS: 0,
PGAS_BASE: 0,
PGAS_SIZE: 0,
NA_ENABLE_MPSIMPLE: 1,
NA_ENABLE_DMA: 1,
NA_DMA_GENIRQ: 1,
NA_DMA_ENTRIES: 4,
USE_DEBUG: 1'(USE_DEBUG),
DEBUG_STM: 1,
DEBUG_CTM: 1,
DEBUG_SUBNET_BITS: 6,
DEBUG_LOCAL_SUBNET: 0,
DEBUG_ROUTER_BUFFER_SIZE: 4,
DEBUG_MAX_PKT_LEN: 8
};
localparam config_t CONFIG = derive_config(BASE_CONFIG);
// In Verilator, we feed clk and rst from the C++ toplevel, in ModelSim & Co.
// these signals are generated inside this testbench.
`ifndef verilator
reg clk;
reg rst;
`endif
noc_soc_top
#(.CONFIG(CONFIG))
u_system
(.clk (clk),
.rst (rst),
//.c_glip_in (c_glip_in),
// .c_glip_out (c_glip_out),
.wb_ext_ack_o (4'hx),
.wb_ext_err_o (4'hx),
.wb_ext_rty_o (4'hx),
.wb_ext_dat_o (128'hx),
.wb_ext_adr_i (),
.wb_ext_cyc_i (),
.wb_ext_dat_i (),
.wb_ext_sel_i (),
.wb_ext_stb_i (),
.wb_ext_we_i (),
.wb_ext_cab_i (),
.wb_ext_cti_i (),
.wb_ext_bte_i ()
);
// Generate testbench signals.
// In Verilator, these signals are generated in the C++ toplevel testbench
`ifndef verilator
initial begin
clk = 1'b1;
rst = 1'b1;
#15;
rst = 1'b0;
end
//always clk = #1.25 ~clk;
`endif
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../../src/rtl/*/verilog")
// verilog-auto-inst-param-value: t
// End:
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module tile_aes_top
import dii_package::*;
import optimsoc_functions::*;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH,
/* User parameters */
// Set the number of masters and slaves
parameter MASTERS = 0,
parameter SLAVES = 1,
// Set bus address and data width in bits
// DATA_WIDTH must be a multiple of 8 (full bytes)!
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32,
// Memory range definitions, see above
// The number of parameters actually limits the number of slaves as
// there is no generic way that is handled by all tools to define
// variable width parameter arrays.
parameter S0_ENABLE = 1,
parameter S0_RANGE_WIDTH = 1,
parameter S0_RANGE_MATCH = 1'b0,
parameter S1_ENABLE = 0,
parameter S1_RANGE_WIDTH = 1,
parameter S1_RANGE_MATCH = 1'b0,
parameter S2_ENABLE = 0,
parameter S2_RANGE_WIDTH = 1,
parameter S2_RANGE_MATCH = 1'b0,
parameter S3_ENABLE = 0,
parameter S3_RANGE_WIDTH = 1,
parameter S3_RANGE_MATCH = 1'b0,
parameter S4_ENABLE = 0,
parameter S4_RANGE_WIDTH = 1,
parameter S4_RANGE_MATCH = 1'b0,
parameter S5_ENABLE = 0,
parameter S5_RANGE_WIDTH = 1,
parameter S5_RANGE_MATCH = 1'b0,
parameter S6_ENABLE = 0,
parameter S6_RANGE_WIDTH = 1,
parameter S6_RANGE_MATCH = 1'b0,
parameter S7_ENABLE = 0,
parameter S7_RANGE_WIDTH = 1,
parameter S7_RANGE_MATCH = 1'b0,
parameter S8_ENABLE = 0,
parameter S8_RANGE_WIDTH = 1,
parameter S8_RANGE_MATCH = 1'b0,
parameter S9_ENABLE = 0,
parameter S9_RANGE_WIDTH = 1,
parameter S9_RANGE_MATCH = 1'b0,
/* Derived local parameters */
// Width of byte select registers
localparam SEL_WIDTH = DATA_WIDTH >> 3
)
(
input clk,
input rst_sys,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
localparam NR_MASTERS = 0;
localparam NR_SLAVES = 10;
localparam S0 = 0;
localparam S1 = 1;
localparam S2 = 2;
localparam S3 = 3;
localparam S4 = 4;
localparam S5 = 5;
localparam S6 = 6;
localparam S7 = 7;
localparam S8 = 8;
localparam S9 = 9;
/* localparam SLAVE_NA = S0;
localparam SLAVE_AES = S1;
localparam SLAVE_DES3 = S2;
localparam SLAVE_SHA256 = S3;
localparam SLAVE_MD5 = S4;
localparam SLAVE_DFT = S5;
localparam SLAVE_FIR = S6;
localparam SLAVE_IDFT = S7;
localparam SLAVE_WBRAM = S8;
localparam SLAVE_UART = S9; */
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
genvar c, m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
# (
.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(S0_ENABLE),
.S0_RANGE_WIDTH(S0_RANGE_WIDTH),.S0_RANGE_MATCH(S0_RANGE_MATCH),
.S1_ENABLE(S1_ENABLE),
.S1_RANGE_WIDTH(S1_RANGE_WIDTH),.S1_RANGE_MATCH(S1_RANGE_MATCH),
.S2_ENABLE(S2_ENABLE),
.S2_RANGE_WIDTH(S2_RANGE_WIDTH),.S2_RANGE_MATCH(S2_RANGE_MATCH),
.S3_ENABLE(S3_ENABLE),
.S3_RANGE_WIDTH(S3_RANGE_WIDTH),.S3_RANGE_MATCH(S3_RANGE_MATCH),
.S4_ENABLE(S4_ENABLE),
.S4_RANGE_WIDTH(S4_RANGE_WIDTH),.S4_RANGE_MATCH(S4_RANGE_MATCH),
.S5_ENABLE(S5_ENABLE),
.S5_RANGE_WIDTH(S5_RANGE_WIDTH),.S5_RANGE_MATCH(S5_RANGE_MATCH),
.S6_ENABLE(S6_ENABLE),
.S6_RANGE_WIDTH(S6_RANGE_WIDTH),.S6_RANGE_MATCH(S6_RANGE_MATCH),
.S7_ENABLE(S7_ENABLE),
.S7_RANGE_WIDTH(S7_RANGE_WIDTH),.S7_RANGE_MATCH(S7_RANGE_MATCH),
.S8_ENABLE(S8_ENABLE),
.S8_RANGE_WIDTH(S8_RANGE_WIDTH),.S8_RANGE_MATCH(S8_RANGE_MATCH),
.S9_ENABLE(S9_ENABLE),
.S9_RANGE_WIDTH(S9_RANGE_WIDTH),.S9_RANGE_MATCH(S9_RANGE_MATCH)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
networkadapter_ct
#(.CONFIG(CONFIG)
)
aes_top_na(
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[S0]),
.wbs_rty_o (bussl_rty_o[S0]),
.wbs_err_o (bussl_err_o[S0]),
.wbs_dat_o (bussl_dat_o[S0]),
.irq (),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[S0]),
.wbs_cyc_i (bussl_cyc_i[S0]),
.wbs_dat_i (bussl_dat_i[S0]),
.wbs_sel_i (bussl_sel_i[S0]),
.wbs_stb_i (bussl_stb_i[S0]),
.wbs_we_i (bussl_we_i[S0]),
.wbs_cab_i (bussl_cab_i[S0]),
.wbs_cti_i (bussl_cti_i[S0]),
.wbs_bte_i (bussl_bte_i[S0]));
aes_top aes_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i(bussl_adr_i[S1]),
.wb_cyc_i(bussl_cyc_i[S1]),
.wb_dat_i(bussl_dat_i[S1]),
.wb_sel_i(bussl_sel_i[S1]),
.wb_stb_i(bussl_stb_i[S1]),
.wb_we_i(bussl_we_i[S1]),
.wb_ack_o(bussl_ack_o[S1]),
.wb_dat_o(bussl_rty_o[S1]),
.wb_err_o(bussl_err_o[S1])
);
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module tile_des3_top
import dii_package::*;
import optimsoc_functions::*;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH,
/* User parameters */
// Set the number of masters and slaves
parameter MASTERS = 0,
parameter SLAVES = 1,
// Set bus address and data width in bits
// DATA_WIDTH must be a multiple of 8 (full bytes)!
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32,
// Memory range definitions, see above
// The number of parameters actually limits the number of slaves as
// there is no generic way that is handled by all tools to define
// variable width parameter arrays.
parameter S0_ENABLE = 1,
parameter S0_RANGE_WIDTH = 1,
parameter S0_RANGE_MATCH = 1'b0,
parameter S1_ENABLE = 0,
parameter S1_RANGE_WIDTH = 1,
parameter S1_RANGE_MATCH = 1'b0,
parameter S2_ENABLE = 0,
parameter S2_RANGE_WIDTH = 1,
parameter S2_RANGE_MATCH = 1'b0,
parameter S3_ENABLE = 0,
parameter S3_RANGE_WIDTH = 1,
parameter S3_RANGE_MATCH = 1'b0,
parameter S4_ENABLE = 0,
parameter S4_RANGE_WIDTH = 1,
parameter S4_RANGE_MATCH = 1'b0,
parameter S5_ENABLE = 0,
parameter S5_RANGE_WIDTH = 1,
parameter S5_RANGE_MATCH = 1'b0,
parameter S6_ENABLE = 0,
parameter S6_RANGE_WIDTH = 1,
parameter S6_RANGE_MATCH = 1'b0,
parameter S7_ENABLE = 0,
parameter S7_RANGE_WIDTH = 1,
parameter S7_RANGE_MATCH = 1'b0,
parameter S8_ENABLE = 0,
parameter S8_RANGE_WIDTH = 1,
parameter S8_RANGE_MATCH = 1'b0,
parameter S9_ENABLE = 0,
parameter S9_RANGE_WIDTH = 1,
parameter S9_RANGE_MATCH = 1'b0,
/* Derived local parameters */
// Width of byte select registers
localparam SEL_WIDTH = DATA_WIDTH >> 3
)
(
input clk,
input rst_sys,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
localparam NR_MASTERS = 0;
localparam NR_SLAVES = 10;
localparam S0 = 0;
localparam S1 = 1;
localparam S2 = 2;
localparam S3 = 3;
localparam S4 = 4;
localparam S5 = 5;
localparam S6 = 6;
localparam S7 = 7;
localparam S8 = 8;
localparam S9 = 9;
/* localparam SLAVE_NA = S0;
localparam SLAVE_AES = S1;
localparam SLAVE_DES3 = S2;
localparam SLAVE_SHA256 = S3;
localparam SLAVE_MD5 = S4;
localparam SLAVE_DFT = S5;
localparam SLAVE_FIR = S6;
localparam SLAVE_IDFT = S7;
localparam SLAVE_WBRAM = S8;
localparam SLAVE_UART = S9; */
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
genvar c, m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
# (
.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(S0_ENABLE),
.S0_RANGE_WIDTH(S0_RANGE_WIDTH),.S0_RANGE_MATCH(S0_RANGE_MATCH),
.S1_ENABLE(S1_ENABLE),
.S1_RANGE_WIDTH(S1_RANGE_WIDTH),.S1_RANGE_MATCH(S1_RANGE_MATCH),
.S2_ENABLE(S2_ENABLE),
.S2_RANGE_WIDTH(S2_RANGE_WIDTH),.S2_RANGE_MATCH(S2_RANGE_MATCH),
.S3_ENABLE(S3_ENABLE),
.S3_RANGE_WIDTH(S3_RANGE_WIDTH),.S3_RANGE_MATCH(S3_RANGE_MATCH),
.S4_ENABLE(S4_ENABLE),
.S4_RANGE_WIDTH(S4_RANGE_WIDTH),.S4_RANGE_MATCH(S4_RANGE_MATCH),
.S5_ENABLE(S5_ENABLE),
.S5_RANGE_WIDTH(S5_RANGE_WIDTH),.S5_RANGE_MATCH(S5_RANGE_MATCH),
.S6_ENABLE(S6_ENABLE),
.S6_RANGE_WIDTH(S6_RANGE_WIDTH),.S6_RANGE_MATCH(S6_RANGE_MATCH),
.S7_ENABLE(S7_ENABLE),
.S7_RANGE_WIDTH(S7_RANGE_WIDTH),.S7_RANGE_MATCH(S7_RANGE_MATCH),
.S8_ENABLE(S8_ENABLE),
.S8_RANGE_WIDTH(S8_RANGE_WIDTH),.S8_RANGE_MATCH(S8_RANGE_MATCH),
.S9_ENABLE(S9_ENABLE),
.S9_RANGE_WIDTH(S9_RANGE_WIDTH),.S9_RANGE_MATCH(S9_RANGE_MATCH)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
networkadapter_ct
#(.CONFIG(CONFIG)
)
des3_top_na(
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[S0]),
.wbs_rty_o (bussl_rty_o[S0]),
.wbs_err_o (bussl_err_o[S0]),
.wbs_dat_o (bussl_dat_o[S0]),
.irq (),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[S0]),
.wbs_cyc_i (bussl_cyc_i[S0]),
.wbs_dat_i (bussl_dat_i[S0]),
.wbs_sel_i (bussl_sel_i[S0]),
.wbs_stb_i (bussl_stb_i[S0]),
.wbs_we_i (bussl_we_i[S0]),
.wbs_cab_i (bussl_cab_i[S0]),
.wbs_cti_i (bussl_cti_i[S0]),
.wbs_bte_i (bussl_bte_i[S0]));
des3_top des3_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i(bussl_adr_i[S1]),
.wb_cyc_i(bussl_cyc_i[S1]),
.wb_dat_i(bussl_dat_i[S1]),
.wb_sel_i(bussl_sel_i[S1]),
.wb_stb_i(bussl_stb_i[S1]),
.wb_we_i(bussl_we_i[S1]),
.wb_ack_o(bussl_ack_o[S1]),
.wb_dat_o(bussl_rty_o[S1]),
.wb_err_o(bussl_err_o[S1])
);
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module tile_dft_top_top
import dii_package::*;
import optimsoc_functions::*;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH,
/* User parameters */
// Set the number of masters and slaves
parameter MASTERS = 0,
parameter SLAVES = 1,
// Set bus address and data width in bits
// DATA_WIDTH must be a multiple of 8 (full bytes)!
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32,
// Memory range definitions, see above
// The number of parameters actually limits the number of slaves as
// there is no generic way that is handled by all tools to define
// variable width parameter arrays.
parameter S0_ENABLE = 1,
parameter S0_RANGE_WIDTH = 1,
parameter S0_RANGE_MATCH = 1'b0,
parameter S1_ENABLE = 0,
parameter S1_RANGE_WIDTH = 1,
parameter S1_RANGE_MATCH = 1'b0,
parameter S2_ENABLE = 0,
parameter S2_RANGE_WIDTH = 1,
parameter S2_RANGE_MATCH = 1'b0,
parameter S3_ENABLE = 0,
parameter S3_RANGE_WIDTH = 1,
parameter S3_RANGE_MATCH = 1'b0,
parameter S4_ENABLE = 0,
parameter S4_RANGE_WIDTH = 1,
parameter S4_RANGE_MATCH = 1'b0,
parameter S5_ENABLE = 0,
parameter S5_RANGE_WIDTH = 1,
parameter S5_RANGE_MATCH = 1'b0,
parameter S6_ENABLE = 0,
parameter S6_RANGE_WIDTH = 1,
parameter S6_RANGE_MATCH = 1'b0,
parameter S7_ENABLE = 0,
parameter S7_RANGE_WIDTH = 1,
parameter S7_RANGE_MATCH = 1'b0,
parameter S8_ENABLE = 0,
parameter S8_RANGE_WIDTH = 1,
parameter S8_RANGE_MATCH = 1'b0,
parameter S9_ENABLE = 0,
parameter S9_RANGE_WIDTH = 1,
parameter S9_RANGE_MATCH = 1'b0,
/* Derived local parameters */
// Width of byte select registers
localparam SEL_WIDTH = DATA_WIDTH >> 3
)
(
input clk,
input rst_sys,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
localparam NR_MASTERS = 0;
localparam NR_SLAVES = 10;
localparam S0 = 0;
localparam S1 = 1;
localparam S2 = 2;
localparam S3 = 3;
localparam S4 = 4;
localparam S5 = 5;
localparam S6 = 6;
localparam S7 = 7;
localparam S8 = 8;
localparam S9 = 9;
/* localparam SLAVE_NA = S0;
localparam SLAVE_AES = S1;
localparam SLAVE_DES3 = S2;
localparam SLAVE_SHA256 = S3;
localparam SLAVE_MD5 = S4;
localparam SLAVE_DFT = S5;
localparam SLAVE_FIR = S6;
localparam SLAVE_IDFT = S7;
localparam SLAVE_WBRAM = S8;
localparam SLAVE_UART = S9; */
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
genvar c, m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
# (
.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(S0_ENABLE),
.S0_RANGE_WIDTH(S0_RANGE_WIDTH),.S0_RANGE_MATCH(S0_RANGE_MATCH),
.S1_ENABLE(S1_ENABLE),
.S1_RANGE_WIDTH(S1_RANGE_WIDTH),.S1_RANGE_MATCH(S1_RANGE_MATCH),
.S2_ENABLE(S2_ENABLE),
.S2_RANGE_WIDTH(S2_RANGE_WIDTH),.S2_RANGE_MATCH(S2_RANGE_MATCH),
.S3_ENABLE(S3_ENABLE),
.S3_RANGE_WIDTH(S3_RANGE_WIDTH),.S3_RANGE_MATCH(S3_RANGE_MATCH),
.S4_ENABLE(S4_ENABLE),
.S4_RANGE_WIDTH(S4_RANGE_WIDTH),.S4_RANGE_MATCH(S4_RANGE_MATCH),
.S5_ENABLE(S5_ENABLE),
.S5_RANGE_WIDTH(S5_RANGE_WIDTH),.S5_RANGE_MATCH(S5_RANGE_MATCH),
.S6_ENABLE(S6_ENABLE),
.S6_RANGE_WIDTH(S6_RANGE_WIDTH),.S6_RANGE_MATCH(S6_RANGE_MATCH),
.S7_ENABLE(S7_ENABLE),
.S7_RANGE_WIDTH(S7_RANGE_WIDTH),.S7_RANGE_MATCH(S7_RANGE_MATCH),
.S8_ENABLE(S8_ENABLE),
.S8_RANGE_WIDTH(S8_RANGE_WIDTH),.S8_RANGE_MATCH(S8_RANGE_MATCH),
.S9_ENABLE(S9_ENABLE),
.S9_RANGE_WIDTH(S9_RANGE_WIDTH),.S9_RANGE_MATCH(S9_RANGE_MATCH)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
networkadapter_ct
#(.CONFIG(CONFIG)
)
dft_top_top_na(
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[S0]),
.wbs_rty_o (bussl_rty_o[S0]),
.wbs_err_o (bussl_err_o[S0]),
.wbs_dat_o (bussl_dat_o[S0]),
.irq (),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[S0]),
.wbs_cyc_i (bussl_cyc_i[S0]),
.wbs_dat_i (bussl_dat_i[S0]),
.wbs_sel_i (bussl_sel_i[S0]),
.wbs_stb_i (bussl_stb_i[S0]),
.wbs_we_i (bussl_we_i[S0]),
.wbs_cab_i (bussl_cab_i[S0]),
.wbs_cti_i (bussl_cti_i[S0]),
.wbs_bte_i (bussl_bte_i[S0]));
dft_top_top dft_top_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i(bussl_adr_i[S1]),
.wb_cyc_i(bussl_cyc_i[S1]),
.wb_dat_i(bussl_dat_i[S1]),
.wb_sel_i(bussl_sel_i[S1]),
.wb_stb_i(bussl_stb_i[S1]),
.wb_we_i(bussl_we_i[S1]),
.wb_ack_o(bussl_ack_o[S1]),
.wb_dat_o(bussl_rty_o[S1]),
.wb_err_o(bussl_err_o[S1])
);
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module tile_fir_top
import dii_package::*;
import optimsoc_functions::*;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH,
/* User parameters */
// Set the number of masters and slaves
parameter MASTERS = 0,
parameter SLAVES = 1,
// Set bus address and data width in bits
// DATA_WIDTH must be a multiple of 8 (full bytes)!
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32,
// Memory range definitions, see above
// The number of parameters actually limits the number of slaves as
// there is no generic way that is handled by all tools to define
// variable width parameter arrays.
parameter S0_ENABLE = 1,
parameter S0_RANGE_WIDTH = 1,
parameter S0_RANGE_MATCH = 1'b0,
parameter S1_ENABLE = 0,
parameter S1_RANGE_WIDTH = 1,
parameter S1_RANGE_MATCH = 1'b0,
parameter S2_ENABLE = 0,
parameter S2_RANGE_WIDTH = 1,
parameter S2_RANGE_MATCH = 1'b0,
parameter S3_ENABLE = 0,
parameter S3_RANGE_WIDTH = 1,
parameter S3_RANGE_MATCH = 1'b0,
parameter S4_ENABLE = 0,
parameter S4_RANGE_WIDTH = 1,
parameter S4_RANGE_MATCH = 1'b0,
parameter S5_ENABLE = 0,
parameter S5_RANGE_WIDTH = 1,
parameter S5_RANGE_MATCH = 1'b0,
parameter S6_ENABLE = 0,
parameter S6_RANGE_WIDTH = 1,
parameter S6_RANGE_MATCH = 1'b0,
parameter S7_ENABLE = 0,
parameter S7_RANGE_WIDTH = 1,
parameter S7_RANGE_MATCH = 1'b0,
parameter S8_ENABLE = 0,
parameter S8_RANGE_WIDTH = 1,
parameter S8_RANGE_MATCH = 1'b0,
parameter S9_ENABLE = 0,
parameter S9_RANGE_WIDTH = 1,
parameter S9_RANGE_MATCH = 1'b0,
/* Derived local parameters */
// Width of byte select registers
localparam SEL_WIDTH = DATA_WIDTH >> 3
)
(
input clk,
input rst_sys,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
localparam NR_MASTERS = 0;
localparam NR_SLAVES = 10;
localparam S0 = 0;
localparam S1 = 1;
localparam S2 = 2;
localparam S3 = 3;
localparam S4 = 4;
localparam S5 = 5;
localparam S6 = 6;
localparam S7 = 7;
localparam S8 = 8;
localparam S9 = 9;
/* localparam SLAVE_NA = S0;
localparam SLAVE_AES = S1;
localparam SLAVE_DES3 = S2;
localparam SLAVE_SHA256 = S3;
localparam SLAVE_MD5 = S4;
localparam SLAVE_DFT = S5;
localparam SLAVE_FIR = S6;
localparam SLAVE_IDFT = S7;
localparam SLAVE_WBRAM = S8;
localparam SLAVE_UART = S9; */
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
genvar c, m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
# (
.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(S0_ENABLE),
.S0_RANGE_WIDTH(S0_RANGE_WIDTH),.S0_RANGE_MATCH(S0_RANGE_MATCH),
.S1_ENABLE(S1_ENABLE),
.S1_RANGE_WIDTH(S1_RANGE_WIDTH),.S1_RANGE_MATCH(S1_RANGE_MATCH),
.S2_ENABLE(S2_ENABLE),
.S2_RANGE_WIDTH(S2_RANGE_WIDTH),.S2_RANGE_MATCH(S2_RANGE_MATCH),
.S3_ENABLE(S3_ENABLE),
.S3_RANGE_WIDTH(S3_RANGE_WIDTH),.S3_RANGE_MATCH(S3_RANGE_MATCH),
.S4_ENABLE(S4_ENABLE),
.S4_RANGE_WIDTH(S4_RANGE_WIDTH),.S4_RANGE_MATCH(S4_RANGE_MATCH),
.S5_ENABLE(S5_ENABLE),
.S5_RANGE_WIDTH(S5_RANGE_WIDTH),.S5_RANGE_MATCH(S5_RANGE_MATCH),
.S6_ENABLE(S6_ENABLE),
.S6_RANGE_WIDTH(S6_RANGE_WIDTH),.S6_RANGE_MATCH(S6_RANGE_MATCH),
.S7_ENABLE(S7_ENABLE),
.S7_RANGE_WIDTH(S7_RANGE_WIDTH),.S7_RANGE_MATCH(S7_RANGE_MATCH),
.S8_ENABLE(S8_ENABLE),
.S8_RANGE_WIDTH(S8_RANGE_WIDTH),.S8_RANGE_MATCH(S8_RANGE_MATCH),
.S9_ENABLE(S9_ENABLE),
.S9_RANGE_WIDTH(S9_RANGE_WIDTH),.S9_RANGE_MATCH(S9_RANGE_MATCH)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
networkadapter_ct
#(.CONFIG(CONFIG)
)
fir_top_na(
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[S0]),
.wbs_rty_o (bussl_rty_o[S0]),
.wbs_err_o (bussl_err_o[S0]),
.wbs_dat_o (bussl_dat_o[S0]),
.irq (),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[S0]),
.wbs_cyc_i (bussl_cyc_i[S0]),
.wbs_dat_i (bussl_dat_i[S0]),
.wbs_sel_i (bussl_sel_i[S0]),
.wbs_stb_i (bussl_stb_i[S0]),
.wbs_we_i (bussl_we_i[S0]),
.wbs_cab_i (bussl_cab_i[S0]),
.wbs_cti_i (bussl_cti_i[S0]),
.wbs_bte_i (bussl_bte_i[S0]));
fir_top fir_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i(bussl_adr_i[S1]),
.wb_cyc_i(bussl_cyc_i[S1]),
.wb_dat_i(bussl_dat_i[S1]),
.wb_sel_i(bussl_sel_i[S1]),
.wb_stb_i(bussl_stb_i[S1]),
.wb_we_i(bussl_we_i[S1]),
.wb_ack_o(bussl_ack_o[S1]),
.wb_dat_o(bussl_rty_o[S1]),
.wb_err_o(bussl_err_o[S1])
);
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module tile_idft_top_top
import dii_package::*;
import optimsoc_functions::*;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH,
/* User parameters */
// Set the number of masters and slaves
parameter MASTERS = 0,
parameter SLAVES = 1,
// Set bus address and data width in bits
// DATA_WIDTH must be a multiple of 8 (full bytes)!
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32,
// Memory range definitions, see above
// The number of parameters actually limits the number of slaves as
// there is no generic way that is handled by all tools to define
// variable width parameter arrays.
parameter S0_ENABLE = 1,
parameter S0_RANGE_WIDTH = 1,
parameter S0_RANGE_MATCH = 1'b0,
parameter S1_ENABLE = 0,
parameter S1_RANGE_WIDTH = 1,
parameter S1_RANGE_MATCH = 1'b0,
parameter S2_ENABLE = 0,
parameter S2_RANGE_WIDTH = 1,
parameter S2_RANGE_MATCH = 1'b0,
parameter S3_ENABLE = 0,
parameter S3_RANGE_WIDTH = 1,
parameter S3_RANGE_MATCH = 1'b0,
parameter S4_ENABLE = 0,
parameter S4_RANGE_WIDTH = 1,
parameter S4_RANGE_MATCH = 1'b0,
parameter S5_ENABLE = 0,
parameter S5_RANGE_WIDTH = 1,
parameter S5_RANGE_MATCH = 1'b0,
parameter S6_ENABLE = 0,
parameter S6_RANGE_WIDTH = 1,
parameter S6_RANGE_MATCH = 1'b0,
parameter S7_ENABLE = 0,
parameter S7_RANGE_WIDTH = 1,
parameter S7_RANGE_MATCH = 1'b0,
parameter S8_ENABLE = 0,
parameter S8_RANGE_WIDTH = 1,
parameter S8_RANGE_MATCH = 1'b0,
parameter S9_ENABLE = 0,
parameter S9_RANGE_WIDTH = 1,
parameter S9_RANGE_MATCH = 1'b0,
/* Derived local parameters */
// Width of byte select registers
localparam SEL_WIDTH = DATA_WIDTH >> 3
)
(
input clk,
input rst_sys,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
localparam NR_MASTERS = 0;
localparam NR_SLAVES = 10;
localparam S0 = 0;
localparam S1 = 1;
localparam S2 = 2;
localparam S3 = 3;
localparam S4 = 4;
localparam S5 = 5;
localparam S6 = 6;
localparam S7 = 7;
localparam S8 = 8;
localparam S9 = 9;
/* localparam SLAVE_NA = S0;
localparam SLAVE_AES = S1;
localparam SLAVE_DES3 = S2;
localparam SLAVE_SHA256 = S3;
localparam SLAVE_MD5 = S4;
localparam SLAVE_DFT = S5;
localparam SLAVE_FIR = S6;
localparam SLAVE_IDFT = S7;
localparam SLAVE_WBRAM = S8;
localparam SLAVE_UART = S9; */
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
genvar c, m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
# (
.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(S0_ENABLE),
.S0_RANGE_WIDTH(S0_RANGE_WIDTH),.S0_RANGE_MATCH(S0_RANGE_MATCH),
.S1_ENABLE(S1_ENABLE),
.S1_RANGE_WIDTH(S1_RANGE_WIDTH),.S1_RANGE_MATCH(S1_RANGE_MATCH),
.S2_ENABLE(S2_ENABLE),
.S2_RANGE_WIDTH(S2_RANGE_WIDTH),.S2_RANGE_MATCH(S2_RANGE_MATCH),
.S3_ENABLE(S3_ENABLE),
.S3_RANGE_WIDTH(S3_RANGE_WIDTH),.S3_RANGE_MATCH(S3_RANGE_MATCH),
.S4_ENABLE(S4_ENABLE),
.S4_RANGE_WIDTH(S4_RANGE_WIDTH),.S4_RANGE_MATCH(S4_RANGE_MATCH),
.S5_ENABLE(S5_ENABLE),
.S5_RANGE_WIDTH(S5_RANGE_WIDTH),.S5_RANGE_MATCH(S5_RANGE_MATCH),
.S6_ENABLE(S6_ENABLE),
.S6_RANGE_WIDTH(S6_RANGE_WIDTH),.S6_RANGE_MATCH(S6_RANGE_MATCH),
.S7_ENABLE(S7_ENABLE),
.S7_RANGE_WIDTH(S7_RANGE_WIDTH),.S7_RANGE_MATCH(S7_RANGE_MATCH),
.S8_ENABLE(S8_ENABLE),
.S8_RANGE_WIDTH(S8_RANGE_WIDTH),.S8_RANGE_MATCH(S8_RANGE_MATCH),
.S9_ENABLE(S9_ENABLE),
.S9_RANGE_WIDTH(S9_RANGE_WIDTH),.S9_RANGE_MATCH(S9_RANGE_MATCH)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
networkadapter_ct
#(.CONFIG(CONFIG)
)
idft_top_top_na(
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[S0]),
.wbs_rty_o (bussl_rty_o[S0]),
.wbs_err_o (bussl_err_o[S0]),
.wbs_dat_o (bussl_dat_o[S0]),
.irq (),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[S0]),
.wbs_cyc_i (bussl_cyc_i[S0]),
.wbs_dat_i (bussl_dat_i[S0]),
.wbs_sel_i (bussl_sel_i[S0]),
.wbs_stb_i (bussl_stb_i[S0]),
.wbs_we_i (bussl_we_i[S0]),
.wbs_cab_i (bussl_cab_i[S0]),
.wbs_cti_i (bussl_cti_i[S0]),
.wbs_bte_i (bussl_bte_i[S0]));
idft_top_top idft_top_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i(bussl_adr_i[S1]),
.wb_cyc_i(bussl_cyc_i[S1]),
.wb_dat_i(bussl_dat_i[S1]),
.wb_sel_i(bussl_sel_i[S1]),
.wb_stb_i(bussl_stb_i[S1]),
.wb_we_i(bussl_we_i[S1]),
.wb_ack_o(bussl_ack_o[S1]),
.wb_dat_o(bussl_rty_o[S1]),
.wb_err_o(bussl_err_o[S1])
);
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module tile_md5_top
import dii_package::*;
import optimsoc_functions::*;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH,
/* User parameters */
// Set the number of masters and slaves
parameter MASTERS = 0,
parameter SLAVES = 1,
// Set bus address and data width in bits
// DATA_WIDTH must be a multiple of 8 (full bytes)!
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32,
// Memory range definitions, see above
// The number of parameters actually limits the number of slaves as
// there is no generic way that is handled by all tools to define
// variable width parameter arrays.
parameter S0_ENABLE = 1,
parameter S0_RANGE_WIDTH = 1,
parameter S0_RANGE_MATCH = 1'b0,
parameter S1_ENABLE = 0,
parameter S1_RANGE_WIDTH = 1,
parameter S1_RANGE_MATCH = 1'b0,
parameter S2_ENABLE = 0,
parameter S2_RANGE_WIDTH = 1,
parameter S2_RANGE_MATCH = 1'b0,
parameter S3_ENABLE = 0,
parameter S3_RANGE_WIDTH = 1,
parameter S3_RANGE_MATCH = 1'b0,
parameter S4_ENABLE = 0,
parameter S4_RANGE_WIDTH = 1,
parameter S4_RANGE_MATCH = 1'b0,
parameter S5_ENABLE = 0,
parameter S5_RANGE_WIDTH = 1,
parameter S5_RANGE_MATCH = 1'b0,
parameter S6_ENABLE = 0,
parameter S6_RANGE_WIDTH = 1,
parameter S6_RANGE_MATCH = 1'b0,
parameter S7_ENABLE = 0,
parameter S7_RANGE_WIDTH = 1,
parameter S7_RANGE_MATCH = 1'b0,
parameter S8_ENABLE = 0,
parameter S8_RANGE_WIDTH = 1,
parameter S8_RANGE_MATCH = 1'b0,
parameter S9_ENABLE = 0,
parameter S9_RANGE_WIDTH = 1,
parameter S9_RANGE_MATCH = 1'b0,
/* Derived local parameters */
// Width of byte select registers
localparam SEL_WIDTH = DATA_WIDTH >> 3
)
(
input clk,
input rst_sys,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
localparam NR_MASTERS = 0;
localparam NR_SLAVES = 10;
localparam S0 = 0;
localparam S1 = 1;
localparam S2 = 2;
localparam S3 = 3;
localparam S4 = 4;
localparam S5 = 5;
localparam S6 = 6;
localparam S7 = 7;
localparam S8 = 8;
localparam S9 = 9;
/* localparam SLAVE_NA = S0;
localparam SLAVE_AES = S1;
localparam SLAVE_DES3 = S2;
localparam SLAVE_SHA256 = S3;
localparam SLAVE_MD5 = S4;
localparam SLAVE_DFT = S5;
localparam SLAVE_FIR = S6;
localparam SLAVE_IDFT = S7;
localparam SLAVE_WBRAM = S8;
localparam SLAVE_UART = S9; */
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
genvar c, m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
# (
.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(S0_ENABLE),
.S0_RANGE_WIDTH(S0_RANGE_WIDTH),.S0_RANGE_MATCH(S0_RANGE_MATCH),
.S1_ENABLE(S1_ENABLE),
.S1_RANGE_WIDTH(S1_RANGE_WIDTH),.S1_RANGE_MATCH(S1_RANGE_MATCH),
.S2_ENABLE(S2_ENABLE),
.S2_RANGE_WIDTH(S2_RANGE_WIDTH),.S2_RANGE_MATCH(S2_RANGE_MATCH),
.S3_ENABLE(S3_ENABLE),
.S3_RANGE_WIDTH(S3_RANGE_WIDTH),.S3_RANGE_MATCH(S3_RANGE_MATCH),
.S4_ENABLE(S4_ENABLE),
.S4_RANGE_WIDTH(S4_RANGE_WIDTH),.S4_RANGE_MATCH(S4_RANGE_MATCH),
.S5_ENABLE(S5_ENABLE),
.S5_RANGE_WIDTH(S5_RANGE_WIDTH),.S5_RANGE_MATCH(S5_RANGE_MATCH),
.S6_ENABLE(S6_ENABLE),
.S6_RANGE_WIDTH(S6_RANGE_WIDTH),.S6_RANGE_MATCH(S6_RANGE_MATCH),
.S7_ENABLE(S7_ENABLE),
.S7_RANGE_WIDTH(S7_RANGE_WIDTH),.S7_RANGE_MATCH(S7_RANGE_MATCH),
.S8_ENABLE(S8_ENABLE),
.S8_RANGE_WIDTH(S8_RANGE_WIDTH),.S8_RANGE_MATCH(S8_RANGE_MATCH),
.S9_ENABLE(S9_ENABLE),
.S9_RANGE_WIDTH(S9_RANGE_WIDTH),.S9_RANGE_MATCH(S9_RANGE_MATCH)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
networkadapter_ct
#(.CONFIG(CONFIG)
)
md5_top_na(
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[S0]),
.wbs_rty_o (bussl_rty_o[S0]),
.wbs_err_o (bussl_err_o[S0]),
.wbs_dat_o (bussl_dat_o[S0]),
.irq (),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[S0]),
.wbs_cyc_i (bussl_cyc_i[S0]),
.wbs_dat_i (bussl_dat_i[S0]),
.wbs_sel_i (bussl_sel_i[S0]),
.wbs_stb_i (bussl_stb_i[S0]),
.wbs_we_i (bussl_we_i[S0]),
.wbs_cab_i (bussl_cab_i[S0]),
.wbs_cti_i (bussl_cti_i[S0]),
.wbs_bte_i (bussl_bte_i[S0]));
md5_top md5_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i(bussl_adr_i[S1]),
.wb_cyc_i(bussl_cyc_i[S1]),
.wb_dat_i(bussl_dat_i[S1]),
.wb_sel_i(bussl_sel_i[S1]),
.wb_stb_i(bussl_stb_i[S1]),
.wb_we_i(bussl_we_i[S1]),
.wb_ack_o(bussl_ack_o[S1]),
.wb_dat_o(bussl_rty_o[S1]),
.wb_err_o(bussl_err_o[S1])
);
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================*/
module tile_picorv32_top
import dii_package::*;
import optimsoc_functions::*;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH,
/* User parameters */
// Set the number of masters and slaves
parameter MASTERS = 1,
parameter SLAVES = 0,
// Set bus address and data width in bits
// DATA_WIDTH must be a multiple of 8 (full bytes)!
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32,
// Memory range definitions, see above
// The number of parameters actually limits the number of slaves as
// there is no generic way that is handled by all tools to define
// variable width parameter arrays.
parameter S0_ENABLE = 0,
parameter S0_RANGE_WIDTH = 1,
parameter S0_RANGE_MATCH = 1'b0,
parameter S1_ENABLE = 0,
parameter S1_RANGE_WIDTH = 1,
parameter S1_RANGE_MATCH = 1'b0,
parameter S2_ENABLE = 0,
parameter S2_RANGE_WIDTH = 1,
parameter S2_RANGE_MATCH = 1'b0,
parameter S3_ENABLE = 0,
parameter S3_RANGE_WIDTH = 1,
parameter S3_RANGE_MATCH = 1'b0,
parameter S4_ENABLE = 0,
parameter S4_RANGE_WIDTH = 1,
parameter S4_RANGE_MATCH = 1'b0,
parameter S5_ENABLE = 0,
parameter S5_RANGE_WIDTH = 1,
parameter S5_RANGE_MATCH = 1'b0,
parameter S6_ENABLE = 0,
parameter S6_RANGE_WIDTH = 1,
parameter S6_RANGE_MATCH = 1'b0,
parameter S7_ENABLE = 0,
parameter S7_RANGE_WIDTH = 1,
parameter S7_RANGE_MATCH = 1'b0,
parameter S8_ENABLE = 0,
parameter S8_RANGE_WIDTH = 1,
parameter S8_RANGE_MATCH = 1'b0,
parameter S9_ENABLE = 0,
parameter S9_RANGE_WIDTH = 1,
parameter S9_RANGE_MATCH = 1'b0,
/* Derived local parameters */
// Width of byte select registers
localparam SEL_WIDTH = DATA_WIDTH >> 3
)
(
input clk,
input rst_sys,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
localparam NR_MASTERS = 1;
localparam NR_SLAVES = 10;
localparam S0 = 0;
localparam S1 = 1;
localparam S2 = 2;
localparam S3 = 3;
localparam S4 = 4;
localparam S5 = 5;
localparam S6 = 6;
localparam S7 = 7;
localparam S8 = 8;
localparam S9 = 9;
localparam SLAVE_NA = S0;
localparam SLAVE_AES = S1;
localparam SLAVE_DES3 = S2;
localparam SLAVE_SHA256 = S3;
localparam SLAVE_MD5 = S4;
localparam SLAVE_DFT = S5;
localparam SLAVE_FIR = S6;
localparam SLAVE_IDFT = S7;
localparam SLAVE_WBRAM = S8;
localparam SLAVE_UART = S9;
wire [31:0] busms_adr_o;
wire busms_cyc_o;
wire [31:0] busms_dat_o;
wire [3:0] busms_sel_o;
wire busms_stb_o;
wire busms_we_o;
wire busms_cab_o;
wire [2:0] busms_cti_o;
wire [1:0] busms_bte_o;
wire busms_ack_i;
wire busms_rty_i;
wire busms_err_i;
wire [31:0] busms_dat_i;
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
genvar m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
wb_bus_b3
# (
.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(S0_ENABLE),
.S0_RANGE_WIDTH(S0_RANGE_WIDTH),.S0_RANGE_MATCH(S0_RANGE_MATCH),
.S1_ENABLE(S1_ENABLE),
.S1_RANGE_WIDTH(S1_RANGE_WIDTH),.S1_RANGE_MATCH(S1_RANGE_MATCH),
.S2_ENABLE(S2_ENABLE),
.S2_RANGE_WIDTH(S2_RANGE_WIDTH),.S2_RANGE_MATCH(S2_RANGE_MATCH),
.S3_ENABLE(S3_ENABLE),
.S3_RANGE_WIDTH(S3_RANGE_WIDTH),.S3_RANGE_MATCH(S3_RANGE_MATCH),
.S4_ENABLE(S4_ENABLE),
.S4_RANGE_WIDTH(S4_RANGE_WIDTH),.S4_RANGE_MATCH(S4_RANGE_MATCH),
.S5_ENABLE(S5_ENABLE),
.S5_RANGE_WIDTH(S5_RANGE_WIDTH),.S5_RANGE_MATCH(S5_RANGE_MATCH),
.S6_ENABLE(S6_ENABLE),
.S6_RANGE_WIDTH(S6_RANGE_WIDTH),.S6_RANGE_MATCH(S6_RANGE_MATCH),
.S7_ENABLE(S7_ENABLE),
.S7_RANGE_WIDTH(S7_RANGE_WIDTH),.S7_RANGE_MATCH(S7_RANGE_MATCH),
.S8_ENABLE(S8_ENABLE),
.S8_RANGE_WIDTH(S8_RANGE_WIDTH),.S8_RANGE_MATCH(S8_RANGE_MATCH),
.S9_ENABLE(S9_ENABLE),
.S9_RANGE_WIDTH(S9_RANGE_WIDTH),.S9_RANGE_MATCH(S9_RANGE_MATCH)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i), // Templated
.m_ack_o (busms_ack_i), // Templated
.m_err_o (busms_err_i), // Templated
.m_rty_o (busms_rty_i), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o), // Templated
.m_dat_i (busms_dat_o), // Templated
.m_cyc_i (busms_cyc_o), // Templated
.m_stb_i (busms_stb_o), // Templated
.m_sel_i (busms_sel_o), // Templated
.m_we_i (busms_we_o), // Templated
.m_cti_i (busms_cti_o), // Templated
.m_bte_i (busms_bte_o), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
networkadapter_ct
#(.CONFIG(CONFIG)
)
u_na(
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o),
.wbm_cyc_o (busms_cyc_o),
.wbm_dat_o (busms_dat_o),
.wbm_sel_o (busms_sel_o),
.wbm_stb_o (busms_stb_o),
.wbm_we_o (busms_we_o),
.wbm_cab_o (busms_cab_o),
.wbm_cti_o (busms_cti_o),
.wbm_bte_o (busms_bte_o),
.wbs_ack_o (bussl_ack_o[S0]),
.wbs_rty_o (bussl_rty_o[S0]),
.wbs_err_o (bussl_err_o[S0]),
.wbs_dat_o (bussl_dat_o[S0]),
.irq (),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i),
.wbm_rty_i (busms_rty_i),
.wbm_err_i (busms_err_i),
.wbm_dat_i (busms_dat_i),
.wbs_adr_i (bussl_adr_i[S0]),
.wbs_cyc_i (bussl_cyc_i[S0]),
.wbs_dat_i (bussl_dat_i[S0]),
.wbs_sel_i (bussl_sel_i[S0]),
.wbs_stb_i (bussl_stb_i[S0]),
.wbs_we_i (bussl_we_i[S0]),
.wbs_cab_i (bussl_cab_i[S0]),
.wbs_cti_i (bussl_cti_i[S0]),
.wbs_bte_i (bussl_bte_i[S0]));
picorv32_top picorv32_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wbm_adr_o (busms_adr_o), // Templated
.wbm_dat_i (busms_dat_i), // Templated
.wbm_cyc_o (busms_cyc_o), // Templated
.wbm_stb_o (busms_stb_o), // Templated
.wbm_we_o (busms_we_o), // Templated
.wbm_dat_o (busms_dat_o), // Templated
.wbm_ack_i (busms_ack_i), // Templated
.wbm_sel_o ()
); // Templated
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module tile_ram_wb_01
import dii_package::*;
import optimsoc_functions::*;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH,
/* User parameters */
// Set the number of masters and slaves
parameter MASTERS = 0,
parameter SLAVES = 1,
// Set bus address and data width in bits
// DATA_WIDTH must be a multiple of 8 (full bytes)!
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32,
// Memory range definitions, see above
// The number of parameters actually limits the number of slaves as
// there is no generic way that is handled by all tools to define
// variable width parameter arrays.
parameter S0_ENABLE = 1,
parameter S0_RANGE_WIDTH = 1,
parameter S0_RANGE_MATCH = 1'b0,
parameter S1_ENABLE = 0,
parameter S1_RANGE_WIDTH = 1,
parameter S1_RANGE_MATCH = 1'b0,
parameter S2_ENABLE = 0,
parameter S2_RANGE_WIDTH = 1,
parameter S2_RANGE_MATCH = 1'b0,
parameter S3_ENABLE = 0,
parameter S3_RANGE_WIDTH = 1,
parameter S3_RANGE_MATCH = 1'b0,
parameter S4_ENABLE = 0,
parameter S4_RANGE_WIDTH = 1,
parameter S4_RANGE_MATCH = 1'b0,
parameter S5_ENABLE = 0,
parameter S5_RANGE_WIDTH = 1,
parameter S5_RANGE_MATCH = 1'b0,
parameter S6_ENABLE = 0,
parameter S6_RANGE_WIDTH = 1,
parameter S6_RANGE_MATCH = 1'b0,
parameter S7_ENABLE = 0,
parameter S7_RANGE_WIDTH = 1,
parameter S7_RANGE_MATCH = 1'b0,
parameter S8_ENABLE = 0,
parameter S8_RANGE_WIDTH = 1,
parameter S8_RANGE_MATCH = 1'b0,
parameter S9_ENABLE = 0,
parameter S9_RANGE_WIDTH = 1,
parameter S9_RANGE_MATCH = 1'b0,
/* Derived local parameters */
// Width of byte select registers
localparam SEL_WIDTH = DATA_WIDTH >> 3
)
(
input clk,
input rst_sys,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
localparam NR_MASTERS = 0;
localparam NR_SLAVES = 10;
localparam S0 = 0;
localparam S1 = 1;
localparam S2 = 2;
localparam S3 = 3;
localparam S4 = 4;
localparam S5 = 5;
localparam S6 = 6;
localparam S7 = 7;
localparam S8 = 8;
localparam S9 = 9;
/* localparam SLAVE_NA = S0;
localparam SLAVE_AES = S1;
localparam SLAVE_DES3 = S2;
localparam SLAVE_SHA256 = S3;
localparam SLAVE_MD5 = S4;
localparam SLAVE_DFT = S5;
localparam SLAVE_FIR = S6;
localparam SLAVE_IDFT = S7;
localparam SLAVE_WBRAM = S8;
localparam SLAVE_UART = S9; */
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
genvar c, m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
# (
.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(S0_ENABLE),
.S0_RANGE_WIDTH(S0_RANGE_WIDTH),.S0_RANGE_MATCH(S0_RANGE_MATCH),
.S1_ENABLE(S1_ENABLE),
.S1_RANGE_WIDTH(S1_RANGE_WIDTH),.S1_RANGE_MATCH(S1_RANGE_MATCH),
.S2_ENABLE(S2_ENABLE),
.S2_RANGE_WIDTH(S2_RANGE_WIDTH),.S2_RANGE_MATCH(S2_RANGE_MATCH),
.S3_ENABLE(S3_ENABLE),
.S3_RANGE_WIDTH(S3_RANGE_WIDTH),.S3_RANGE_MATCH(S3_RANGE_MATCH),
.S4_ENABLE(S4_ENABLE),
.S4_RANGE_WIDTH(S4_RANGE_WIDTH),.S4_RANGE_MATCH(S4_RANGE_MATCH),
.S5_ENABLE(S5_ENABLE),
.S5_RANGE_WIDTH(S5_RANGE_WIDTH),.S5_RANGE_MATCH(S5_RANGE_MATCH),
.S6_ENABLE(S6_ENABLE),
.S6_RANGE_WIDTH(S6_RANGE_WIDTH),.S6_RANGE_MATCH(S6_RANGE_MATCH),
.S7_ENABLE(S7_ENABLE),
.S7_RANGE_WIDTH(S7_RANGE_WIDTH),.S7_RANGE_MATCH(S7_RANGE_MATCH),
.S8_ENABLE(S8_ENABLE),
.S8_RANGE_WIDTH(S8_RANGE_WIDTH),.S8_RANGE_MATCH(S8_RANGE_MATCH),
.S9_ENABLE(S9_ENABLE),
.S9_RANGE_WIDTH(S9_RANGE_WIDTH),.S9_RANGE_MATCH(S9_RANGE_MATCH)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
networkadapter_ct
#(.CONFIG(CONFIG)
)
ram_wb_01_na(
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[S0]),
.wbs_rty_o (bussl_rty_o[S0]),
.wbs_err_o (bussl_err_o[S0]),
.wbs_dat_o (bussl_dat_o[S0]),
.irq (),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[S0]),
.wbs_cyc_i (bussl_cyc_i[S0]),
.wbs_dat_i (bussl_dat_i[S0]),
.wbs_sel_i (bussl_sel_i[S0]),
.wbs_stb_i (bussl_stb_i[S0]),
.wbs_we_i (bussl_we_i[S0]),
.wbs_cab_i (bussl_cab_i[S0]),
.wbs_cti_i (bussl_cti_i[S0]),
.wbs_bte_i (bussl_bte_i[S0]));
ram_wb_01 ram_wb_01_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i(bussl_adr_i[S1]),
.wb_cyc_i(bussl_cyc_i[S1]),
.wb_dat_i(bussl_dat_i[S1]),
.wb_sel_i(bussl_sel_i[S1]),
.wb_stb_i(bussl_stb_i[S1]),
.wb_we_i(bussl_we_i[S1]),
.wb_ack_o(bussl_ack_o[S1]),
.wb_dat_o(bussl_rty_o[S1]),
.wb_err_o(bussl_err_o[S1])
);
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module tile_ram_wb_02
import dii_package::*;
import optimsoc_functions::*;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH,
/* User parameters */
// Set the number of masters and slaves
parameter MASTERS = 0,
parameter SLAVES = 1,
// Set bus address and data width in bits
// DATA_WIDTH must be a multiple of 8 (full bytes)!
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32,
// Memory range definitions, see above
// The number of parameters actually limits the number of slaves as
// there is no generic way that is handled by all tools to define
// variable width parameter arrays.
parameter S0_ENABLE = 1,
parameter S0_RANGE_WIDTH = 1,
parameter S0_RANGE_MATCH = 1'b0,
parameter S1_ENABLE = 0,
parameter S1_RANGE_WIDTH = 1,
parameter S1_RANGE_MATCH = 1'b0,
parameter S2_ENABLE = 0,
parameter S2_RANGE_WIDTH = 1,
parameter S2_RANGE_MATCH = 1'b0,
parameter S3_ENABLE = 0,
parameter S3_RANGE_WIDTH = 1,
parameter S3_RANGE_MATCH = 1'b0,
parameter S4_ENABLE = 0,
parameter S4_RANGE_WIDTH = 1,
parameter S4_RANGE_MATCH = 1'b0,
parameter S5_ENABLE = 0,
parameter S5_RANGE_WIDTH = 1,
parameter S5_RANGE_MATCH = 1'b0,
parameter S6_ENABLE = 0,
parameter S6_RANGE_WIDTH = 1,
parameter S6_RANGE_MATCH = 1'b0,
parameter S7_ENABLE = 0,
parameter S7_RANGE_WIDTH = 1,
parameter S7_RANGE_MATCH = 1'b0,
parameter S8_ENABLE = 0,
parameter S8_RANGE_WIDTH = 1,
parameter S8_RANGE_MATCH = 1'b0,
parameter S9_ENABLE = 0,
parameter S9_RANGE_WIDTH = 1,
parameter S9_RANGE_MATCH = 1'b0,
/* Derived local parameters */
// Width of byte select registers
localparam SEL_WIDTH = DATA_WIDTH >> 3
)
(
input clk,
input rst_sys,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
localparam NR_MASTERS = 0;
localparam NR_SLAVES = 10;
localparam S0 = 0;
localparam S1 = 1;
localparam S2 = 2;
localparam S3 = 3;
localparam S4 = 4;
localparam S5 = 5;
localparam S6 = 6;
localparam S7 = 7;
localparam S8 = 8;
localparam S9 = 9;
/* localparam SLAVE_NA = S0;
localparam SLAVE_AES = S1;
localparam SLAVE_DES3 = S2;
localparam SLAVE_SHA256 = S3;
localparam SLAVE_MD5 = S4;
localparam SLAVE_DFT = S5;
localparam SLAVE_FIR = S6;
localparam SLAVE_IDFT = S7;
localparam SLAVE_WBRAM = S8;
localparam SLAVE_UART = S9; */
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
genvar c, m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
# (
.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(S0_ENABLE),
.S0_RANGE_WIDTH(S0_RANGE_WIDTH),.S0_RANGE_MATCH(S0_RANGE_MATCH),
.S1_ENABLE(S1_ENABLE),
.S1_RANGE_WIDTH(S1_RANGE_WIDTH),.S1_RANGE_MATCH(S1_RANGE_MATCH),
.S2_ENABLE(S2_ENABLE),
.S2_RANGE_WIDTH(S2_RANGE_WIDTH),.S2_RANGE_MATCH(S2_RANGE_MATCH),
.S3_ENABLE(S3_ENABLE),
.S3_RANGE_WIDTH(S3_RANGE_WIDTH),.S3_RANGE_MATCH(S3_RANGE_MATCH),
.S4_ENABLE(S4_ENABLE),
.S4_RANGE_WIDTH(S4_RANGE_WIDTH),.S4_RANGE_MATCH(S4_RANGE_MATCH),
.S5_ENABLE(S5_ENABLE),
.S5_RANGE_WIDTH(S5_RANGE_WIDTH),.S5_RANGE_MATCH(S5_RANGE_MATCH),
.S6_ENABLE(S6_ENABLE),
.S6_RANGE_WIDTH(S6_RANGE_WIDTH),.S6_RANGE_MATCH(S6_RANGE_MATCH),
.S7_ENABLE(S7_ENABLE),
.S7_RANGE_WIDTH(S7_RANGE_WIDTH),.S7_RANGE_MATCH(S7_RANGE_MATCH),
.S8_ENABLE(S8_ENABLE),
.S8_RANGE_WIDTH(S8_RANGE_WIDTH),.S8_RANGE_MATCH(S8_RANGE_MATCH),
.S9_ENABLE(S9_ENABLE),
.S9_RANGE_WIDTH(S9_RANGE_WIDTH),.S9_RANGE_MATCH(S9_RANGE_MATCH)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
networkadapter_ct
#(.CONFIG(CONFIG)
)
ram_wb_02_na(
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[S0]),
.wbs_rty_o (bussl_rty_o[S0]),
.wbs_err_o (bussl_err_o[S0]),
.wbs_dat_o (bussl_dat_o[S0]),
.irq (),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[S0]),
.wbs_cyc_i (bussl_cyc_i[S0]),
.wbs_dat_i (bussl_dat_i[S0]),
.wbs_sel_i (bussl_sel_i[S0]),
.wbs_stb_i (bussl_stb_i[S0]),
.wbs_we_i (bussl_we_i[S0]),
.wbs_cab_i (bussl_cab_i[S0]),
.wbs_cti_i (bussl_cti_i[S0]),
.wbs_bte_i (bussl_bte_i[S0]));
ram_wb_02 ram_wb_02_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i(bussl_adr_i[S1]),
.wb_cyc_i(bussl_cyc_i[S1]),
.wb_dat_i(bussl_dat_i[S1]),
.wb_sel_i(bussl_sel_i[S1]),
.wb_stb_i(bussl_stb_i[S1]),
.wb_we_i(bussl_we_i[S1]),
.wb_ack_o(bussl_ack_o[S1]),
.wb_dat_o(bussl_rty_o[S1]),
.wb_err_o(bussl_err_o[S1])
);
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module tile_uart_top
import dii_package::*;
import optimsoc_functions::*;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH,
/* User parameters */
// Set the number of masters and slaves
parameter MASTERS = 0,
parameter SLAVES = 1,
// Set bus address and data width in bits
// DATA_WIDTH must be a multiple of 8 (full bytes)!
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32,
// Memory range definitions, see above
// The number of parameters actually limits the number of slaves as
// there is no generic way that is handled by all tools to define
// variable width parameter arrays.
parameter S0_ENABLE = 1,
parameter S0_RANGE_WIDTH = 1,
parameter S0_RANGE_MATCH = 1'b0,
parameter S1_ENABLE = 0,
parameter S1_RANGE_WIDTH = 1,
parameter S1_RANGE_MATCH = 1'b0,
parameter S2_ENABLE = 0,
parameter S2_RANGE_WIDTH = 1,
parameter S2_RANGE_MATCH = 1'b0,
parameter S3_ENABLE = 0,
parameter S3_RANGE_WIDTH = 1,
parameter S3_RANGE_MATCH = 1'b0,
parameter S4_ENABLE = 0,
parameter S4_RANGE_WIDTH = 1,
parameter S4_RANGE_MATCH = 1'b0,
parameter S5_ENABLE = 0,
parameter S5_RANGE_WIDTH = 1,
parameter S5_RANGE_MATCH = 1'b0,
parameter S6_ENABLE = 0,
parameter S6_RANGE_WIDTH = 1,
parameter S6_RANGE_MATCH = 1'b0,
parameter S7_ENABLE = 0,
parameter S7_RANGE_WIDTH = 1,
parameter S7_RANGE_MATCH = 1'b0,
parameter S8_ENABLE = 0,
parameter S8_RANGE_WIDTH = 1,
parameter S8_RANGE_MATCH = 1'b0,
parameter S9_ENABLE = 0,
parameter S9_RANGE_WIDTH = 1,
parameter S9_RANGE_MATCH = 1'b0,
/* Derived local parameters */
// Width of byte select registers
localparam SEL_WIDTH = DATA_WIDTH >> 3
)
(
input clk,
input rst_sys,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
localparam NR_MASTERS = 0;
localparam NR_SLAVES = 10;
localparam S0 = 0;
localparam S1 = 1;
localparam S2 = 2;
localparam S3 = 3;
localparam S4 = 4;
localparam S5 = 5;
localparam S6 = 6;
localparam S7 = 7;
localparam S8 = 8;
localparam S9 = 9;
/* localparam SLAVE_NA = S0;
localparam SLAVE_AES = S1;
localparam SLAVE_DES3 = S2;
localparam SLAVE_SHA256 = S3;
localparam SLAVE_MD5 = S4;
localparam SLAVE_DFT = S5;
localparam SLAVE_FIR = S6;
localparam SLAVE_IDFT = S7;
localparam SLAVE_WBRAM = S8;
localparam SLAVE_UART = S9; */
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
genvar c, m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
# (
.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(S0_ENABLE),
.S0_RANGE_WIDTH(S0_RANGE_WIDTH),.S0_RANGE_MATCH(S0_RANGE_MATCH),
.S1_ENABLE(S1_ENABLE),
.S1_RANGE_WIDTH(S1_RANGE_WIDTH),.S1_RANGE_MATCH(S1_RANGE_MATCH),
.S2_ENABLE(S2_ENABLE),
.S2_RANGE_WIDTH(S2_RANGE_WIDTH),.S2_RANGE_MATCH(S2_RANGE_MATCH),
.S3_ENABLE(S3_ENABLE),
.S3_RANGE_WIDTH(S3_RANGE_WIDTH),.S3_RANGE_MATCH(S3_RANGE_MATCH),
.S4_ENABLE(S4_ENABLE),
.S4_RANGE_WIDTH(S4_RANGE_WIDTH),.S4_RANGE_MATCH(S4_RANGE_MATCH),
.S5_ENABLE(S5_ENABLE),
.S5_RANGE_WIDTH(S5_RANGE_WIDTH),.S5_RANGE_MATCH(S5_RANGE_MATCH),
.S6_ENABLE(S6_ENABLE),
.S6_RANGE_WIDTH(S6_RANGE_WIDTH),.S6_RANGE_MATCH(S6_RANGE_MATCH),
.S7_ENABLE(S7_ENABLE),
.S7_RANGE_WIDTH(S7_RANGE_WIDTH),.S7_RANGE_MATCH(S7_RANGE_MATCH),
.S8_ENABLE(S8_ENABLE),
.S8_RANGE_WIDTH(S8_RANGE_WIDTH),.S8_RANGE_MATCH(S8_RANGE_MATCH),
.S9_ENABLE(S9_ENABLE),
.S9_RANGE_WIDTH(S9_RANGE_WIDTH),.S9_RANGE_MATCH(S9_RANGE_MATCH)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
networkadapter_ct
#(.CONFIG(CONFIG)
)
uart_top_na(
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[S0]),
.wbs_rty_o (bussl_rty_o[S0]),
.wbs_err_o (bussl_err_o[S0]),
.wbs_dat_o (bussl_dat_o[S0]),
.irq (),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[S0]),
.wbs_cyc_i (bussl_cyc_i[S0]),
.wbs_dat_i (bussl_dat_i[S0]),
.wbs_sel_i (bussl_sel_i[S0]),
.wbs_stb_i (bussl_stb_i[S0]),
.wbs_we_i (bussl_we_i[S0]),
.wbs_cab_i (bussl_cab_i[S0]),
.wbs_cti_i (bussl_cti_i[S0]),
.wbs_bte_i (bussl_bte_i[S0]));
uart_top uart_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i(bussl_adr_i[S1]),
.wb_cyc_i(bussl_cyc_i[S1]),
.wb_dat_i(bussl_dat_i[S1]),
.wb_sel_i(bussl_sel_i[S1]),
.wb_stb_i(bussl_stb_i[S1]),
.wb_we_i(bussl_we_i[S1]),
.wb_ack_o(bussl_ack_o[S1]),
.wb_dat_o(bussl_rty_o[S1]),
.wb_err_o(bussl_err_o[S1])
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// raminfr.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// Inferrable Distributed RAM for FIFOs ////
//// ////
//// Known problems (limits): ////
//// None . ////
//// ////
//// To Do: ////
//// Nothing so far. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// ////
//// Created: 2002/07/22 ////
//// Last Updated: 2002/07/22 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
//Following is the Verilog code for a dual-port RAM with asynchronous read.
module raminfr
(clk, we, a, dpra, di, dpo);
parameter addr_width = 4;
parameter data_width = 8;
parameter depth = 16;
input clk;
input we;
input [addr_width-1:0] a;
input [addr_width-1:0] dpra;
input [data_width-1:0] di;
//output [data_width-1:0] spo;
output [data_width-1:0] dpo;
reg [data_width-1:0] ram [depth-1:0];
wire [data_width-1:0] dpo;
wire [data_width-1:0] di;
wire [addr_width-1:0] a;
wire [addr_width-1:0] dpra;
always @(posedge clk) begin
if (we)
ram[a] <= di;
end
// assign spo = ram[a];
assign dpo = ram[dpra];
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_defines.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// Defines of the Core ////
//// ////
//// Known problems (limits): ////
//// None ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) = ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.13 2003/06/11 16:37:47 gorban
// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
//
// Revision 1.12 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.10 2001/12/11 08:55:40 mohor
// Scratch register define added.
//
// Revision 1.9 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.8 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.7 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.6 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.5 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.4 2001/05/21 19:12:02 gorban
// Corrected some Linter messages.
//
// Revision 1.3 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:11+02 jacob
// Initial revision
//
//
// Uncomment this if you want your UART to have
// 16xBaudrate output port.
// If defined, the enable signal will be used to drive baudrate_o signal
// It's frequency is 16xbaudrate
// `define UART_HAS_BAUDRATE_OUTPUT
// Register addresses
`define UART_REG_RB 3'd0 // receiver buffer
`define UART_REG_TR 3'd0 // transmitter
`define UART_REG_IE 3'd1 // Interrupt enable
`define UART_REG_II 3'd2 // Interrupt identification
`define UART_REG_FC 3'd2 // FIFO control
`define UART_REG_LC 3'd3 // Line Control
`define UART_REG_MC 3'd4 // Modem control
`define UART_REG_LS 3'd5 // Line status
`define UART_REG_MS 3'd6 // Modem status
`define UART_REG_SR 3'd7 // Scratch register
`define UART_REG_DL1 3'd0 // Divisor latch bytes (1-2)
`define UART_REG_DL2 3'd1
// Interrupt Enable register bits
`define UART_IE_RDA 0 // Received Data available interrupt
`define UART_IE_THRE 1 // Transmitter Holding Register empty interrupt
`define UART_IE_RLS 2 // Receiver Line Status Interrupt
`define UART_IE_MS 3 // Modem Status Interrupt
// Interrupt Identification register bits
`define UART_II_IP 0 // Interrupt pending when 0
`define UART_II_II 3:1 // Interrupt identification
// Interrupt identification values for bits 3:1
`define UART_II_RLS 3'b011 // Receiver Line Status
`define UART_II_RDA 3'b010 // Receiver Data available
`define UART_II_TI 3'b110 // Timeout Indication
`define UART_II_THRE 3'b001 // Transmitter Holding Register empty
`define UART_II_MS 3'b000 // Modem Status
// FIFO Control Register bits
`define UART_FC_TL 1:0 // Trigger level
// FIFO trigger level values
`define UART_FC_1 2'b00
`define UART_FC_4 2'b01
`define UART_FC_8 2'b10
`define UART_FC_14 2'b11
// Line Control register bits
`define UART_LC_BITS 1:0 // bits in character
`define UART_LC_SB 2 // stop bits
`define UART_LC_PE 3 // parity enable
`define UART_LC_EP 4 // even parity
`define UART_LC_SP 5 // stick parity
`define UART_LC_BC 6 // Break control
`define UART_LC_DL 7 // Divisor Latch access bit
// Modem Control register bits
`define UART_MC_DTR 0
`define UART_MC_RTS 1
`define UART_MC_OUT1 2
`define UART_MC_OUT2 3
`define UART_MC_LB 4 // Loopback mode
// Line Status Register bits
`define UART_LS_DR 0 // Data ready
`define UART_LS_OE 1 // Overrun Error
`define UART_LS_PE 2 // Parity Error
`define UART_LS_FE 3 // Framing Error
`define UART_LS_BI 4 // Break interrupt
`define UART_LS_TFE 5 // Transmit FIFO is empty
`define UART_LS_TE 6 // Transmitter Empty indicator
`define UART_LS_EI 7 // Error indicator
// Modem Status Register bits
`define UART_MS_DCTS 0 // Delta signals
`define UART_MS_DDSR 1
`define UART_MS_TERI 2
`define UART_MS_DDCD 3
`define UART_MS_CCTS 4 // Complement signals
`define UART_MS_CDSR 5
`define UART_MS_CRI 6
`define UART_MS_CDCD 7
// FIFO parameter defines
`define UART_FIFO_WIDTH 8
`define UART_FIFO_DEPTH 16
`define UART_FIFO_POINTER_W 4
`define UART_FIFO_COUNTER_W 5
// receiver fifo has width 11 because it has break, parity and framing error bits
`define UART_FIFO_REC_WIDTH 11
`define VERBOSE_WB 0 // All activity on the WISHBONE is recorded
`define VERBOSE_LINE_STATUS 0 // Details about the lsr (line status register)
`define FAST_TEST 1 // 64/1024 packets are sent
// Define the prescaler (divisor) for the UART as the initialization code that is part
// of the or1k toolchain does not seem to be setting it at all
`define PRESCALER_PRESET_HARD
`define PRESCALER_LOW_PRESET 8'd27
`define PRESCALER_HIGH_PRESET 8'd0
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_receiver.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core receiver logic ////
//// ////
//// Known problems (limits): ////
//// None known ////
//// ////
//// To Do: ////
//// Thourough testing. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.29 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.28 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.27 2001/12/30 20:39:13 mohor
// More than one character was stored in case of break. End of the break
// was not detected correctly.
//
// Revision 1.26 2001/12/20 13:28:27 mohor
// Missing declaration of rf_push_q fixed.
//
// Revision 1.25 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.24 2001/12/19 08:03:34 mohor
// Warnings cleared.
//
// Revision 1.23 2001/12/19 07:33:54 mohor
// Synplicity was having troubles with the comment.
//
// Revision 1.22 2001/12/17 14:46:48 mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.21 2001/12/13 10:31:16 mohor
// timeout irq must be set regardless of the rda irq (rda irq does not reset the
// timeout counter).
//
// Revision 1.20 2001/12/10 19:52:05 gorban
// Igor fixed break condition bugs
//
// Revision 1.19 2001/12/06 14:51:04 gorban
// Bug in LSR[0] is fixed.
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
//
// Revision 1.18 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.17 2001/11/28 19:36:39 gorban
// Fixed: timeout and break didn't pay attention to current data format when counting time
//
// Revision 1.16 2001/11/27 22:17:09 gorban
// Fixed bug that prevented synthesis in uart_receiver.v
//
// Revision 1.15 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.14 2001/11/10 12:43:21 gorban
// Logic Synthesis bugs fixed. Some other minor changes
//
// Revision 1.13 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.12 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.11 2001/10/31 15:19:22 gorban
// Fixes to break and timeout conditions
//
// Revision 1.10 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.9 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.6 2001/06/23 11:21:48 gorban
// DL made 16-bit long. Fixed transmission/reception bugs.
//
// Revision 1.5 2001/06/02 14:28:14 gorban
// Fixed receiver and transmitter. Major bug fixed.
//
// Revision 1.4 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/27 17:37:49 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2 2001/05/21 19:12:02 gorban
// Corrected some Linter messages.
//
// Revision 1.1 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:11+02 jacob
// Initial revision
//
//
`include "uart_defines.v"
module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable,
counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
input clk;
input wb_rst_i;
input [7:0] lcr;
input rf_pop;
input srx_pad_i;
input enable;
input rx_reset;
input lsr_mask;
output [9:0] counter_t;
output [`UART_FIFO_COUNTER_W-1:0] rf_count;
output [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
output rf_overrun;
output rf_error_bit;
output [3:0] rstate;
output rf_push_pulse;
reg [3:0] rstate;
reg [3:0] rcounter16;
reg [2:0] rbit_counter;
reg [7:0] rshift; // receiver shift register
reg rparity; // received parity
reg rparity_error;
reg rframing_error; // framing error flag
reg rparity_xor;
reg [7:0] counter_b; // counts the 0 (low) signals
reg rf_push_q;
// RX FIFO signals
reg [`UART_FIFO_REC_WIDTH-1:0] rf_data_in;
wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
wire rf_push_pulse;
reg rf_push;
wire rf_pop;
wire rf_overrun;
wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
wire rf_error_bit; // an error (parity or framing) is inside the fifo
wire break_error = (counter_b == 0);
// RX FIFO instance
uart_rfifo #(`UART_FIFO_REC_WIDTH) fifo_rx(
.clk( clk ),
.wb_rst_i( wb_rst_i ),
.data_in( rf_data_in ),
.data_out( rf_data_out ),
.push( rf_push_pulse ),
.pop( rf_pop ),
.overrun( rf_overrun ),
.count( rf_count ),
.error_bit( rf_error_bit ),
.fifo_reset( rx_reset ),
.reset_status(lsr_mask)
);
wire rcounter16_eq_7 = (rcounter16 == 4'd7);
wire rcounter16_eq_0 = (rcounter16 == 4'd0);
wire [3:0] rcounter16_minus_1 = rcounter16 - 3'd1;
parameter sr_idle = 4'd0;
parameter sr_rec_start = 4'd1;
parameter sr_rec_bit = 4'd2;
parameter sr_rec_parity = 4'd3;
parameter sr_rec_stop = 4'd4;
parameter sr_check_parity = 4'd5;
parameter sr_rec_prepare = 4'd6;
parameter sr_end_bit = 4'd7;
parameter sr_ca_lc_parity = 4'd8;
parameter sr_wait1 = 4'd9;
parameter sr_push = 4'd10;
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
begin
rstate <= sr_idle;
rcounter16 <= 0;
rbit_counter <= 0;
rparity_xor <= 1'b0;
rframing_error <= 1'b0;
rparity_error <= 1'b0;
rparity <= 1'b0;
rshift <= 0;
rf_push <= 1'b0;
rf_data_in <= 0;
end
else
if (enable)
begin
case (rstate)
sr_idle : begin
rf_push <= 1'b0;
rf_data_in <= 0;
rcounter16 <= 4'b1110;
if (srx_pad_i==1'b0 & ~break_error) // detected a pulse (start bit?)
begin
rstate <= sr_rec_start;
end
end
sr_rec_start : begin
rf_push <= 1'b0;
if (rcounter16_eq_7) // check the pulse
if (srx_pad_i==1'b1) // no start bit
rstate <= sr_idle;
else // start bit detected
rstate <= sr_rec_prepare;
rcounter16 <= rcounter16_minus_1;
end
sr_rec_prepare:begin
case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word
2'b00 : rbit_counter <= 3'b100;
2'b01 : rbit_counter <= 3'b101;
2'b10 : rbit_counter <= 3'b110;
2'b11 : rbit_counter <= 3'b111;
endcase
if (rcounter16_eq_0)
begin
rstate <= sr_rec_bit;
rcounter16 <= 4'b1110;
rshift <= 0;
end
else
rstate <= sr_rec_prepare;
rcounter16 <= rcounter16_minus_1;
end
sr_rec_bit : begin
if (rcounter16_eq_0)
rstate <= sr_end_bit;
if (rcounter16_eq_7) // read the bit
case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word
2'b00 : rshift[4:0] <= {srx_pad_i, rshift[4:1]};
2'b01 : rshift[5:0] <= {srx_pad_i, rshift[5:1]};
2'b10 : rshift[6:0] <= {srx_pad_i, rshift[6:1]};
2'b11 : rshift[7:0] <= {srx_pad_i, rshift[7:1]};
endcase
rcounter16 <= rcounter16_minus_1;
end
sr_end_bit : begin
if (rbit_counter==3'b0) // no more bits in word
if (lcr[`UART_LC_PE]) // choose state based on parity
rstate <= sr_rec_parity;
else
begin
rstate <= sr_rec_stop;
rparity_error <= 1'b0; // no parity - no error :)
end
else // else we have more bits to read
begin
rstate <= sr_rec_bit;
rbit_counter <= rbit_counter - 3'd1;
end
rcounter16 <= 4'b1110;
end
sr_rec_parity: begin
if (rcounter16_eq_7) // read the parity
begin
rparity <= srx_pad_i;
rstate <= sr_ca_lc_parity;
end
rcounter16 <= rcounter16_minus_1;
end
sr_ca_lc_parity : begin // rcounter equals 6
rcounter16 <= rcounter16_minus_1;
rparity_xor <= ^{rshift,rparity}; // calculate parity on all incoming data
rstate <= sr_check_parity;
end
sr_check_parity: begin // rcounter equals 5
case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
2'b00: rparity_error <= rparity_xor == 0; // no error if parity 1
2'b01: rparity_error <= ~rparity; // parity should sticked to 1
2'b10: rparity_error <= rparity_xor == 1; // error if parity is odd
2'b11: rparity_error <= rparity; // parity should be sticked to 0
endcase
rcounter16 <= rcounter16_minus_1;
rstate <= sr_wait1;
end
sr_wait1 : if (rcounter16_eq_0)
begin
rstate <= sr_rec_stop;
rcounter16 <= 4'b1110;
end
else
rcounter16 <= rcounter16_minus_1;
sr_rec_stop : begin
if (rcounter16_eq_7) // read the parity
begin
rframing_error <= !srx_pad_i; // no framing error if input is 1 (stop bit)
rstate <= sr_push;
end
rcounter16 <= rcounter16_minus_1;
end
sr_push : begin
///////////////////////////////////////
// $display($time, ": received: %b", rf_data_in);
if(srx_pad_i | break_error)
begin
if(break_error)
rf_data_in <= {8'b0, 3'b100}; // break input (empty character) to receiver FIFO
else
rf_data_in <= {rshift, 1'b0, rparity_error, rframing_error};
rf_push <= 1'b1;
rstate <= sr_idle;
end
else if(~rframing_error) // There's always a framing before break_error -> wait for break or srx_pad_i
begin
rf_data_in <= {rshift, 1'b0, rparity_error, rframing_error};
rf_push <= 1'b1;
rcounter16 <= 4'b1110;
rstate <= sr_rec_start;
end
end
default : rstate <= sr_idle;
endcase
end // if (enable)
end // always of receiver
always @ (posedge clk or posedge wb_rst_i)
begin
if(wb_rst_i)
rf_push_q <= 0;
else
rf_push_q <= rf_push;
end
assign rf_push_pulse = rf_push & ~rf_push_q;
//
// Break condition detection.
// Works in conjuction with the receiver state machine
reg [9:0] toc_value; // value to be set to timeout counter
always @(lcr)
case (lcr[3:0])
4'b0000 : toc_value = 447; // 7 bits
4'b0100 : toc_value = 479; // 7.5 bits
4'b0001, 4'b1000 : toc_value = 511; // 8 bits
4'b1100 : toc_value = 543; // 8.5 bits
4'b0010, 4'b0101, 4'b1001 : toc_value = 575; // 9 bits
4'b0011, 4'b0110, 4'b1010, 4'b1101 : toc_value = 639; // 10 bits
4'b0111, 4'b1011, 4'b1110 : toc_value = 703; // 11 bits
4'b1111 : toc_value = 767; // 12 bits
endcase // case(lcr[3:0])
wire [7:0] brc_value; // value to be set to break counter
assign brc_value = toc_value[9:2]; // the same as timeout but 1 insead of 4 character times
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
counter_b <= 8'd159;
else
if (srx_pad_i)
counter_b <= brc_value; // character time length - 1
else
if(enable & counter_b != 8'b0) // only work on enable times break not reached.
counter_b <= counter_b - 8'd1; // decrement break counter
end // always of break condition detection
///
/// Timeout condition detection
reg [9:0] counter_t; // counts the timeout condition clocks
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
counter_t <= 10'd639; // 10 bits for the default 8N1
else
if(rf_push_pulse || rf_pop || rf_count == 0) // counter is reset when RX FIFO is empty, accessed or above trigger level
counter_t <= toc_value;
else
if (enable && counter_t != 10'b0) // we don't want to underflow
counter_t <= counter_t - 10'd1;
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_regs.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// Registers of the uart 16550 core ////
//// ////
//// Known problems (limits): ////
//// Inserts 1 wait state in all WISHBONE transfers ////
//// ////
//// To Do: ////
//// Nothing or verification. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: (See log for the revision history ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.41 2004/05/21 11:44:41 tadejm
// Added synchronizer flops for RX input.
//
// Revision 1.40 2003/06/11 16:37:47 gorban
// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
//
// Revision 1.39 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.38 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.37 2001/12/27 13:24:09 mohor
// lsr[7] was not showing overrun errors.
//
// Revision 1.36 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.35 2001/12/19 08:03:34 mohor
// Warnings cleared.
//
// Revision 1.34 2001/12/19 07:33:54 mohor
// Synplicity was having troubles with the comment.
//
// Revision 1.33 2001/12/17 10:14:43 mohor
// Things related to msr register changed. After THRE IRQ occurs, and one
// character is written to the transmit fifo, the detection of the THRE bit in the
// LSR is delayed for one character time.
//
// Revision 1.32 2001/12/14 13:19:24 mohor
// MSR register fixed.
//
// Revision 1.31 2001/12/14 10:06:58 mohor
// After reset modem status register MSR should be reset.
//
// Revision 1.30 2001/12/13 10:09:13 mohor
// thre irq should be cleared only when being source of interrupt.
//
// Revision 1.29 2001/12/12 09:05:46 mohor
// LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).
//
// Revision 1.28 2001/12/10 19:52:41 gorban
// Scratch register added
//
// Revision 1.27 2001/12/06 14:51:04 gorban
// Bug in LSR[0] is fixed.
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
//
// Revision 1.26 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.25 2001/11/28 19:36:39 gorban
// Fixed: timeout and break didn't pay attention to current data format when counting time
//
// Revision 1.24 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.23 2001/11/12 21:57:29 gorban
// fixed more typo bugs
//
// Revision 1.22 2001/11/12 15:02:28 mohor
// lsr1r error fixed.
//
// Revision 1.21 2001/11/12 14:57:27 mohor
// ti_int_pnd error fixed.
//
// Revision 1.20 2001/11/12 14:50:27 mohor
// ti_int_d error fixed.
//
// Revision 1.19 2001/11/10 12:43:21 gorban
// Logic Synthesis bugs fixed. Some other minor changes
//
// Revision 1.18 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.17 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.16 2001/11/02 09:55:16 mohor
// no message
//
// Revision 1.15 2001/10/31 15:19:22 gorban
// Fixes to break and timeout conditions
//
// Revision 1.14 2001/10/29 17:00:46 gorban
// fixed parity sending and tx_fifo resets over- and underrun
//
// Revision 1.13 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.12 2001/10/19 16:21:40 gorban
// Changes data_out to be synchronous again as it should have been.
//
// Revision 1.11 2001/10/18 20:35:45 gorban
// small fix
//
// Revision 1.10 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.9 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.10 2001/06/23 11:21:48 gorban
// DL made 16-bit long. Fixed transmission/reception bugs.
//
// Revision 1.9 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.8 2001/05/29 20:05:04 gorban
// Fixed some bugs and synthesis problems.
//
// Revision 1.7 2001/05/27 17:37:49 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.6 2001/05/21 19:12:02 gorban
// Corrected some Linter messages.
//
// Revision 1.5 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:11+02 jacob
// Initial revision
//
//
`include "uart_defines.v"
`define UART_DL1 7:0
`define UART_DL2 15:8
module uart_regs
#(parameter SIM = 0)
(clk,
wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_re_i,
// additional signals
modem_inputs,
stx_pad_o, srx_pad_i,
rts_pad_o, dtr_pad_o, int_o
`ifdef UART_HAS_BAUDRATE_OUTPUT
, baud_o
`endif
);
input clk;
input wb_rst_i;
input [2:0] wb_addr_i;
input [7:0] wb_dat_i;
output [7:0] wb_dat_o;
input wb_we_i;
input wb_re_i;
output stx_pad_o;
input srx_pad_i;
input [3:0] modem_inputs;
output rts_pad_o;
output dtr_pad_o;
output int_o;
`ifdef UART_HAS_BAUDRATE_OUTPUT
output baud_o;
`endif
wire [3:0] modem_inputs;
reg enable;
`ifdef UART_HAS_BAUDRATE_OUTPUT
assign baud_o = enable; // baud_o is actually the enable signal
`endif
wire stx_pad_o; // received from transmitter module
wire srx_pad_i;
wire srx_pad;
reg [7:0] wb_dat_o;
wire [2:0] wb_addr_i;
wire [7:0] wb_dat_i;
reg [3:0] ier;
reg [3:0] iir;
reg [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
reg [4:0] mcr;
reg [7:0] lcr;
reg [7:0] msr;
reg [15:0] dl; // 32-bit divisor latch
reg [7:0] scratch; // UART scratch register
reg start_dlc; // activate dlc on writing to UART_DL1
reg lsr_mask_d; // delay for lsr_mask condition
reg msi_reset; // reset MSR 4 lower bits indicator
//reg threi_clear; // THRE interrupt clear flag
reg [15:0] dlc; // 32-bit divisor latch counter
reg int_o;
reg [3:0] trigger_level; // trigger level of the receiver FIFO
reg rx_reset;
reg tx_reset;
wire dlab; // divisor latch access bit
wire cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i; // modem status bits
wire loopback; // loopback bit (MCR bit 4)
wire cts, dsr, ri, dcd; // effective signals
wire cts_c, dsr_c, ri_c, dcd_c; // Complement effective signals (considering loopback)
wire rts_pad_o, dtr_pad_o; // modem control outputs
// LSR bits wires and regs
wire [7:0] lsr;
wire lsr0, lsr1, lsr2, lsr3, lsr4, lsr5, lsr6, lsr7;
reg lsr0r, lsr1r, lsr2r, lsr3r, lsr4r, lsr5r, lsr6r, lsr7r;
wire lsr_mask; // lsr_mask
//
// ASSINGS
//
assign lsr[7:0] = { lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, lsr0r };
assign {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs;
assign {cts, dsr, ri, dcd} = ~{cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
assign {cts_c, dsr_c, ri_c, dcd_c} = loopback ? {mcr[`UART_MC_RTS],mcr[`UART_MC_DTR],mcr[`UART_MC_OUT1],mcr[`UART_MC_OUT2]}
: {cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
assign dlab = lcr[`UART_LC_DL];
assign loopback = mcr[4];
// assign modem outputs
assign rts_pad_o = mcr[`UART_MC_RTS];
assign dtr_pad_o = mcr[`UART_MC_DTR];
// Interrupt signals
wire rls_int; // receiver line status interrupt
wire rda_int; // receiver data available interrupt
wire ti_int; // timeout indicator interrupt
wire thre_int; // transmitter holding register empty interrupt
wire ms_int; // modem status interrupt
// FIFO signals
reg tf_push;
reg rf_pop;
wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
wire rf_error_bit; // an error (parity or framing) is inside the fifo
wire rf_overrun;
wire rf_push_pulse;
wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
wire [2:0] tstate;
wire [3:0] rstate;
wire [9:0] counter_t;
wire thre_set_en; // THRE status is delayed one character time when a character is written to fifo.
reg [7:0] block_cnt; // While counter counts, THRE status is blocked (delayed one character cycle)
reg [7:0] block_value; // One character length minus stop bit
// Transmitter Instance
wire serial_out;
uart_transmitter #(.SIM (SIM)) transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, serial_out, tstate, tf_count, tx_reset, lsr_mask);
// Synchronizing and sampling serial RX input
uart_sync_flops i_uart_sync_flops
(
.rst_i (wb_rst_i),
.clk_i (clk),
.stage1_rst_i (1'b0),
.stage1_clk_en_i (1'b1),
.async_dat_i (srx_pad_i),
.sync_dat_o (srx_pad)
);
defparam i_uart_sync_flops.width = 1;
defparam i_uart_sync_flops.init_value = 1'b1;
// handle loopback
wire serial_in = loopback ? serial_out : srx_pad;
assign stx_pad_o = loopback ? 1'b1 : serial_out;
// Receiver Instance
uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, serial_in, enable,
counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
// Asynchronous reading here because the outputs are sampled in uart_wb.v file
always @(dl or dlab or ier or iir or scratch
or lcr or lsr or msr or rf_data_out or wb_addr_i or wb_re_i) // asynchrounous reading
begin
case (wb_addr_i)
`UART_REG_RB : wb_dat_o = dlab ? dl[`UART_DL1] : rf_data_out[10:3];
`UART_REG_IE : wb_dat_o = dlab ? dl[`UART_DL2] : {4'd0,ier};
`UART_REG_II : wb_dat_o = {4'b1100,iir};
`UART_REG_LC : wb_dat_o = lcr;
`UART_REG_LS : wb_dat_o = lsr;
`UART_REG_MS : wb_dat_o = msr;
`UART_REG_SR : wb_dat_o = scratch;
default: wb_dat_o = 8'b0; // ??
endcase // case(wb_addr_i)
end // always @ (dl or dlab or ier or iir or scratch...
// rf_pop signal handling
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
rf_pop <= 0;
else
if (rf_pop) // restore the signal to 0 after one clock cycle
rf_pop <= 0;
else
if (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab)
rf_pop <= 1; // advance read pointer
end
wire lsr_mask_condition;
wire iir_read;
wire msr_read;
wire fifo_read;
wire fifo_write;
assign lsr_mask_condition = (wb_re_i && wb_addr_i == `UART_REG_LS && !dlab);
assign iir_read = (wb_re_i && wb_addr_i == `UART_REG_II && !dlab);
assign msr_read = (wb_re_i && wb_addr_i == `UART_REG_MS && !dlab);
assign fifo_read = (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab);
assign fifo_write = (wb_we_i && wb_addr_i == `UART_REG_TR && !dlab);
// lsr_mask_d delayed signal handling
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
lsr_mask_d <= 0;
else // reset bits in the Line Status Register
lsr_mask_d <= lsr_mask_condition;
end
// lsr_mask is rise detected
assign lsr_mask = lsr_mask_condition && ~lsr_mask_d;
// msi_reset signal handling
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
msi_reset <= 1;
else
if (msi_reset)
msi_reset <= 0;
else
if (msr_read)
msi_reset <= 1; // reset bits in Modem Status Register
end
//
// WRITES AND RESETS //
//
// Line Control Register
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
lcr <= 8'b00000011; // 8n1 setting
else
if (wb_we_i && wb_addr_i==`UART_REG_LC)
lcr <= wb_dat_i;
// Interrupt Enable Register or UART_DL2
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
begin
ier <= 4'b0000; // no interrupts after reset
`ifdef PRESCALER_PRESET_HARD
dl[`UART_DL2] <= `PRESCALER_HIGH_PRESET;
`else
dl[`UART_DL2] <= 8'b0;
`endif
end
else
if (wb_we_i && wb_addr_i==`UART_REG_IE)
if (dlab)
begin
dl[`UART_DL2] <=
`ifdef PRESCALER_PRESET_HARD
dl[`UART_DL2];
`else
wb_dat_i;
`endif
end
else
ier <= wb_dat_i[3:0]; // ier uses only 4 lsb
// FIFO Control Register and rx_reset, tx_reset signals
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) begin
fcr <= 2'b11;
rx_reset <= 0;
tx_reset <= 0;
end else
if (wb_we_i && wb_addr_i==`UART_REG_FC) begin
fcr <= wb_dat_i[7:6];
rx_reset <= wb_dat_i[1];
tx_reset <= wb_dat_i[2];
end else begin
rx_reset <= 0;
tx_reset <= 0;
end
// Modem Control Register
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
mcr <= 5'b0;
else
if (wb_we_i && wb_addr_i==`UART_REG_MC)
mcr <= wb_dat_i[4:0];
// Scratch register
// Line Control Register
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
scratch <= 0; // 8n1 setting
else
if (wb_we_i && wb_addr_i==`UART_REG_SR)
scratch <= wb_dat_i;
// TX_FIFO or UART_DL1
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
begin
`ifdef PRESCALER_PRESET_HARD
dl[`UART_DL1] <= `PRESCALER_LOW_PRESET;
`else
dl[`UART_DL1] <= 8'b0;
`endif
tf_push <= 1'b0;
start_dlc <= 1'b0;
end
else
if (wb_we_i && wb_addr_i==`UART_REG_TR)
if (dlab)
begin
`ifdef PRESCALER_PRESET_HARD
dl[`UART_DL1] <= dl[`UART_DL1];
`else
dl[`UART_DL1] <= wb_dat_i;
`endif
start_dlc <= 1'b1; // enable DL counter
tf_push <= 1'b0;
end
else
begin
tf_push <= 1'b1;
start_dlc <= 1'b0;
end // else: !if(dlab)
else
begin
start_dlc <= 1'b0;
tf_push <= 1'b0;
end // else: !if(dlab)
// Receiver FIFO trigger level selection logic (asynchronous mux)
always @(fcr)
case (fcr[`UART_FC_TL])
2'b00 : trigger_level = 1;
2'b01 : trigger_level = 4;
2'b10 : trigger_level = 8;
2'b11 : trigger_level = 14;
endcase // case(fcr[`UART_FC_TL])
//
// STATUS REGISTERS //
//
// Modem Status Register
reg [3:0] delayed_modem_signals;
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
begin
msr <= 0;
delayed_modem_signals[3:0] <= 0;
end
else begin
msr[`UART_MS_DDCD:`UART_MS_DCTS] <= msi_reset ? 4'b0 :
msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ delayed_modem_signals[3:0]);
msr[`UART_MS_CDCD:`UART_MS_CCTS] <= {dcd_c, ri_c, dsr_c, cts_c};
delayed_modem_signals[3:0] <= {dcd, ri, dsr, cts};
end
end
// Line Status Register
// activation conditions
assign lsr0 = (rf_count==0 && rf_push_pulse); // data in receiver fifo available set condition
assign lsr1 = rf_overrun; // Receiver overrun error
assign lsr2 = rf_data_out[1]; // parity error bit
assign lsr3 = rf_data_out[0]; // framing error bit
assign lsr4 = rf_data_out[2]; // break error in the character
assign lsr5 = (tf_count==5'b0 && thre_set_en); // transmitter fifo is empty
assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate == /*`S_IDLE */ 0)); // transmitter empty
assign lsr7 = rf_error_bit | rf_overrun;
// lsr bit0 (receiver data available)
reg lsr0_d;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr0_d <= 0;
else lsr0_d <= lsr0;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr0r <= 0;
else lsr0r <= (rf_count==1 && rf_pop && !rf_push_pulse || rx_reset) ? 1'b0 : // deassert condition
lsr0r || (lsr0 && ~lsr0_d); // set on rise of lsr0 and keep asserted until deasserted
// lsr bit 1 (receiver overrun)
reg lsr1_d; // delayed
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr1_d <= 0;
else lsr1_d <= lsr1;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr1r <= 0;
else lsr1r <= lsr_mask ? 1'b0 : lsr1r || (lsr1 && ~lsr1_d); // set on rise
// lsr bit 2 (parity error)
reg lsr2_d; // delayed
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr2_d <= 0;
else lsr2_d <= lsr2;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr2r <= 0;
else lsr2r <= lsr_mask ? 1'b0 : lsr2r || (lsr2 && ~lsr2_d); // set on rise
// lsr bit 3 (framing error)
reg lsr3_d; // delayed
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr3_d <= 0;
else lsr3_d <= lsr3;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr3r <= 0;
else lsr3r <= lsr_mask ? 1'b0 : lsr3r || (lsr3 && ~lsr3_d); // set on rise
// lsr bit 4 (break indicator)
reg lsr4_d; // delayed
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr4_d <= 0;
else lsr4_d <= lsr4;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr4r <= 0;
else lsr4r <= lsr_mask ? 1'b0 : lsr4r || (lsr4 && ~lsr4_d);
// lsr bit 5 (transmitter fifo is empty)
reg lsr5_d;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr5_d <= 1;
else lsr5_d <= lsr5;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr5r <= 1;
else lsr5r <= (fifo_write) ? 1'b0 : lsr5r || (lsr5 && ~lsr5_d);
// lsr bit 6 (transmitter empty indicator)
reg lsr6_d;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr6_d <= 1;
else lsr6_d <= lsr6;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr6r <= 1;
else lsr6r <= (fifo_write) ? 1'b0 : lsr6r || (lsr6 && ~lsr6_d);
// lsr bit 7 (error in fifo)
reg lsr7_d;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr7_d <= 0;
else lsr7_d <= lsr7;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr7r <= 0;
else lsr7r <= lsr_mask ? 1'b0 : lsr7r || (lsr7 && ~lsr7_d);
// Frequency divider
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
dlc <= 0;
else
if (start_dlc | ~ (|dlc))
dlc <= dl - 16'd1; // preset counter
else
dlc <= dlc - 16'd1; // decrement counter
end
// Enable signal generation logic
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
enable <= 1'b0;
else
if (|dl & ~(|dlc)) // dl>0 & dlc==0
enable <= 1'b1;
else
enable <= 1'b0;
end
// Delaying THRE status for one character cycle after a character is written to an empty fifo.
always @(lcr)
case (lcr[3:0])
4'b0000 : block_value = 95; // 6 bits
4'b0100 : block_value = 103; // 6.5 bits
4'b0001, 4'b1000 : block_value = 111; // 7 bits
4'b1100 : block_value = 119; // 7.5 bits
4'b0010, 4'b0101, 4'b1001 : block_value = 127; // 8 bits
4'b0011, 4'b0110, 4'b1010, 4'b1101 : block_value = 143; // 9 bits
4'b0111, 4'b1011, 4'b1110 : block_value = 159; // 10 bits
4'b1111 : block_value = 175; // 11 bits
endcase // case(lcr[3:0])
// Counting time of one character minus stop bit
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
block_cnt <= 8'd0;
else
if(lsr5r & fifo_write) // THRE bit set & write to fifo occured
block_cnt <= SIM ? 8'd1 : block_value;
else
if (enable & block_cnt != 8'b0) // only work on enable times
block_cnt <= block_cnt - 8'd1; // decrement break counter
end // always of break condition detection
// Generating THRE status enable signal
assign thre_set_en = ~(|block_cnt);
//
// INTERRUPT LOGIC
//
assign rls_int = ier[`UART_IE_RLS] && (lsr[`UART_LS_OE] || lsr[`UART_LS_PE] || lsr[`UART_LS_FE] || lsr[`UART_LS_BI]);
assign rda_int = ier[`UART_IE_RDA] && (rf_count >= {1'b0,trigger_level});
assign thre_int = ier[`UART_IE_THRE] && lsr[`UART_LS_TFE];
assign ms_int = ier[`UART_IE_MS] && (| msr[3:0]);
assign ti_int = ier[`UART_IE_RDA] && (counter_t == 10'b0) && (|rf_count);
reg rls_int_d;
reg thre_int_d;
reg ms_int_d;
reg ti_int_d;
reg rda_int_d;
// delay lines
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) rls_int_d <= 0;
else rls_int_d <= rls_int;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) rda_int_d <= 0;
else rda_int_d <= rda_int;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) thre_int_d <= 0;
else thre_int_d <= thre_int;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) ms_int_d <= 0;
else ms_int_d <= ms_int;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) ti_int_d <= 0;
else ti_int_d <= ti_int;
// rise detection signals
wire rls_int_rise;
wire thre_int_rise;
wire ms_int_rise;
wire ti_int_rise;
wire rda_int_rise;
assign rda_int_rise = rda_int & ~rda_int_d;
assign rls_int_rise = rls_int & ~rls_int_d;
assign thre_int_rise = thre_int & ~thre_int_d;
assign ms_int_rise = ms_int & ~ms_int_d;
assign ti_int_rise = ti_int & ~ti_int_d;
// interrupt pending flags
reg rls_int_pnd;
reg rda_int_pnd;
reg thre_int_pnd;
reg ms_int_pnd;
reg ti_int_pnd;
// interrupt pending flags assignments
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) rls_int_pnd <= 0;
else
rls_int_pnd <= lsr_mask ? 1'b0 : // reset condition
rls_int_rise ? 1'b1 : // latch condition
rls_int_pnd && ier[`UART_IE_RLS]; // default operation: remove if masked
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) rda_int_pnd <= 0;
else
rda_int_pnd <= ((rf_count == {1'b0,trigger_level}) && fifo_read) ? 1'b0 : // reset condition
rda_int_rise ? 1'b1 : // latch condition
rda_int_pnd && ier[`UART_IE_RDA]; // default operation: remove if masked
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) thre_int_pnd <= 0;
else
thre_int_pnd <= fifo_write || (iir_read & ~iir[`UART_II_IP] & iir[`UART_II_II] == `UART_II_THRE)? 1'b0 :
thre_int_rise ? 1'b1 :
thre_int_pnd && ier[`UART_IE_THRE];
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) ms_int_pnd <= 0;
else
ms_int_pnd <= msr_read ? 1'b0 :
ms_int_rise ? 1'b1 :
ms_int_pnd && ier[`UART_IE_MS];
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) ti_int_pnd <= 0;
else
ti_int_pnd <= fifo_read ? 1'b0 :
ti_int_rise ? 1'b1 :
ti_int_pnd && ier[`UART_IE_RDA];
// end of pending flags
// INT_O logic
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
int_o <= 1'b0;
else
int_o <=
rls_int_pnd ? ~lsr_mask :
rda_int_pnd ? 1'b1 :
ti_int_pnd ? ~fifo_read :
thre_int_pnd ? !(fifo_write & iir_read) :
ms_int_pnd ? ~msr_read :
1'd0; // if no interrupt are pending
end
// Interrupt Identification register
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
iir <= 1;
else
if (rls_int_pnd) // interrupt is pending
begin
iir[`UART_II_II] <= `UART_II_RLS; // set identification register to correct value
iir[`UART_II_IP] <= 1'b0; // and clear the IIR bit 0 (interrupt pending)
end else // the sequence of conditions determines priority of interrupt identification
if (rda_int)
begin
iir[`UART_II_II] <= `UART_II_RDA;
iir[`UART_II_IP] <= 1'b0;
end
else if (ti_int_pnd)
begin
iir[`UART_II_II] <= `UART_II_TI;
iir[`UART_II_IP] <= 1'b0;
end
else if (thre_int_pnd)
begin
iir[`UART_II_II] <= `UART_II_THRE;
iir[`UART_II_IP] <= 1'b0;
end
else if (ms_int_pnd)
begin
iir[`UART_II_II] <= `UART_II_MS;
iir[`UART_II_IP] <= 1'b0;
end else // no interrupt is pending
begin
iir[`UART_II_II] <= 0;
iir[`UART_II_IP] <= 1'b1;
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_rfifo.v (Modified from uart_fifo.v) ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core receiver FIFO ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2002/07/22 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2003/06/11 16:37:47 gorban
// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
//
// Revision 1.2 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.1 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.16 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.15 2001/12/18 09:01:07 mohor
// Bug that was entered in the last update fixed (rx state machine).
//
// Revision 1.14 2001/12/17 14:46:48 mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.13 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.12 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.11 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.10 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.9 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8 2001/08/24 08:48:10 mohor
// FIFO was not cleared after the data was read bug fixed.
//
// Revision 1.7 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.3 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/27 17:37:48 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:12+02 jacob
// Initial revision
//
//
`include "uart_defines.v"
module uart_rfifo (clk,
wb_rst_i, data_in, data_out,
// Control signals
push, // push strobe, active high
pop, // pop strobe, active high
// status signals
overrun,
count,
error_bit,
fifo_reset,
reset_status
);
// FIFO parameters
parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
input clk;
input wb_rst_i;
input push;
input pop;
input [fifo_width-1:0] data_in;
input fifo_reset;
input reset_status;
output [fifo_width-1:0] data_out;
output overrun;
output [fifo_counter_w-1:0] count;
output error_bit;
wire [fifo_width-1:0] data_out;
wire [7:0] data8_out;
// flags FIFO
reg [2:0] fifo[fifo_depth-1:0];
// FIFO pointers
reg [fifo_pointer_w-1:0] top;
reg [fifo_pointer_w-1:0] bottom;
reg [fifo_counter_w-1:0] count;
reg overrun;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 4'h1;
raminfr #(fifo_pointer_w,8,fifo_depth) rfifo
(.clk(clk),
.we(push),
.a(top),
.dpra(bottom),
.di(data_in[fifo_width-1:fifo_width-8]),
.dpo(data8_out)
);
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
begin
top <= 0;
bottom <= 0;
count <= 0;
fifo[0] <= 0;
fifo[1] <= 0;
fifo[2] <= 0;
fifo[3] <= 0;
fifo[4] <= 0;
fifo[5] <= 0;
fifo[6] <= 0;
fifo[7] <= 0;
fifo[8] <= 0;
fifo[9] <= 0;
fifo[10] <= 0;
fifo[11] <= 0;
fifo[12] <= 0;
fifo[13] <= 0;
fifo[14] <= 0;
fifo[15] <= 0;
end
else
if (fifo_reset) begin
top <= 0;
bottom <= 0;
count <= 0;
fifo[0] <= 0;
fifo[1] <= 0;
fifo[2] <= 0;
fifo[3] <= 0;
fifo[4] <= 0;
fifo[5] <= 0;
fifo[6] <= 0;
fifo[7] <= 0;
fifo[8] <= 0;
fifo[9] <= 0;
fifo[10] <= 0;
fifo[11] <= 0;
fifo[12] <= 0;
fifo[13] <= 0;
fifo[14] <= 0;
fifo[15] <= 0;
end
else
begin
case ({push, pop})
2'b10 : if (count<fifo_depth) // overrun condition
begin
top <= top_plus_1;
fifo[top] <= data_in[2:0];
count <= count + 5'd1;
end
2'b01 : if(count>0)
begin
fifo[bottom] <= 0;
bottom <= bottom + 4'd1;
count <= count - 5'd1;
end
2'b11 : begin
bottom <= bottom + 4'd1;
top <= top_plus_1;
fifo[top] <= data_in[2:0];
end
default: ;
endcase
end
end // always
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
overrun <= 1'b0;
else
if(fifo_reset | reset_status)
overrun <= 1'b0;
else
if(push & ~pop & (count==fifo_depth))
overrun <= 1'b1;
end // always
// please note though that data_out is only valid one clock after pop signal
assign data_out = {data8_out,fifo[bottom]};
// Additional logic for detection of error conditions (parity and framing) inside the FIFO
// for the Line Status Register bit 7
wire [2:0] word0 = fifo[0];
wire [2:0] word1 = fifo[1];
wire [2:0] word2 = fifo[2];
wire [2:0] word3 = fifo[3];
wire [2:0] word4 = fifo[4];
wire [2:0] word5 = fifo[5];
wire [2:0] word6 = fifo[6];
wire [2:0] word7 = fifo[7];
wire [2:0] word8 = fifo[8];
wire [2:0] word9 = fifo[9];
wire [2:0] word10 = fifo[10];
wire [2:0] word11 = fifo[11];
wire [2:0] word12 = fifo[12];
wire [2:0] word13 = fifo[13];
wire [2:0] word14 = fifo[14];
wire [2:0] word15 = fifo[15];
// a 1 is returned if any of the error bits in the fifo is 1
assign error_bit = |(word0[2:0] | word1[2:0] | word2[2:0] | word3[2:0] |
word4[2:0] | word5[2:0] | word6[2:0] | word7[2:0] |
word8[2:0] | word9[2:0] | word10[2:0] | word11[2:0] |
word12[2:0] | word13[2:0] | word14[2:0] | word15[2:0] );
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_sync_flops.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core receiver logic ////
//// ////
//// Known problems (limits): ////
//// None known ////
//// ////
//// To Do: ////
//// Thourough testing. ////
//// ////
//// Author(s): ////
//// - Andrej Erzen ([email protected]) ////
//// - Tadej Markovic ([email protected]) ////
//// ////
//// Created: 2004/05/20 ////
//// Last Updated: 2004/05/20 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
module uart_sync_flops
(
// internal signals
rst_i,
clk_i,
stage1_rst_i,
stage1_clk_en_i,
async_dat_i,
sync_dat_o
);
parameter width = 1;
parameter init_value = 1'b0;
input rst_i; // reset input
input clk_i; // clock input
input stage1_rst_i; // synchronous reset for stage 1 FF
input stage1_clk_en_i; // synchronous clock enable for stage 1 FF
input [width-1:0] async_dat_i; // asynchronous data input
output [width-1:0] sync_dat_o; // synchronous data output
//
// Interal signal declarations
//
reg [width-1:0] sync_dat_o;
reg [width-1:0] flop_0;
// first stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
flop_0 <= {width{init_value}};
else
flop_0 <= async_dat_i;
end
// second stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
sync_dat_o <= {width{init_value}};
else if (stage1_rst_i)
sync_dat_o <= {width{init_value}};
else if (stage1_clk_en_i)
sync_dat_o <= flop_0;
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_tfifo.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core transmitter FIFO ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2002/07/22 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.16 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.15 2001/12/18 09:01:07 mohor
// Bug that was entered in the last update fixed (rx state machine).
//
// Revision 1.14 2001/12/17 14:46:48 mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.13 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.12 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.11 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.10 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.9 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8 2001/08/24 08:48:10 mohor
// FIFO was not cleared after the data was read bug fixed.
//
// Revision 1.7 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.3 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/27 17:37:48 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:12+02 jacob
// Initial revision
//
//
`include "uart_defines.v"
module uart_tfifo (clk,
wb_rst_i, data_in, data_out,
// Control signals
push, // push strobe, active high
pop, // pop strobe, active high
// status signals
overrun,
count,
fifo_reset,
reset_status
);
// FIFO parameters
parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
input clk;
input wb_rst_i;
input push;
input pop;
input [fifo_width-1:0] data_in;
input fifo_reset;
input reset_status;
output [fifo_width-1:0] data_out;
output overrun;
output [fifo_counter_w-1:0] count;
wire [fifo_width-1:0] data_out;
// FIFO pointers
reg [fifo_pointer_w-1:0] top;
reg [fifo_pointer_w-1:0] bottom;
reg [fifo_counter_w-1:0] count;
reg overrun;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 4'd1;
raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo
(.clk(clk),
.we(push),
.a(top),
.dpra(bottom),
.di(data_in),
.dpo(data_out)
);
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
begin
top <= 0;
bottom <= 0;
count <= 0;
end
else
if (fifo_reset) begin
top <= 0;
bottom <= 0;
count <= 0;
end
else
begin
case ({push, pop})
2'b10 : if (count<fifo_depth) // overrun condition
begin
top <= top_plus_1;
count <= count + 5'd1;
end
2'b01 : if(count>0)
begin
bottom <= bottom + 4'd1;
count <= count - 5'd1;
end
2'b11 : begin
bottom <= bottom + 4'd1;
top <= top_plus_1;
end
default: ;
endcase
end
end // always
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
overrun <= 1'b0;
else
if(fifo_reset | reset_status)
overrun <= 1'b0;
else
if(push & (count==fifo_depth))
overrun <= 1'b1;
end // always
endmodule
|