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`include "lisnoc_def.vh"
`undef FLIT_WIDTH
`undef FLIT_TYPE_MSB
`undef FLIT_TYPE_WIDTH
`undef FLIT_TYPE_LSB
`undef FLIT_CONTENT_WIDTH
`undef FLIT_CONTENT_MSB
`undef FLIT_CONTENT_LSB
`undef FLIT_DEST_WIDTH
`undef FLIT_DEST_MSB
`undef FLIT_DEST_LSB
`undef PACKET_CLASS_MSB
`undef PACKET_CLASS_WIDTH
`undef PACKET_CLASS_LSB
`undef PACKET_CLASS_DMA
// source address field of header flit
`undef SOURCE_MSB
`undef SOURCE_WIDTH
`undef SOURCE_LSB
// packet id field of header flit
`undef PACKET_ID_MSB
`undef PACKET_ID_WIDTH
`undef PACKET_ID_LSB
`undef PACKET_TYPE_MSB
`undef PACKET_TYPE_WIDTH
`undef PACKET_TYPE_LSB
`undef PACKET_TYPE_L2R_REQ
`undef PACKET_TYPE_R2L_REQ
`undef PACKET_TYPE_L2R_RESP
`undef PACKET_TYPE_R2L_RESP
`undef PACKET_REQ_LAST
`undef PACKET_RESP_LAST
`undef SIZE_MSB
`undef SIZE_WIDTH
`undef SIZE_LSB
`undef DMA_REQUEST_WIDTH
`undef DMA_REQFIELD_LADDR_WIDTH
`undef DMA_REQFIELD_SIZE_WIDTH
`undef DMA_REQFIELD_RTILE_WIDTH
`undef DMA_REQFIELD_RADDR_WIDTH
`undef DMA_REQFIELD_LADDR_MSB
`undef DMA_REQFIELD_LADDR_LSB
`undef DMA_REQFIELD_SIZE_MSB
`undef DMA_REQFIELD_SIZE_LSB
`undef DMA_REQFIELD_RTILE_MSB
`undef DMA_REQFIELD_RTILE_LSB
`undef DMA_REQFIELD_RADDR_MSB
`undef DMA_REQFIELD_RADDR_LSB
`undef DMA_REQFIELD_DIR
`undef DMA_REQUEST_INVALID
`undef DMA_REQUEST_VALID
`undef DMA_REQMASK_WIDTH
`undef DMA_REQMASK_LADDR
`undef DMA_REQMASK_SIZE
`undef DMA_REQMASK_RTILE
`undef DMA_REQMASK_RADDR
`undef DMA_REQMASK_DIR
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* The wishbone slave interface to configure the DMA module.
*
* (c) 2011-2013 by the author(s)
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*
*/
`include "lisnoc_dma_def.vh"
module lisnoc_dma_wbinterface(/*AUTOARG*/
// Outputs
wb_if_dat_o, wb_if_ack_o, if_write_req, if_write_pos,
if_write_select, if_write_en, if_valid_pos, if_valid_set,
if_valid_en, if_validrd_en,
// Inputs
clk, rst, wb_if_adr_i, wb_if_dat_i, wb_if_cyc_i, wb_if_stb_i,
wb_if_we_i, done
);
parameter table_entries = 4;
// localparam table_entries_ptrwidth = $clog2(table_entries);
localparam table_entries_ptrwidth = 2;
parameter tileid = 0; // TODO: remove
input clk,rst;
input [31:0] wb_if_adr_i;
input [31:0] wb_if_dat_i;
input wb_if_cyc_i;
input wb_if_stb_i;
input wb_if_we_i;
output reg [31:0] wb_if_dat_o;
output wb_if_ack_o;
output [`DMA_REQUEST_WIDTH-1:0] if_write_req;
output [table_entries_ptrwidth-1:0] if_write_pos;
output [`DMA_REQMASK_WIDTH-1:0] if_write_select;
output if_write_en;
// Interface read (status) interface
output [table_entries_ptrwidth-1:0] if_valid_pos;
output if_valid_set;
output if_valid_en;
output if_validrd_en;
input [table_entries-1:0] done;
assign if_write_req = { wb_if_dat_i[`DMA_REQFIELD_LADDR_WIDTH-1:0],
wb_if_dat_i[`DMA_REQFIELD_SIZE_WIDTH-1:0],
wb_if_dat_i[`DMA_REQFIELD_RTILE_WIDTH-1:0],
wb_if_dat_i[`DMA_REQFIELD_RADDR_WIDTH-1:0],
wb_if_dat_i[0] };
assign if_write_pos = wb_if_adr_i[table_entries_ptrwidth+4:5]; // ptrwidth MUST be <= 7 (=128 entries)
assign if_write_en = wb_if_cyc_i & wb_if_stb_i & wb_if_we_i;
assign if_valid_pos = wb_if_adr_i[table_entries_ptrwidth+4:5]; // ptrwidth MUST be <= 7 (=128 entries)
assign if_valid_en = wb_if_cyc_i & wb_if_stb_i & (wb_if_adr_i[4:0] == 5'h14) & wb_if_we_i;
assign if_validrd_en = wb_if_cyc_i & wb_if_stb_i & (wb_if_adr_i[4:0] == 5'h14) & ~wb_if_we_i;
assign if_valid_set = wb_if_we_i | (~wb_if_we_i & ~done[if_valid_pos]);
assign wb_if_ack_o = wb_if_cyc_i & wb_if_stb_i;
always @(*) begin
if (wb_if_adr_i[4:0] == 5'h14) begin
wb_if_dat_o = {31'h0,done[if_valid_pos]};
end else begin
wb_if_dat_o = 32'h0;
end
end
genvar i;
// This assumes, that mask and address match
generate
for (i=0;i<`DMA_REQMASK_WIDTH;i=i+1) begin
assign if_write_select[i] = (wb_if_adr_i[4:2] == i);
end
endgenerate
endmodule // lisnoc_dma_wbinterface
`include "lisnoc_dma_undef.vh"
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* The packet buffer is similar to a FIFO but does only signal a flit
* at the output when a complete packet is in the buffer. This relaxes
* backpressure problems that may arise.
*
* (c) 2011-2013 by the author(s)
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*
*/
`include "lisnoc_def.vh"
module lisnoc_packet_buffer(/*AUTOARG*/
// Outputs
in_ready, out_flit, out_valid, out_size,
// Inputs
clk, rst, in_flit, in_valid, out_ready
);
parameter data_width = 32;
localparam flit_width = data_width+2;
parameter fifo_depth = 16;
localparam size_width = $clog2(fifo_depth+1);
localparam READY = 1'b0, BUSY = 1'b1;
//inputs
input clk, rst;
input [flit_width-1:0] in_flit;
input in_valid;
output in_ready;
output [flit_width-1:0] out_flit;
output out_valid;
input out_ready;
output reg [size_width-1:0] out_size;
// Signals for fifo
reg [flit_width-1:0] fifo_data [0:fifo_depth]; //actual fifo
reg [fifo_depth:0] fifo_write_ptr;
reg [fifo_depth:0] last_flits;
wire full_packet;
wire pop;
wire push;
wire [1:0] in_flit_type;
assign in_flit_type = in_flit[flit_width-1:flit_width-2];
wire in_is_last;
assign in_is_last = (in_flit_type == `FLIT_TYPE_LAST) || (in_flit_type == `FLIT_TYPE_SINGLE);
reg [fifo_depth-1:0] valid_flits;
always @(*) begin : valid_flits_comb
integer i;
// Set first element
valid_flits[fifo_depth-1] = fifo_write_ptr[fifo_depth];
for (i=fifo_depth-2;i>=0;i=i-1) begin
valid_flits[i] = fifo_write_ptr[i+1] | valid_flits[i+1];
end
end
assign full_packet = |(last_flits[fifo_depth-1:0] & valid_flits);
assign pop = out_valid & out_ready;
assign push = in_valid & in_ready;
assign out_flit = fifo_data[0];
assign out_valid = full_packet;
assign in_ready = !fifo_write_ptr[fifo_depth];
always @(*) begin : findfirstlast
reg [size_width-1:0] i;
reg [size_width-1:0] s;
reg found;
s = 0;
found = 0;
for (i=0;i<fifo_depth;i=i+1) begin
if (last_flits[i] && !found) begin
s = i+1;
found = 1;
end
end
out_size = s;
end
always @(posedge clk) begin
if (rst) begin
fifo_write_ptr <= {{fifo_depth{1'b0}},1'b1};
end else if (push & !pop) begin
fifo_write_ptr <= fifo_write_ptr << 1;
end else if (!push & pop) begin
fifo_write_ptr <= fifo_write_ptr >> 1;
end
end
always @(posedge clk) begin : shift_register
if (rst) begin
last_flits <= {fifo_depth+1{1'b0}};
end else begin : shift
integer i;
for (i=0;i<fifo_depth-1;i=i+1) begin
if (pop) begin
if (push & fifo_write_ptr[i+1]) begin
fifo_data[i] <= in_flit;
last_flits[i] <= in_is_last;
end else begin
fifo_data[i] <= fifo_data[i+1];
last_flits[i] <= last_flits[i+1];
end
end else if (push & fifo_write_ptr[i]) begin
fifo_data[i] <= in_flit;
last_flits[i] <= in_is_last;
end
end // for (i=0;i<fifo_depth-1;i=i+1)
// Handle last element
if (pop & push & fifo_write_ptr[i+1]) begin
fifo_data[i] <= in_flit;
last_flits[i] <= in_is_last;
end else if (push & fifo_write_ptr[i]) begin
fifo_data[i] <= in_flit;
last_flits[i] <= in_is_last;
end
end
end // block: shift_register
endmodule
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is a deserializer for virtual channels
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
* Alexandra Weber <[email protected]>
*/
// TODO: Make more flexible by lookup vector class->vc
module lisnoc_vc_deserializer(
//output
flit_o, valid_o, ready_for_input,
//input
flit_i, valid_i, ready_for_output,
clk, rst
);
parameter flit_data_width = 32;
parameter flit_type_width = 2;
localparam flit_width = flit_data_width + flit_type_width;
parameter FLIT_TYPE_HEADER = 2'b01;
parameter FLIT_TYPE_PAYLOAD = 2'b00;
parameter FLIT_TYPE_LAST = 2'b10;
parameter FLIT_TYPE_SINGLE = 2'b11;
// every vchannel gets the packets of one class
parameter class_msb = 21;
parameter class_lsb = 20;
parameter class_width = 2;
// number of output vchannels
parameter vchannels = 2;
input clk;
input rst;
// array of readys from the vchannels
input [vchannels-1:0] ready_for_output;
// not-full signal from the fifo
output reg ready_for_input;
// one vchannel in (serialized)
input [flit_width-1:0] flit_i;
input valid_i;
// n-vchannel out (multiple vchannels)
output reg [flit_width-1:0] flit_o;
output reg [vchannels-1:0] valid_o;
reg [flit_width-1:0] nxt_flit_o;
reg [vchannels-1:0] nxt_valid_o;
reg [class_width-1:0] req_vchannel;
reg [class_width-1:0] nxt_req_vchannel;
reg state;
reg nxt_state;
always @ (*) begin: fsm
localparam WAITING = 1'b0;
localparam SENDING = 1'b1;
case (state)
WAITING: begin
nxt_flit_o = 'hx;
nxt_valid_o = {vchannels{1'b0}};
ready_for_input = 1'b0;
if(flit_i[flit_width-1:flit_width-2] == FLIT_TYPE_HEADER ||
flit_i[flit_width-1:flit_width-2] == FLIT_TYPE_SINGLE) begin
nxt_req_vchannel = flit_i[class_msb:class_lsb];
nxt_state = SENDING;
nxt_flit_o = flit_i;
ready_for_input = 1'b1;
nxt_valid_o[nxt_req_vchannel] = 1'b1;
end else begin
nxt_req_vchannel = req_vchannel;
nxt_state = WAITING;
ready_for_input = 1'b0;
end
end
SENDING: begin : sending
nxt_flit_o = flit_o;
nxt_valid_o[req_vchannel] = 1'b1;
if(ready_for_output[req_vchannel] == 1'b1) begin
ready_for_input = 1'b1;
nxt_flit_o = flit_i;
if(flit_o[flit_width-1:flit_width-2] == FLIT_TYPE_SINGLE ||
flit_o[flit_width-1:flit_width-2] == FLIT_TYPE_LAST) begin
nxt_state = WAITING;
nxt_valid_o[nxt_req_vchannel] = 1'b0;
end else begin
nxt_state = SENDING;
end
end else begin
ready_for_input = 1'b0;
nxt_state = state;
nxt_flit_o = flit_o;
end
end
endcase
end
always @ (posedge clk) begin
if(rst == 1'b1) begin
flit_o = 'hx;
valid_o = {vchannels{1'b0}};
state = 1'b0;
end else begin
flit_o = nxt_flit_o;
valid_o = nxt_valid_o;
req_vchannel = nxt_req_vchannel;
state = nxt_state;
end
end
endmodule
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is a multiplexer that muxes several incoming vchannels to a
* single one. It ensures wormhole forwarding in a first-come,
* first-served way. There must not be two valid vchannels at the
* same time, so it cannot be used as an arbiter!
*
* Author(s):
* Michael Tempelmeier <[email protected]>
*/
`include "lisnoc_def.vh"
module lisnoc_vc_multiplexer(/*AUTOARG*/
// Outputs
ready_o, valid_o, data_o,
// Inputs
clk, rst, valid_i, data_i, ready_i
);
parameter vchannels = 3;
parameter flit_width = 32;
input clk;
input rst;
//n-vchannel in
input [vchannels-1:0] valid_i;
output [vchannels-1:0] ready_o;
input [flit_width-1:0] data_i;
//one vchannel out
input ready_i;
output valid_o;
output [flit_width-1:0] data_o;
reg state;
reg nxt_state;
`define STATE_READY 1'b0
`define STATE_VALID 1'b1
reg [vchannels-1 :0] channel_mask;
reg [vchannels-1 :0] nxt_channel_mask;
assign data_o = data_i;
assign valid_o = |(valid_i & channel_mask);
assign ready_o = channel_mask & {vchannels{ready_i}};
always @ (*) begin : fsm_logic
//default:
nxt_state = state;
nxt_channel_mask = channel_mask;
case (state)
`STATE_READY: begin
if (ready_i) begin
if((data_i[flit_width-1:flit_width-2] == `FLIT_TYPE_HEADER) && (|valid_i)) begin
//save the current vchannel if a new packet arrives
//if the packet is a single-flit we don't need this information since there are no
//following flits that have to be served on the same vchannel
nxt_state = `STATE_VALID;
nxt_channel_mask = valid_i; //save the current channel;
end
end
end // case: `STATE_READY
`STATE_VALID: begin
if (ready_i) begin
if((data_i[flit_width-1:flit_width-2] == `FLIT_TYPE_LAST) && (valid_i & channel_mask)) begin
//end of packet - we are ready for a new one
nxt_state = `STATE_READY;
nxt_channel_mask = {vchannels{1'b1}};
end
end
end
default: begin
//nothing
end
endcase // case (state)
end // block: fsm_logic
always @ (posedge clk) begin : fsm_reg
if (rst) begin
state = `STATE_READY;
channel_mask = {vchannels{1'b1}};
end else begin
state = nxt_state;
channel_mask = nxt_channel_mask;
end
end
endmodule // lisnoc_vc_multiplexer
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is a serializer that serializes several incoming vchannels to a
* single one. It ensures wormhole forwarding in a first-come,
* first-served way. There must not be two valid vchannels at the
* same time, so it cannot be used as an arbiter!
*
* Author(s):
* Michael Tempelmeier <[email protected]>
*/
`include "lisnoc_def.vh"
module lisnoc_vc_serializer(/*AUTOARG*/
// Outputs
ready_mvc, valid_ser, data_ser,
// Inputs
clk, rst, valid_mvc, data_mvc, ready_ser
);
parameter vchannels = 3;
parameter flit_width = 32;
input clk;
input rst;
//n-vchannel in (multiple vchannels)
input [vchannels-1:0] valid_mvc;
output [vchannels-1:0] ready_mvc;
input [flit_width-1:0] data_mvc;
//one vchannel out (serialized)
input ready_ser;
output valid_ser;
output [flit_width-1:0] data_ser;
reg state;
reg nxt_state;
localparam STATE_READY = 1'b0;
localparam STATE_VALID = 1'b1;
reg [vchannels-1 :0] channel_mask;
reg [vchannels-1 :0] nxt_channel_mask;
assign data_ser = data_mvc;
assign valid_ser = |(valid_mvc & channel_mask);
assign ready_mvc = channel_mask & {vchannels{ready_ser}};
always @ (*) begin : fsm_logic
//default:
nxt_state = state;
nxt_channel_mask = channel_mask;
case (state)
STATE_READY: begin
if (ready_ser) begin
if((data_mvc[flit_width-1:flit_width-2] == `FLIT_TYPE_HEADER) && (|valid_mvc)) begin
//save the current vchannel if a new packet arrives
//if the packet is a single-flit we don't need this information since there are no
//following flits that have to be served on the same vchannel
nxt_state = STATE_VALID;
nxt_channel_mask = valid_mvc; //save the current channel;
end
end
end // case: STATE_READY
STATE_VALID: begin
if (ready_ser) begin
if((data_mvc[flit_width-1:flit_width-2] == `FLIT_TYPE_LAST) && (valid_mvc & channel_mask)) begin
//end of packet - we are ready for a new one
nxt_state = STATE_READY;
nxt_channel_mask = {vchannels{1'b1}};
end
end
end
default: begin
//nothing
end
endcase // case (state)
end // block: fsm_logic
always @ (posedge clk) begin : fsm_reg
if (rst) begin
state = STATE_READY;
channel_mask = {vchannels{1'b1}};
end else begin
state = nxt_state;
channel_mask = nxt_channel_mask;
end
end
endmodule // lisnoc_vc_multiplexer
|
/* Copyright (c) 2012-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* The wishbone slave interface to access the simple message passing.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*
*/
module mpbuffer
import optimsoc_config::*;
#(parameter config_t CONFIG = 'x,
parameter SIZE = 16,
parameter N = 1
)
(
input clk,
input rst,
output [N*CONFIG.NOC_FLIT_WIDTH-1:0] noc_out_flit,
output [N-1:0] noc_out_last,
output [N-1:0] noc_out_valid,
input [N-1:0] noc_out_ready,
input [N*CONFIG.NOC_FLIT_WIDTH-1:0] noc_in_flit,
input [N-1:0] noc_in_last,
input [N-1:0] noc_in_valid,
output [N-1:0] noc_in_ready,
// Bus side (generic)
input [31:0] bus_addr,
input bus_we,
input bus_en,
input [31:0] bus_data_in,
output reg [31:0] bus_data_out,
output bus_ack,
output bus_err,
output irq
);
wire [N:0] bus_sel_mod;
wire [N:0] bus_err_mod;
wire [N:0] bus_ack_mod;
wire [N:0][31:0] bus_data_mod;
wire [N-1:0] irq_mod;
genvar n;
generate
for (n = 0; n <= N; n++) begin
assign bus_sel_mod[n] = (bus_addr[19:13] == n);
end
endgenerate
always @(*) begin
bus_data_out = 32'hx;
for (int i = 0; i <= N; i++) begin
if (bus_sel_mod[i])
bus_data_out = bus_data_mod[i];
end
end
assign bus_ack = |bus_ack_mod;
assign bus_err = |bus_err_mod;
assign irq = |irq_mod;
assign bus_ack_mod[0] = bus_en & bus_sel_mod[0] & !bus_we & (bus_addr[12:0] == 0);
assign bus_err_mod[0] = bus_en & bus_sel_mod[0] & (bus_we | (bus_addr[12:0] != 0));
assign bus_data_mod[0] = N;
generate
for (n = 0; n < N; n++) begin
mpbuffer_endpoint
#(.CONFIG(CONFIG), .SIZE(SIZE))
u_endpoint
(.*,
.noc_out_flit (noc_out_flit[n*CONFIG.NOC_FLIT_WIDTH +: CONFIG.NOC_FLIT_WIDTH]),
.noc_out_last (noc_out_last[n]),
.noc_out_valid (noc_out_valid[n]),
.noc_out_ready (noc_out_ready[n]),
.noc_in_flit (noc_in_flit[n*CONFIG.NOC_FLIT_WIDTH +: CONFIG.NOC_FLIT_WIDTH]),
.noc_in_last (noc_in_last[n]),
.noc_in_valid (noc_in_valid[n]),
.noc_in_ready (noc_in_ready[n]),
.bus_en (bus_en & bus_sel_mod[n+1]),
.bus_data_out (bus_data_mod[n+1]),
.bus_ack (bus_ack_mod[n+1]),
.bus_err (bus_err_mod[n+1]),
.irq (irq_mod[n])
);
end
endgenerate
endmodule // mpbuffer
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* Simple (software-controlled) message passing module.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
/*
*
* +-> Input path <- packet buffer <-- Ingress
* | * raise interrupt (!empty)
* Bus interface --> + * read size flits from packet buffer
* |
* +-> Output path -> packet buffer --> Egress
* * set size
* * write flits to packet buffer
*
* Ingress <---+----- NoC
* |
* Handle control message
* |
* Egress ----+----> NoC
*/
module mpbuffer_endpoint
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
parameter SIZE = 16
)
(
input clk,
input rst,
output reg [CONFIG.NOC_FLIT_WIDTH-1:0] noc_out_flit,
output reg noc_out_last,
output reg noc_out_valid,
input noc_out_ready,
input [CONFIG.NOC_FLIT_WIDTH-1:0] noc_in_flit,
input noc_in_last,
input noc_in_valid,
output reg noc_in_ready,
// Bus side (generic)
input [31:0] bus_addr,
input bus_we,
input bus_en,
input [31:0] bus_data_in,
output reg [31:0] bus_data_out,
output reg bus_ack,
output reg bus_err,
output irq
);
import optimsoc_functions::*;
localparam SIZE_WIDTH = clog2_width(SIZE);
// Connect from the outgoing state machine to the packet buffer
wire [CONFIG.NOC_FLIT_WIDTH-1:0] out_flit;
reg out_last;
reg out_valid;
wire out_ready;
wire [CONFIG.NOC_FLIT_WIDTH-1:0] in_flit;
wire in_last;
wire in_valid;
reg in_ready;
reg enabled;
reg nxt_enabled;
assign irq = in_valid;
assign out_flit = bus_data_in;
reg if_fifo_in_en;
reg if_fifo_in_ack;
reg [31:0] if_fifo_in_data;
reg if_fifo_out_en;
reg if_fifo_out_ack;
/*
* +------+---+------------------------+
* | 0x0 | R | Read from Ingress FIFO |
* +------+---+------------------------+
* | | W | Write to Egress FIFO |
* +------+---+------------------------+
* | 0x4 | W | Enable interface |
* +------+---+------------------------+
* | | R | Status |
* +------+---+------------------------+
*
*/
always @(*) begin
bus_ack = 0;
bus_err = 0;
bus_data_out = 32'hx;
nxt_enabled = enabled;
if_fifo_in_en = 1'b0;
if_fifo_out_en = 1'b0;
if (bus_en) begin
if (bus_addr[5:2] == 4'h0) begin
if (!bus_we) begin
if_fifo_in_en = 1'b1;
bus_ack = if_fifo_in_ack;
bus_data_out = if_fifo_in_data;
end else begin
if_fifo_out_en = 1'b1;
bus_ack = if_fifo_out_ack;
end
end else if (bus_addr[5:2] == 4'h1) begin
bus_ack = 1'b1;
if (bus_we) begin
nxt_enabled = 1'b1;
end else begin
bus_data_out = {30'h0, noc_out_valid, in_valid};
end
end else begin
bus_err = 1'b1;
end
end // if (bus_en)
end // always @ begin
always @(posedge clk) begin
if (rst) begin
enabled <= 1'b0;
end else begin
enabled <= nxt_enabled;
end
end
/**
* Simple writes to 0x0
* * Start transfer and set size S
* * For S flits: Write flit
*/
// State register
reg [1:0] state_out;
reg [1:0] nxt_state_out;
reg state_in;
reg nxt_state_in;
// Size register that is also used to count down the remaining
// flits to be send out
reg [SIZE_WIDTH-1:0] size_out;
reg [SIZE_WIDTH-1:0] nxt_size_out;
wire [SIZE_WIDTH:0] size_in;
// States of output state machine
localparam OUT_IDLE = 0;
localparam OUT_FIRST = 1;
localparam OUT_PAYLOAD = 2;
// States of input state machine
localparam IN_IDLE = 0;
localparam IN_FLIT = 1;
// Combinational part of input state machine
always @(*) begin
in_ready = 1'b0;
if_fifo_in_ack = 1'b0;
if_fifo_in_data = 32'hx;
nxt_state_in = state_in;
case(state_in)
IN_IDLE: begin
if (if_fifo_in_en) begin
if (in_valid) begin
if_fifo_in_data = {{31-SIZE_WIDTH{1'b0}},size_in};
if_fifo_in_ack = 1'b1;
if (size_in!=0) begin
nxt_state_in = IN_FLIT;
end
end else begin
if_fifo_in_data = 0;
if_fifo_in_ack = 1'b1;
nxt_state_in = IN_IDLE;
end
end else begin
nxt_state_in = IN_IDLE;
end
end
IN_FLIT: begin
if (if_fifo_in_en) begin
if_fifo_in_data = in_flit[31:0];
in_ready = 1'b1;
if_fifo_in_ack = 1'b1;
if (size_in==1) begin
nxt_state_in = IN_IDLE;
end else begin
nxt_state_in = IN_FLIT;
end
end else begin
nxt_state_in = IN_FLIT;
end
end // case: IN_FLIT
default: begin
nxt_state_in = IN_IDLE;
end
endcase
end
// Combinational part of output state machine
always @(*) begin
// default values
out_valid = 1'b0; // no flit
nxt_size_out = size_out; // keep size
if_fifo_out_ack = 1'b0; // don't acknowledge
out_last = 1'bx; // Default is undefined
case(state_out)
OUT_IDLE: begin
// Transition from IDLE to FIRST
// when write on bus, which is the size
if (if_fifo_out_en) begin
// Store the written value as size
nxt_size_out = bus_data_in[SIZE_WIDTH-1:0];
// Acknowledge to the bus
if_fifo_out_ack = 1'b1;
nxt_state_out = OUT_FIRST;
end else begin
nxt_state_out = OUT_IDLE;
end
end
OUT_FIRST: begin
// The first flit is written from the bus now.
// This can be either the only flit (size==1)
// or a further flits will follow.
// Forward the flits to the packet buffer.
if (if_fifo_out_en) begin
// When the bus writes, the data is statically assigned
// to out_flit. Set out_valid to signal the flit should
// be output
out_valid = 1'b1;
if (size_out==1) begin
out_last = 1'b1;
end
if (out_ready) begin
// When the output packet buffer is ready this cycle
// the flit has been stored in the packet buffer
// Decrement size
nxt_size_out = size_out-1;
// Acknowledge to the bus
if_fifo_out_ack = 1'b1;
if (size_out==1) begin
// When this was the only flit, go to IDLE again
nxt_state_out = OUT_IDLE;
end else begin
// Otherwise accept further flis as payload
nxt_state_out = OUT_PAYLOAD;
end
end else begin // if (out_ready)
// If the packet buffer is not ready, we simply hold
// the data and valid and wait another cycle for the
// packet buffer to become ready
nxt_state_out = OUT_FIRST;
end
end else begin // if (bus_we && bus_en)
// Wait for the bus
nxt_state_out = OUT_FIRST;
end
end
OUT_PAYLOAD: begin
// After the first flit (HEADER) further flits are
// forwarded in this state. The essential difference to the
// FIRST state is in the output type which can here be
// PAYLOAD or LAST
if (bus_we && bus_en) begin
// When the bus writes, the data is statically assigned
// to out_flit. Set out_valid to signal the flit should
// be output
out_valid = 1'b1;
if (size_out==1) begin
out_last = 1'b1;
end
if (out_ready) begin
// When the output packet buffer is ready this cycle
// the flit has been stored in the packet buffer
// Decrement size
nxt_size_out = size_out-1;
// Acknowledge to the bus
if_fifo_out_ack = 1'b1;
if (size_out==1) begin
// When this was the last flit, go to IDLE again
nxt_state_out = OUT_IDLE;
end else begin
// Otherwise accept further flis as payload
nxt_state_out = OUT_PAYLOAD;
end
end else begin // if (out_ready)
// If the packet buffer is not ready, we simply hold
// the data and valid and wait another cycle for the
// packet buffer to become ready
nxt_state_out = OUT_PAYLOAD;
end
end else begin // if (bus_we && bus_en)
// Wait for the bus
nxt_state_out = OUT_PAYLOAD;
end
end
default: begin
// Defaulting to go to idle
nxt_state_out = OUT_IDLE;
end
endcase
end
// Sequential part of both state machines
always @(posedge clk) begin
if (rst) begin
state_out <= OUT_IDLE; // Start in idle state
// size does not require a reset value (not used before set)
state_in <= IN_IDLE;
end else begin
// Register combinational values
state_out <= nxt_state_out;
size_out <= nxt_size_out;
state_in <= nxt_state_in;
end
end
reg [CONFIG.NOC_FLIT_WIDTH-1:0] ingress_flit;
reg ingress_last;
reg ingress_valid;
wire ingress_ready;
wire [CONFIG.NOC_FLIT_WIDTH-1:0] egress_flit;
wire egress_last;
wire egress_valid;
reg egress_ready;
reg [CONFIG.NOC_FLIT_WIDTH-1:0] control_flit;
reg [CONFIG.NOC_FLIT_WIDTH-1:0] nxt_control_flit;
reg control_pending;
reg nxt_control_pending;
always @(*) begin
noc_in_ready = !control_pending & ingress_ready;
ingress_flit = noc_in_flit;
nxt_control_pending = control_pending;
nxt_control_flit = control_flit;
// Ingress part
ingress_valid = noc_in_valid;
ingress_last = noc_in_last;
if ((noc_in_valid & !control_pending) &&
(noc_in_flit[26:24] == 3'b111) &&
!noc_in_flit[0]) begin
nxt_control_pending = 1'b1;
nxt_control_flit[31:27] = noc_in_flit[23:19];
nxt_control_flit[26:24] = 3'b111;
nxt_control_flit[23:19] = noc_in_flit[31:27];
nxt_control_flit[18:2] = noc_in_flit[18:2];
nxt_control_flit[1] = enabled;
nxt_control_flit[0] = 1'b1;
ingress_valid = 1'b0;
ingress_last = 1'b1;
end
// Egress part
if (egress_valid & !egress_last) begin
egress_ready = noc_out_ready;
noc_out_valid = egress_valid;
noc_out_flit = egress_flit;
noc_out_last = egress_last;
end else if (control_pending) begin
egress_ready = 1'b0;
noc_out_valid = 1'b1;
noc_out_flit = control_flit;
noc_out_last = 1'b1;
if (noc_out_ready) begin
nxt_control_pending = 1'b0;
end
end else begin
egress_ready = noc_out_ready;
noc_out_valid = egress_valid;
noc_out_last = egress_last;
noc_out_flit = egress_flit;
end
end // always @ begin
always @(posedge clk) begin
if (rst) begin
control_pending <= 1'b0;
control_flit <= {CONFIG.NOC_FLIT_WIDTH{1'hx}};
end else begin
control_pending <= nxt_control_pending;
control_flit <= nxt_control_flit;
end
end
// The output packet buffer
noc_buffer
#(.DEPTH(SIZE), .FLIT_WIDTH(CONFIG.NOC_FLIT_WIDTH), .FULLPACKET(1))
u_packetbuffer_out(.*,
.in_ready (out_ready),
.in_flit (out_flit),
.in_last (out_last),
.in_valid (out_valid),
.packet_size (),
.out_flit (egress_flit),
.out_last (egress_last),
.out_valid (egress_valid),
.out_ready (egress_ready));
// The input packet buffer
noc_buffer
#(.DEPTH(SIZE), .FLIT_WIDTH(CONFIG.NOC_FLIT_WIDTH), .FULLPACKET(1))
u_packetbuffer_in(.*,
.in_ready (ingress_ready),
.in_flit (ingress_flit),
.in_last (ingress_last),
.in_valid (ingress_valid),
.packet_size (size_in),
.out_flit (in_flit),
.out_last (in_last),
.out_valid (in_valid),
.out_ready (in_ready));
endmodule // mpbuffer_endpoint
|
/* Copyright (c) 2012-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* The wishbone slave interface to access the simple message passing.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*
*/
module mpbuffer_wb
import optimsoc_config::*;
#(parameter config_t CONFIG = 'x,
parameter SIZE = 16,
parameter N = 1
)
(
input clk,
input rst,
output [N*CONFIG.NOC_FLIT_WIDTH-1:0] noc_out_flit,
output [N-1:0] noc_out_last,
output [N-1:0] noc_out_valid,
input [N-1:0] noc_out_ready,
input [N*CONFIG.NOC_FLIT_WIDTH-1:0] noc_in_flit,
input [N-1:0] noc_in_last,
input [N-1:0] noc_in_valid,
output [N-1:0] noc_in_ready,
input [31:0] wb_adr_i,
input wb_we_i,
input wb_cyc_i,
input wb_stb_i,
input [31:0] wb_dat_i,
output [31:0] wb_dat_o,
output wb_ack_o,
output wb_err_o,
output irq
);
// Bus side (generic)
wire [31:0] bus_addr;
wire bus_we;
wire bus_en;
wire [31:0] bus_data_in;
wire [31:0] bus_data_out;
wire bus_ack;
wire bus_err;
assign bus_addr = wb_adr_i;
assign bus_we = wb_we_i;
assign bus_en = wb_cyc_i & wb_stb_i;
assign bus_data_in = wb_dat_i;
assign wb_dat_o = bus_data_out;
assign wb_ack_o = bus_ack;
assign wb_err_o = bus_err;
mpbuffer
#(.CONFIG(CONFIG),
.SIZE(SIZE), .N(N))
u_buffer(.*);
endmodule // mpbuffer_wb
|
/* Copyright (c) 2013-2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This modules provides the configuration information of the network
* adapter to the software via memory mapped registers.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
/*
* BASE+
* +----------------------------+
* | 0x0 R: tile id |
* +----------------------------+
* | 0x4 R: number of tiles |
* +----------------------------+
* | 0x8 R: |
* +----------------------------+
* | 0xc R: configuration |
* | bit 0: mp_simple |
* | bit 1: dma |
* +----------------------------+
* | 0x10 R: core base id |
* +----------------------------+
* | 0x14 R: |
* +----------------------------+
* | 0x18 R: domain core number |
* +----------------------------+
* | 0x1c R: global memory size |
* +----------------------------+
* | 0x20 R: global memory tile |
* +----------------------------+
* | 0x24 R: local memory size |
* +----------------------------+
* | 0x28 R: number of compute |
* | tiles |
* +----------------------------+
* | 0x2c R: read a random seed |
* +----------------------------+
* .
* .
* +----------------------------+
* | 0x200 R: list of compute |
* | tiles |
* +----------------------------+
*/
module networkadapter_conf
import optimsoc_config::*;
#(parameter config_t CONFIG = 'x,
parameter TILEID = 'x,
parameter COREBASE = 'x
)
(
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
cdc_conf, cdc_enable,
`endif
`endif
/*AUTOARG*/
// Outputs
data, ack, rty, err,
// Inputs
clk, rst, adr, we, data_i
);
reg [31:0] seed = 0;
`ifdef verilator
initial begin
seed = $random();
end
`endif
localparam REG_TILEID = 0;
localparam REG_NUMTILES = 1;
localparam REG_CONF = 3;
localparam REG_COREBASE = 4;
localparam REG_DOMAIN_NUMCORES = 6;
localparam REG_GMEM_SIZE = 7;
localparam REG_GMEM_TILE = 8;
localparam REG_LMEM_SIZE = 9;
localparam REG_NUMCTS = 10;
localparam REG_SEED = 11;
localparam REG_CDC = 10'h40;
localparam REG_CDC_DYN = 10'h41;
localparam REG_CDC_CONF = 10'h42;
localparam REG_CTLIST = 10'h80;
localparam REGBIT_CONF_MPSIMPLE = 0;
localparam REGBIT_CONF_DMA = 1;
input clk;
input rst;
input [15:0] adr;
input we;
input [31:0] data_i;
output reg [31:0] data;
output ack;
output rty;
output err;
assign ack = ~|adr[15:12];
assign err = ~ack;
assign rty = 1'b0;
// CDC configuration register
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
output reg [2:0] cdc_conf;
output reg cdc_enable;
`endif
`endif
wire [15:0] ctlist_vector[0:63];
genvar i;
generate
for (i=0; i<CONFIG.NUMCTS; i=i+1) begin : gen_ctlist_vector // array is indexed by the desired destination
// The entries of this array are subranges from the parameter, where
// the indexing is reversed (num_dests-i-1)!
assign ctlist_vector[CONFIG.NUMCTS - i - 1] = CONFIG.CTLIST[i];
end
endgenerate
always @(*) begin
if (adr[11:9] == REG_CTLIST[9:7]) begin
if (adr[1]) begin
data = {16'h0,ctlist_vector[adr[6:1]]};
end else begin
data = {ctlist_vector[adr[6:1]],16'h0};
end
end else begin
case (adr[11:2])
REG_TILEID: begin
data = TILEID;
end
REG_NUMTILES: begin
data = CONFIG.NUMTILES;
end
REG_CONF: begin
data = 32'h0000_0000;
data[REGBIT_CONF_MPSIMPLE] = CONFIG.NA_ENABLE_MPSIMPLE;
data[REGBIT_CONF_DMA] = CONFIG.NA_ENABLE_DMA;
end
REG_COREBASE: begin
data = 32'(COREBASE);
end
REG_DOMAIN_NUMCORES: begin
data = CONFIG.CORES_PER_TILE;
end
REG_GMEM_SIZE: begin
data = CONFIG.GMEM_SIZE;
end
REG_GMEM_TILE: begin
data = CONFIG.GMEM_TILE;
end
REG_LMEM_SIZE: begin
data = CONFIG.LMEM_SIZE;
end
REG_NUMCTS: begin
data = CONFIG.NUMCTS;
end
REG_SEED: begin
data = seed;
end
REG_CDC: begin
`ifdef OPTIMSOC_CLOCKDOMAINS
data = 32'b1;
`else
data = 32'b0;
`endif
end
REG_CDC_DYN: begin
`ifdef OPTIMSOC_CDC_DYNAMIC
data = 32'b1;
`else
data = 32'b0;
`endif
end
REG_CDC_CONF: begin
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
data = cdc_conf;
`else
data = 32'hx;
`endif
`else
data = 32'hx;
`endif
end
default: begin
data = 32'hx;
end
endcase // case (adr[11:2])
end
end
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
always @(posedge clk) begin
if (rst) begin
cdc_conf <= `OPTIMSOC_CDC_DYN_DEFAULT;
cdc_enable <= 0;
end else begin
if ((adr[11:2]==REG_CDC_CONF) && we) begin
cdc_conf <= data_i[2:0];
cdc_enable <= 1;
end else begin
cdc_conf <= cdc_conf;
cdc_enable <= 0;
end
end
end // always @ (posedge clk)
`endif // `ifdef OPTIMSOC_CDC_DYNAMIC
`endif // `ifdef OPTIMSOC_CLOCKDOMAINS
endmodule // networkadapter_conf
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the network adapter for compute tiles. It is configurable to
* contain different elements, e.g. message passing or DMA.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
`include "lisnoc_def.vh"
module networkadapter_ct
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
parameter TILEID = 'x,
parameter COREBASE = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH
)
(
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
output [2:0] cdc_conf,
output cdc_enable,
`endif
`endif
input clk, rst,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready,
output [31:0] wbm_adr_o,
output wbm_cyc_o,
output [31:0] wbm_dat_o,
output [3:0] wbm_sel_o,
output wbm_stb_o,
output wbm_we_o,
output wbm_cab_o,
output [2:0] wbm_cti_o,
output [1:0] wbm_bte_o,
input wbm_ack_i,
input wbm_rty_i,
input wbm_err_i,
input [31:0] wbm_dat_i,
input [31:0] wbs_adr_i,
input wbs_cyc_i,
input [31:0] wbs_dat_i,
input [3:0] wbs_sel_i,
input wbs_stb_i,
input wbs_we_i,
input wbs_cab_i,
input [2:0] wbs_cti_i,
input [1:0] wbs_bte_i,
output wbs_ack_o,
output wbs_rty_o,
output wbs_err_o,
output [31:0] wbs_dat_o,
output [1:0] irq
);
// Those are the actual channels from the modules
localparam MODCHANNELS = 4;
localparam C_MPSIMPLE_REQ = 0;
localparam C_MPSIMPLE_RESP = 1;
localparam C_DMA_REQ = 2;
localparam C_DMA_RESP = 3;
wire [MODCHANNELS-1:0] mod_out_ready;
wire [MODCHANNELS-1:0] mod_out_valid;
wire [MODCHANNELS-1:0] mod_out_last;
wire [MODCHANNELS-1:0][FLIT_WIDTH-1:0] mod_out_flit;
wire [MODCHANNELS-1:0] mod_in_ready;
wire [MODCHANNELS-1:0] mod_in_valid;
wire [MODCHANNELS-1:0] mod_in_last;
wire [MODCHANNELS-1:0][FLIT_WIDTH-1:0] mod_in_flit;
// The different interfaces at the bus slave
// slave 0: configuration
// NABASE + 0x000000
// slave 1: mp_simple
// NABASE + 0x100000
// slave 2: dma
// NABASE + 0x200000
// If a slave is not present there is a gap
localparam SLAVES = 3; // This is the number of maximum slaves
localparam ID_CONF = 0;
localparam ID_MPSIMPLE = 1;
localparam ID_DMA = 2;
wire [24*SLAVES-1:0] wbif_adr_i;
wire [32*SLAVES-1:0] wbif_dat_i;
wire [SLAVES-1:0] wbif_cyc_i;
wire [SLAVES-1:0] wbif_stb_i;
wire [4*SLAVES-1:0] wbif_sel_i;
wire [SLAVES-1:0] wbif_we_i;
wire [SLAVES*3-1:0] wbif_cti_i;
wire [SLAVES*2-1:0] wbif_bte_i;
wire [32*SLAVES-1:0] wbif_dat_o;
wire [SLAVES-1:0] wbif_ack_o;
wire [SLAVES-1:0] wbif_err_o;
wire [SLAVES-1:0] wbif_rty_o;
wb_decode
#(.SLAVES(3), .DATA_WIDTH(32), .ADDR_WIDTH(24),
.S0_RANGE_WIDTH(4), .S0_RANGE_MATCH(4'h0),
.S1_RANGE_WIDTH(4), .S1_RANGE_MATCH(4'h1),
.S2_RANGE_WIDTH(4), .S2_RANGE_MATCH(4'h2)
)
u_slavedecode
(.clk_i (clk),
.rst_i (rst),
.m_adr_i (wbs_adr_i[23:0]),
.m_dat_i (wbs_dat_i),
.m_cyc_i (wbs_cyc_i),
.m_stb_i (wbs_stb_i),
.m_sel_i (wbs_sel_i),
.m_we_i (wbs_we_i),
.m_cti_i (wbs_cti_i),
.m_bte_i (wbs_bte_i),
.m_dat_o (wbs_dat_o),
.m_ack_o (wbs_ack_o),
.m_err_o (wbs_err_o),
.m_rty_o (wbs_rty_o),
.s_adr_o (wbif_adr_i),
.s_dat_o (wbif_dat_i),
.s_cyc_o (wbif_cyc_i),
.s_stb_o (wbif_stb_i),
.s_sel_o (wbif_sel_i),
.s_we_o (wbif_we_i),
.s_cti_o (wbif_cti_i),
.s_bte_o (wbif_bte_i),
.s_dat_i (wbif_dat_o),
.s_ack_i (wbif_ack_o),
.s_err_i (wbif_err_o),
.s_rty_i (wbif_rty_o));
networkadapter_conf
#(.CONFIG (CONFIG),
.TILEID (TILEID),
.COREBASE (COREBASE))
u_conf(
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
.cdc_conf (cdc_conf[2:0]),
.cdc_enable (cdc_enable),
`endif
`endif
// Outputs
.data (wbif_dat_o[ID_CONF*32 +: 32]),
.ack (wbif_ack_o[ID_CONF]),
.rty (wbif_rty_o[ID_CONF]),
.err (wbif_err_o[ID_CONF]),
// Inputs
.clk (clk),
.rst (rst),
.adr (wbs_adr_i[15:0]),
.we (wbs_cyc_i & wbs_stb_i & wbs_we_i),
.data_i (wbif_dat_i[ID_CONF*32 +: 32]));
// just wire them statically for the moment
assign wbif_rty_o[ID_MPSIMPLE] = 1'b0;
mpbuffer_wb
#(.CONFIG(CONFIG),.N(2),.SIZE(16))
u_mpbuffer
(.*,
.noc_out_flit ({mod_out_flit[C_MPSIMPLE_RESP], mod_out_flit[C_MPSIMPLE_REQ]}),
.noc_out_last ({mod_out_last[C_MPSIMPLE_RESP], mod_out_last[C_MPSIMPLE_REQ]}),
.noc_out_valid ({mod_out_valid[C_MPSIMPLE_RESP], mod_out_valid[C_MPSIMPLE_REQ]}),
.noc_out_ready ({mod_out_ready[C_MPSIMPLE_RESP], mod_out_ready[C_MPSIMPLE_REQ]}),
.noc_in_flit ({mod_in_flit[C_MPSIMPLE_RESP], mod_in_flit[C_MPSIMPLE_REQ]}),
.noc_in_last ({mod_in_last[C_MPSIMPLE_RESP], mod_in_last[C_MPSIMPLE_REQ]}),
.noc_in_valid ({mod_in_valid[C_MPSIMPLE_RESP], mod_in_valid[C_MPSIMPLE_REQ]}),
.noc_in_ready ({mod_in_ready[C_MPSIMPLE_RESP], mod_in_ready[C_MPSIMPLE_REQ]}),
.wb_dat_o (wbif_dat_o[ID_MPSIMPLE*32 +: 32]),
.wb_ack_o (wbif_ack_o[ID_MPSIMPLE]),
.wb_err_o (wbif_err_o[ID_MPSIMPLE]),
.wb_adr_i ({8'h0, wbif_adr_i[ID_MPSIMPLE*24 +: 24]}),
.wb_we_i (wbif_we_i[ID_MPSIMPLE]),
.wb_cyc_i (wbif_cyc_i[ID_MPSIMPLE]),
.wb_stb_i (wbif_stb_i[ID_MPSIMPLE]),
.wb_dat_i (wbif_dat_i[ID_MPSIMPLE*32 +: 32]),
.irq (irq[1])
);
generate
if (CONFIG.NA_ENABLE_DMA) begin
wire [3:0] irq_dma;
assign irq[0] = |irq_dma;
wire [1:0][CONFIG.NOC_FLIT_WIDTH+1:0] dma_in_flit, dma_out_flit;
assign dma_in_flit[0] = {mod_in_last[C_DMA_REQ], 1'b0, mod_in_flit[C_DMA_REQ]};
assign mod_out_last[C_DMA_REQ] = dma_out_flit[0][CONFIG.NOC_FLIT_WIDTH+1];
assign mod_out_flit[C_DMA_REQ] = dma_out_flit[0][CONFIG.NOC_FLIT_WIDTH-1:0];
assign dma_in_flit[1] = {mod_in_last[C_DMA_RESP], 1'b0, mod_in_flit[C_DMA_RESP]};
assign mod_out_last[C_DMA_RESP] = dma_out_flit[1][CONFIG.NOC_FLIT_WIDTH+1];
assign mod_out_flit[C_DMA_RESP] = dma_out_flit[1][CONFIG.NOC_FLIT_WIDTH-1:0];
/* lisnoc_dma AUTO_TEMPLATE(
.noc_in_req_ready (mod_in_ready[C_DMA_REQ]),
.noc_in_req_valid (mod_in_valid[C_DMA_REQ]),
.noc_in_req_flit (dma_in_flit[0]),
.noc_in_resp_ready (mod_in_ready[C_DMA_RESP]),
.noc_in_resp_valid (mod_in_valid[C_DMA_RESP]),
.noc_in_resp_flit (dma_in_flit[1]),
.noc_out_req_ready (mod_out_ready[C_DMA_REQ]),
.noc_out_req_valid (mod_out_valid[C_DMA_REQ]),
.noc_out_req_flit (dma_out_flit[0]),
.noc_out_resp_ready (mod_out_ready[C_DMA_RESP]),
.noc_out_resp_valid (mod_out_valid[C_DMA_RESP]),
.noc_out_resp_flit (dma_out_flit[1]),
.wb_if_dat_\(.*\) (wbif_dat_\1[ID_DMA*32 +: 32]),
.wb_if_adr_i ({8'h0, wbif_adr_i[ID_DMA*24 +: 24]}),
.wb_if_\(.*\) (wbif_\1[ID_DMA]),
.wb_\(.*\) (wbm_\1),
.irq (irq_dma),
); */
lisnoc_dma
#(.tileid(TILEID),.table_entries(CONFIG.NA_DMA_ENTRIES))
u_dma(/*AUTOINST*/
// Outputs
.noc_in_req_ready (mod_in_ready[C_DMA_REQ]), // Templated
.noc_in_resp_ready (mod_in_ready[C_DMA_RESP]), // Templated
.noc_out_req_flit (dma_out_flit[0]), // Templated
.noc_out_req_valid (mod_out_valid[C_DMA_REQ]), // Templated
.noc_out_resp_flit (dma_out_flit[1]), // Templated
.noc_out_resp_valid (mod_out_valid[C_DMA_RESP]), // Templated
.wb_if_dat_o (wbif_dat_o[ID_DMA*32 +: 32]), // Templated
.wb_if_ack_o (wbif_ack_o[ID_DMA]), // Templated
.wb_if_err_o (wbif_err_o[ID_DMA]), // Templated
.wb_if_rty_o (wbif_rty_o[ID_DMA]), // Templated
.wb_adr_o (wbm_adr_o), // Templated
.wb_dat_o (wbm_dat_o), // Templated
.wb_cyc_o (wbm_cyc_o), // Templated
.wb_stb_o (wbm_stb_o), // Templated
.wb_sel_o (wbm_sel_o), // Templated
.wb_we_o (wbm_we_o), // Templated
.wb_cab_o (wbm_cab_o), // Templated
.wb_cti_o (wbm_cti_o), // Templated
.wb_bte_o (wbm_bte_o), // Templated
.irq (irq_dma), // Templated
// Inputs
.clk (clk),
.rst (rst),
.noc_in_req_flit (dma_in_flit[0]), // Templated
.noc_in_req_valid (mod_in_valid[C_DMA_REQ]), // Templated
.noc_in_resp_flit (dma_in_flit[1]), // Templated
.noc_in_resp_valid (mod_in_valid[C_DMA_RESP]), // Templated
.noc_out_req_ready (mod_out_ready[C_DMA_REQ]), // Templated
.noc_out_resp_ready (mod_out_ready[C_DMA_RESP]), // Templated
.wb_if_adr_i ({8'h0, wbif_adr_i[ID_DMA*24 +: 24]}), // Templated
.wb_if_dat_i (wbif_dat_i[ID_DMA*32 +: 32]), // Templated
.wb_if_cyc_i (wbif_cyc_i[ID_DMA]), // Templated
.wb_if_stb_i (wbif_stb_i[ID_DMA]), // Templated
.wb_if_we_i (wbif_we_i[ID_DMA]), // Templated
.wb_dat_i (wbm_dat_i), // Templated
.wb_ack_i (wbm_ack_i)); // Templated
end else begin // if (CONFIG.NA_ENABLE_DMA)
assign irq[0] = 1'b0;
end
endgenerate
wire [1:0][FLIT_WIDTH-1:0] muxed_flit;
wire [1:0] muxed_last, muxed_valid, muxed_ready;
noc_mux
#(.FLIT_WIDTH(FLIT_WIDTH), .CHANNELS(2))
u_mux0
(.*,
.in_flit ({mod_out_flit[C_MPSIMPLE_REQ], mod_out_flit[C_DMA_REQ]}),
.in_last ({mod_out_last[C_MPSIMPLE_REQ], mod_out_last[C_DMA_REQ]}),
.in_valid ({mod_out_valid[C_MPSIMPLE_REQ], mod_out_valid[C_DMA_REQ]}),
.in_ready ({mod_out_ready[C_MPSIMPLE_REQ], mod_out_ready[C_DMA_REQ]}),
.out_flit (muxed_flit[0]),
.out_last (muxed_last[0]),
.out_valid (muxed_valid[0]),
.out_ready (muxed_ready[0]));
noc_mux
#(.FLIT_WIDTH(FLIT_WIDTH), .CHANNELS(2))
u_mux1
(.*,
.in_flit ({mod_out_flit[C_MPSIMPLE_RESP], mod_out_flit[C_DMA_RESP]}),
.in_last ({mod_out_last[C_MPSIMPLE_RESP], mod_out_last[C_DMA_RESP]}),
.in_valid ({mod_out_valid[C_MPSIMPLE_RESP], mod_out_valid[C_DMA_RESP]}),
.in_ready ({mod_out_ready[C_MPSIMPLE_RESP], mod_out_ready[C_DMA_RESP]}),
.out_flit (muxed_flit[1]),
.out_last (muxed_last[1]),
.out_valid (muxed_valid[1]),
.out_ready (muxed_ready[1]));
noc_buffer
#(.FLIT_WIDTH(FLIT_WIDTH), .DEPTH(4))
u_outbuffer0
(.*,
.in_flit (muxed_flit[0]),
.in_last (muxed_last[0]),
.in_valid (muxed_valid[0]),
.in_ready (muxed_ready[0]),
.out_flit (noc_out_flit[0]),
.out_last (noc_out_last[0]),
.out_valid (noc_out_valid[0]),
.out_ready (noc_out_ready[0]),
.packet_size ()
);
noc_buffer
#(.FLIT_WIDTH(FLIT_WIDTH), .DEPTH(4))
u_outbuffer1
(.*,
.in_flit (muxed_flit[1]),
.in_last (muxed_last[1]),
.in_valid (muxed_valid[1]),
.in_ready (muxed_ready[1]),
.out_flit (noc_out_flit[1]),
.out_last (noc_out_last[1]),
.out_valid (noc_out_valid[1]),
.out_ready (noc_out_ready[1]),
.packet_size ()
);
wire [1:0][FLIT_WIDTH-1:0] inbuffer_flit;
wire [1:0] inbuffer_last, inbuffer_valid, inbuffer_ready;
noc_buffer
#(.FLIT_WIDTH(FLIT_WIDTH), .DEPTH(4))
u_inbuffer0
(.*,
.in_flit (noc_in_flit[0]),
.in_last (noc_in_last[0]),
.in_valid (noc_in_valid[0]),
.in_ready (noc_in_ready[0]),
.out_flit (inbuffer_flit[0]),
.out_last (inbuffer_last[0]),
.out_valid (inbuffer_valid[0]),
.out_ready (inbuffer_ready[0]),
.packet_size ()
);
noc_demux
#(.FLIT_WIDTH (FLIT_WIDTH), .CHANNELS (2),
.MAPPING ({ 48'h0, 8'h2, 8'h1 }))
u_demux0
(.*,
.in_flit (inbuffer_flit[0]),
.in_last (inbuffer_last[0]),
.in_valid (inbuffer_valid[0]),
.in_ready (inbuffer_ready[0]),
.out_flit ({mod_in_flit[C_DMA_REQ], mod_in_flit[C_MPSIMPLE_REQ]}),
.out_last ({mod_in_last[C_DMA_REQ], mod_in_last[C_MPSIMPLE_REQ]}),
.out_valid ({mod_in_valid[C_DMA_REQ], mod_in_valid[C_MPSIMPLE_REQ]}),
.out_ready ({mod_in_ready[C_DMA_REQ], mod_in_ready[C_MPSIMPLE_REQ]}));
noc_buffer
#(.FLIT_WIDTH(FLIT_WIDTH), .DEPTH(4))
u_inbuffer1
(.*,
.in_flit (noc_in_flit[1]),
.in_last (noc_in_last[1]),
.in_valid (noc_in_valid[1]),
.in_ready (noc_in_ready[1]),
.out_flit (inbuffer_flit[1]),
.out_last (inbuffer_last[1]),
.out_valid (inbuffer_valid[1]),
.out_ready (inbuffer_ready[1]),
.packet_size ()
);
noc_demux
#(.FLIT_WIDTH (FLIT_WIDTH), .CHANNELS (2),
.MAPPING ({ 48'h0, 8'h2, 8'h1 }))
u_demux1
(.*,
.in_flit (inbuffer_flit[1]),
.in_last (inbuffer_last[1]),
.in_valid (inbuffer_valid[1]),
.in_ready (inbuffer_ready[1]),
.out_flit ({mod_in_flit[C_DMA_RESP], mod_in_flit[C_MPSIMPLE_RESP]}),
.out_last ({mod_in_last[C_DMA_RESP], mod_in_last[C_MPSIMPLE_RESP]}),
.out_valid ({mod_in_valid[C_DMA_RESP], mod_in_valid[C_MPSIMPLE_RESP]}),
.out_ready ({mod_in_ready[C_DMA_RESP], mod_in_ready[C_MPSIMPLE_RESP]}));
endmodule // networkadapter_ct
// Local Variables:
// verilog-library-directories:("../../../../../external/lisnoc/rtl/dma/" "../../../../../external/lisnoc/rtl/mp_simple/" "../../../../../external/lisnoc/rtl/router/" ".")
// verilog-auto-inst-param-value: t
// End:
|
/* Copyright (c) 2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* Buffer for NoC packets
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
* Wei Song <[email protected]>
*/
module noc_buffer
#(parameter FLIT_WIDTH = 32,
parameter DEPTH = 16,
parameter FULLPACKET = 0,
localparam ID_W = $clog2(DEPTH) // the width of the index
)(
input clk,
input rst,
// FIFO input side
input [FLIT_WIDTH-1:0] in_flit,
input in_last,
input in_valid,
output in_ready,
//FIFO output side
output reg [FLIT_WIDTH-1:0] out_flit,
output reg out_last,
output reg out_valid,
input out_ready,
output [ID_W-1:0] packet_size
);
// internal shift register
reg [DEPTH-1:0][FLIT_WIDTH:0] data;
reg [ID_W:0] rp; // read pointer
logic reg_out_valid; // local output valid
logic in_fire, out_fire;
assign in_ready = (rp != DEPTH - 1) || !reg_out_valid;
assign in_fire = in_valid && in_ready;
assign out_fire = out_valid && out_ready;
always_ff @(posedge clk)
if(rst)
reg_out_valid <= 0;
else if(in_valid)
reg_out_valid <= 1;
else if(out_fire && rp == 0)
reg_out_valid <= 0;
always_ff @(posedge clk)
if(rst)
rp <= 0;
else if(in_fire && !out_fire && reg_out_valid)
rp <= rp + 1;
else if(out_fire && !in_fire && rp != 0)
rp <= rp - 1;
always @(posedge clk)
if(in_fire)
data <= {data, {in_last, in_flit}};
generate // SRL does not allow parallel read
if(FULLPACKET != 0) begin
logic [DEPTH-1:0] data_last_buf, data_last_shifted;
always @(posedge clk)
if(rst)
data_last_buf <= 0;
else if(in_fire)
data_last_buf <= {data_last_buf, in_last && in_valid};
// extra logic to get the packet size in a stable manner
assign data_last_shifted = data_last_buf << DEPTH - 1 - rp;
function logic [ID_W:0] find_first_one(input logic [DEPTH-1:0] data);
automatic int i;
for(i=DEPTH-1; i>=0; i--)
if(data[i]) return i;
return DEPTH;
endfunction // size_count
assign packet_size = DEPTH - find_first_one(data_last_shifted);
always_comb begin
out_flit = data[rp][FLIT_WIDTH-1:0];
out_last = data[rp][FLIT_WIDTH];
out_valid = reg_out_valid && |data_last_shifted;
end
end else begin // if (FULLPACKET)
assign packet_size = 0;
always_comb begin
out_flit = data[rp][FLIT_WIDTH-1:0];
out_last = data[rp][FLIT_WIDTH];
out_valid = reg_out_valid;
end
end
endgenerate
endmodule // noc_buffer
|
/* Copyright (c) 2015-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* Route packets to an output port depending on the class
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module noc_demux
import optimsoc_config::*;
import optimsoc_constants::*;
#(
parameter FLIT_WIDTH = 32,
parameter CHANNELS = 2,
parameter [63:0] MAPPING = 'x
)
(
input clk, rst,
input [FLIT_WIDTH-1:0] in_flit,
input in_last,
input in_valid,
output reg in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] out_flit,
output [CHANNELS-1:0] out_last,
output reg [CHANNELS-1:0] out_valid,
input [CHANNELS-1:0] out_ready
);
reg [CHANNELS-1:0] active;
reg [CHANNELS-1:0] nxt_active;
wire [2:0] packet_class;
reg [CHANNELS-1:0] select;
assign packet_class = in_flit[NOC_CLASS_MSB:NOC_CLASS_LSB];
always @(*) begin : gen_select
select = MAPPING[8*packet_class +: CHANNELS];
if (select == 0) begin
select = { {CHANNELS-1{1'b0}}, 1'b1};
end
end
assign out_flit = {CHANNELS{in_flit}};
assign out_last = {CHANNELS{in_last}};
always @(*) begin
nxt_active = active;
out_valid = 0;
in_ready = 0;
if (active == 0) begin
in_ready = |(select & out_ready);
out_valid = select & {CHANNELS{in_valid}};
if (in_valid & ~in_last) begin
nxt_active = select;
end
end else begin
in_ready = |(active & out_ready);
out_valid = active & {CHANNELS{in_valid}};
if (in_valid & in_last) begin
nxt_active = 0;
end
end
end
always @(posedge clk)
if (rst) begin
active <= '0;
end else begin
active <= nxt_active;
end
endmodule // noc_demux
|
/* Copyright (c) 2015-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* Arbitrate between different channels, don't break worms.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
* Andreas Lankes <[email protected]>
*/
module noc_mux
import optimsoc_config::*;
#(
parameter FLIT_WIDTH = 32,
parameter CHANNELS = 2
)
(
input clk, rst,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] in_flit,
input [CHANNELS-1:0] in_last,
input [CHANNELS-1:0] in_valid,
output reg [CHANNELS-1:0] in_ready,
output reg [FLIT_WIDTH-1:0] out_flit,
output reg out_last,
output reg out_valid,
input out_ready
);
wire [CHANNELS-1:0] select;
reg [CHANNELS-1:0] active;
reg activeroute, nxt_activeroute;
wire [CHANNELS-1:0] req_masked;
assign req_masked = {CHANNELS{~activeroute & out_ready}} & in_valid;
always @(*) begin
out_flit = {FLIT_WIDTH{1'b0}};
out_last = 1'b0;
for (int c = 0; c < CHANNELS; c = c + 1) begin
if (select[c]) begin
out_flit = in_flit[c];
out_last = in_last[c];
end
end
end
always @(*) begin
nxt_activeroute = activeroute;
in_ready = {CHANNELS{1'b0}};
if (activeroute) begin
if (|(in_valid & active) && out_ready) begin
in_ready = active;
out_valid = 1;
if (out_last)
nxt_activeroute = 0;
end else begin
out_valid = 1'b0;
in_ready = 0;
end
end else begin
out_valid = 0;
if (|in_valid) begin
out_valid = 1'b1;
nxt_activeroute = ~out_last;
in_ready = select & {CHANNELS{out_ready}};
end
end
end // always @ (*)
always @(posedge clk) begin
if (rst) begin
activeroute <= 0;
active <= {{CHANNELS-1{1'b0}},1'b1};
end else begin
activeroute <= nxt_activeroute;
active <= select;
end
end
arb_rr
#(.N(CHANNELS))
u_arb
(.nxt_gnt (select),
.req (req_masked),
.gnt (active),
.en (1));
endmodule // noc_mux
|
/* Copyright (c) 2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* Mux virtual channels
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module noc_vchannel_mux
#(parameter FLIT_WIDTH = 32,
parameter CHANNELS = 2)
(
input clk,
input rst,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] in_flit,
input [CHANNELS-1:0] in_last,
input [CHANNELS-1:0] in_valid,
output [CHANNELS-1:0] in_ready,
output reg [FLIT_WIDTH-1:0] out_flit,
output reg out_last,
output [CHANNELS-1:0] out_valid,
input [CHANNELS-1:0] out_ready
);
reg [CHANNELS-1:0] select;
logic [CHANNELS-1:0] nxt_select;
assign out_valid = in_valid & select;
assign in_ready = out_ready & select;
always @(*) begin
out_flit = 'x;
out_last = 'x;
for (int c = 0; c < CHANNELS; c++) begin
if (select[c]) begin
out_flit = in_flit[c];
out_last = in_last[c];
end
end
end
arb_rr
#(.N (CHANNELS))
u_arbiter
(.req (in_valid & out_ready),
.en (1),
.gnt (select),
.nxt_gnt (nxt_select));
always_ff @(posedge clk) begin
if (rst) begin
select <= {{CHANNELS-1{1'b0}},1'b1};
end else begin
select <= nxt_select;
end
end
endmodule // noc_vchannel_mux
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is a generic slave selector for the Wishbone bus (B3). The
* number of slaves is configurable and up to ten slaves can be
* connected with a configurable memory map.
*
* Instantiation example:
* wb_sselect
* #(.DATA_WIDTH(32), .ADDR_WIDTH(32),
* .SLAVES(2),
* .S0_ENABLE (1), .S0_RANGE_WIDTH(1), .S0_RANGE_MATCH(1'b0),
* .S1_ENABLE (1), .S1_RANGE_WIDTH(4), .S1_RANGE_MATCH(4'he))
* sselect(.clk_i(clk), rst_i(rst),
* .s_adr_o({m_adr_o[3],..,m_adr_o[0]},
* ...
* );
*
* DATA_WIDTH and ADDR_WIDTH are defined in bits. DATA_WIDTH must be
* full bytes (i.e., multiple of 8)!
*
* The ports are flattened. That means, that all slaves share the bus
* signal ports. With four slaves and a data width of 32 bit the
* s_cyc_o port is 4 bit wide and the s_dat_o is 128 (=4*32) bit wide.
* The signals are arranged from right to left, meaning the s_dat_o is
* defined as [DATA_WIDTH*SLAVES-1:0] and each port s is assigned to
* [(s+1)*DATA_WIDTH-1:s*DATA_WIDTH].
*
* The memory map is defined with the S?_RANGE_WIDTH and
* S?_RANGE_MATCH parameters. The WIDTH sets the number of most
* significant bits (i.e., those from the left) that are relevant to
* define the memory range. The MATCH accordingly sets the value of
* those bits of the address that define the memory range.
*
* Example (32 bit addresses):
* Slave 0: 0x00000000-0x7fffffff
* Slave 1: 0x80000000-0xbfffffff
* Slave 2: 0xe0000000-0xe0ffffff
*
* Slave 0 is defined by the uppermost bit, which is 0 for this
* address range. Slave 1 is defined by the uppermost two bit, that
* are 10 for the memory range. Slave 2 is defined by 8 bit which are
* e0 for the memory range.
*
* This results in:
* S0_RANGE_WIDTH(1), S0_RANGE_MATCH(1'b0)
* S1_RANGE_WIDTH(2), S1_RANGE_MATCH(2'b10)
* S2_RANGE_WIDTH(8), S2_RANGE_MATCH(8'he0)
*
*
* Finally, the slaves can be individually masked to ease
* instantiation using the Sx_ENABLE parameter. By defaults all slaves
* are enabled (and selected as long as x < SLAVES).
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module wb_decode
#(
/* User parameters */
// Set the number of slaves
parameter SLAVES = 3,
// Set bus address and data width in bits
// DATA_WIDTH must be a multiple of 8 (full bytes)!
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32,
/* Derived local parameters */
// Width of byte select registers
localparam SEL_WIDTH = DATA_WIDTH >> 3,
// Memory range definitions, see above
// The number of parameters actually limits the number of slaves as
// there is no generic way that is handled by all tools to define
// variable width parameter arrays.
parameter S0_ENABLE = 0,
parameter S0_RANGE_WIDTH = 1,
parameter S0_RANGE_MATCH = 1'b0,
parameter S1_ENABLE = 0,
parameter S1_RANGE_WIDTH = 2,
parameter S1_RANGE_MATCH = 2'b10,
parameter S2_ENABLE = 0,
parameter S2_RANGE_WIDTH = 8,
parameter S2_RANGE_MATCH = 8'he0,
parameter S3_ENABLE = 0,
parameter S3_RANGE_WIDTH = 16,
parameter S3_RANGE_MATCH = 1'b0,
parameter S4_ENABLE = 0,
parameter S4_RANGE_WIDTH = 32,
parameter S4_RANGE_MATCH = 1'b0,
parameter S5_ENABLE = 0,
parameter S5_RANGE_WIDTH = 64,
parameter S5_RANGE_MATCH = 1'b0,
parameter S6_ENABLE = 0,
parameter S6_RANGE_WIDTH = 128,
parameter S6_RANGE_MATCH = 1'b0,
parameter S7_ENABLE = 0,
parameter S7_RANGE_WIDTH = 256,
parameter S7_RANGE_MATCH = 1'b0,
parameter S8_ENABLE = 0,
parameter S8_RANGE_WIDTH = 512,
parameter S8_RANGE_MATCH = 1'b0,
parameter S9_ENABLE = 0,
parameter S9_RANGE_WIDTH = 1024,
parameter S9_RANGE_MATCH = 1'b0
)
(
/* Ports */
input clk_i,
input rst_i,
input [ADDR_WIDTH-1:0] m_adr_i,
input [DATA_WIDTH-1:0] m_dat_i,
input m_cyc_i,
input m_stb_i,
input [SEL_WIDTH-1:0] m_sel_i,
input m_we_i,
input [2:0] m_cti_i,
input [1:0] m_bte_i,
output reg [DATA_WIDTH-1:0] m_dat_o,
output m_ack_o,
output m_err_o,
output m_rty_o,
output reg [ADDR_WIDTH*SLAVES-1:0] s_adr_o,
output reg [DATA_WIDTH*SLAVES-1:0] s_dat_o,
output reg [SLAVES-1:0] s_cyc_o,
output reg [SLAVES-1:0] s_stb_o,
output reg [SEL_WIDTH*SLAVES-1:0] s_sel_o,
output reg [SLAVES-1:0] s_we_o,
output reg [SLAVES*3-1:0] s_cti_o,
output reg [SLAVES*2-1:0] s_bte_o,
input [DATA_WIDTH*SLAVES-1:0] s_dat_i,
input [SLAVES-1:0] s_ack_i,
input [SLAVES-1:0] s_err_i,
input [SLAVES-1:0] s_rty_i
);
wire [SLAVES-1:0] s_select;
// Generate the slave select signals based on the master bus
// address and the memory range parameters
generate
if (SLAVES > 0)
assign s_select[0] = S0_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S0_RANGE_WIDTH] == S0_RANGE_MATCH[S0_RANGE_WIDTH-1:0]);
if (SLAVES > 1)
assign s_select[1] = S1_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S1_RANGE_WIDTH] == S1_RANGE_MATCH[S1_RANGE_WIDTH-1:0]);
if (SLAVES > 2)
assign s_select[2] = S2_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S2_RANGE_WIDTH] == S2_RANGE_MATCH[S2_RANGE_WIDTH-1:0]);
if (SLAVES > 3)
assign s_select[3] = S3_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S3_RANGE_WIDTH] == S3_RANGE_MATCH[S3_RANGE_WIDTH-1:0]);
if (SLAVES > 4)
assign s_select[4] = S4_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S4_RANGE_WIDTH] == S4_RANGE_MATCH[S4_RANGE_WIDTH-1:0]);
if (SLAVES > 5)
assign s_select[5] = S5_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S5_RANGE_WIDTH] == S5_RANGE_MATCH[S5_RANGE_WIDTH-1:0]);
if (SLAVES > 6)
assign s_select[6] = S6_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S6_RANGE_WIDTH] == S6_RANGE_MATCH[S6_RANGE_WIDTH-1:0]);
if (SLAVES > 7)
assign s_select[7] = S7_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S7_RANGE_WIDTH] == S7_RANGE_MATCH[S7_RANGE_WIDTH-1:0]);
if (SLAVES > 8)
assign s_select[8] = S8_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S8_RANGE_WIDTH] == S8_RANGE_MATCH[S8_RANGE_WIDTH-1:0]);
if (SLAVES > 9)
assign s_select[9] = S9_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S9_RANGE_WIDTH] == S9_RANGE_MATCH[S9_RANGE_WIDTH-1:0]);
endgenerate
// If two s_select are high or none, we might have an bus error
wire bus_error;
assign bus_error = ~^s_select;
reg m_ack, m_err, m_rty;
// Mux the slave bus based on the slave select signal (one hot!)
always @(*) begin : bus_s_mux
integer i;
m_dat_o = {DATA_WIDTH{1'b0}};
m_ack = 1'bz;
m_err = 1'bz;
m_rty = 1'bz;
for (i = 0; i < SLAVES; i = i + 1) begin
s_adr_o[i*ADDR_WIDTH +: ADDR_WIDTH] = m_adr_i;
s_dat_o[i*DATA_WIDTH +: DATA_WIDTH] = m_dat_i;
s_sel_o[i*SEL_WIDTH +: SEL_WIDTH] = m_sel_i;
s_we_o[i] = m_we_i;
s_cti_o[i*3 +: 3] = m_cti_i;
s_bte_o[i*2 +: 2] = m_bte_i;
s_cyc_o[i] = m_cyc_i & s_select[i];
s_stb_o[i] = m_stb_i & s_select[i];
if (s_select[i]) begin
m_dat_o = s_dat_i[i*DATA_WIDTH +: DATA_WIDTH];
m_ack = s_ack_i[i];
m_err = s_err_i[i];
m_rty = s_rty_i[i];
end
end
end
assign m_ack_o = m_ack & !bus_error;
assign m_err_o = m_err | bus_error;
assign m_rty_o = m_rty & !bus_error;
endmodule // wb_sselect
|
/*
* PicoRV32 -- A Small RISC-V (RV32I) Processor Core
*
* Copyright (C) 2015 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
`timescale 1 ns / 1 ps
// `default_nettype none
// `define DEBUGNETS
// `define DEBUGREGS
// `define DEBUGASM
// `define DEBUG
`ifdef DEBUG
`define debug(debug_command) debug_command
`else
`define debug(debug_command)
`endif
`ifdef FORMAL
`define FORMAL_KEEP (* keep *)
`define assert(assert_expr) assert(assert_expr)
`else
`ifdef DEBUGNETS
`define FORMAL_KEEP (* keep *)
`else
`define FORMAL_KEEP
`endif
`define assert(assert_expr) empty_statement
`endif
// uncomment this for register file in extra module
// `define PICORV32_REGS picorv32_regs
// this macro can be used to check if the verilog files in your
// design are read in the correct order.
`define PICORV32_V
/***************************************************************
* picorv32
***************************************************************/
module picorv32 #(
parameter [ 0:0] ENABLE_COUNTERS = 1,
parameter [ 0:0] ENABLE_COUNTERS64 = 1,
parameter [ 0:0] ENABLE_REGS_16_31 = 1,
parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
parameter [ 0:0] LATCHED_MEM_RDATA = 0,
parameter [ 0:0] TWO_STAGE_SHIFT = 1,
parameter [ 0:0] BARREL_SHIFTER = 0,
parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
parameter [ 0:0] TWO_CYCLE_ALU = 0,
parameter [ 0:0] COMPRESSED_ISA = 0,
parameter [ 0:0] CATCH_MISALIGN = 1,
parameter [ 0:0] CATCH_ILLINSN = 1,
parameter [ 0:0] ENABLE_PCPI = 0,
parameter [ 0:0] ENABLE_MUL = 0,
parameter [ 0:0] ENABLE_FAST_MUL = 0,
parameter [ 0:0] ENABLE_DIV = 0,
parameter [ 0:0] ENABLE_IRQ = 0,
parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
parameter [ 0:0] ENABLE_TRACE = 0,
parameter [ 0:0] REGS_INIT_ZERO = 0,
parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
parameter [31:0] STACKADDR = 32'h ffff_ffff
) (
input clk, resetn,
output reg trap,
output reg mem_valid,
output reg mem_instr,
input mem_ready,
output reg [31:0] mem_addr,
output reg [31:0] mem_wdata,
output reg [ 3:0] mem_wstrb,
input [31:0] mem_rdata,
// Look-Ahead Interface
output mem_la_read,
output mem_la_write,
output [31:0] mem_la_addr,
output reg [31:0] mem_la_wdata,
output reg [ 3:0] mem_la_wstrb,
// Pico Co-Processor Interface (PCPI)
output reg pcpi_valid,
output reg [31:0] pcpi_insn,
output [31:0] pcpi_rs1,
output [31:0] pcpi_rs2,
input pcpi_wr,
input [31:0] pcpi_rd,
input pcpi_wait,
input pcpi_ready,
// IRQ Interface
input [31:0] irq,
output reg [31:0] eoi,
`ifdef RISCV_FORMAL
output reg rvfi_valid,
output reg [63:0] rvfi_order,
output reg [31:0] rvfi_insn,
output reg rvfi_trap,
output reg rvfi_halt,
output reg rvfi_intr,
output reg [ 1:0] rvfi_mode,
output reg [ 4:0] rvfi_rs1_addr,
output reg [ 4:0] rvfi_rs2_addr,
output reg [31:0] rvfi_rs1_rdata,
output reg [31:0] rvfi_rs2_rdata,
output reg [ 4:0] rvfi_rd_addr,
output reg [31:0] rvfi_rd_wdata,
output reg [31:0] rvfi_pc_rdata,
output reg [31:0] rvfi_pc_wdata,
output reg [31:0] rvfi_mem_addr,
output reg [ 3:0] rvfi_mem_rmask,
output reg [ 3:0] rvfi_mem_wmask,
output reg [31:0] rvfi_mem_rdata,
output reg [31:0] rvfi_mem_wdata,
`endif
// Trace Interface
output reg trace_valid,
output reg [35:0] trace_data
);
localparam integer irq_timer = 0;
localparam integer irq_ebreak = 1;
localparam integer irq_buserror = 2;
localparam integer irqregs_offset = ENABLE_REGS_16_31 ? 32 : 16;
localparam integer regfile_size = (ENABLE_REGS_16_31 ? 32 : 16) + 4*ENABLE_IRQ*ENABLE_IRQ_QREGS;
localparam integer regindex_bits = (ENABLE_REGS_16_31 ? 5 : 4) + ENABLE_IRQ*ENABLE_IRQ_QREGS;
localparam WITH_PCPI = ENABLE_PCPI || ENABLE_MUL || ENABLE_FAST_MUL || ENABLE_DIV;
localparam [35:0] TRACE_BRANCH = {4'b 0001, 32'b 0};
localparam [35:0] TRACE_ADDR = {4'b 0010, 32'b 0};
localparam [35:0] TRACE_IRQ = {4'b 1000, 32'b 0};
reg [63:0] count_cycle, count_instr;
reg [31:0] reg_pc, reg_next_pc, reg_op1, reg_op2, reg_out;
reg [4:0] reg_sh;
reg [31:0] next_insn_opcode;
reg [31:0] dbg_insn_opcode;
reg [31:0] dbg_insn_addr;
wire dbg_mem_valid = mem_valid;
wire dbg_mem_instr = mem_instr;
wire dbg_mem_ready = mem_ready;
wire [31:0] dbg_mem_addr = mem_addr;
wire [31:0] dbg_mem_wdata = mem_wdata;
wire [ 3:0] dbg_mem_wstrb = mem_wstrb;
wire [31:0] dbg_mem_rdata = mem_rdata;
assign pcpi_rs1 = reg_op1;
assign pcpi_rs2 = reg_op2;
wire [31:0] next_pc;
reg irq_delay;
reg irq_active;
reg [31:0] irq_mask;
reg [31:0] irq_pending;
reg [31:0] timer;
`ifndef PICORV32_REGS
reg [31:0] cpuregs [0:regfile_size-1];
integer i;
initial begin
if (REGS_INIT_ZERO) begin
for (i = 0; i < regfile_size; i = i+1)
cpuregs[i] = 0;
end
end
`endif
task empty_statement;
// This task is used by the `assert directive in non-formal mode to
// avoid empty statement (which are unsupported by plain Verilog syntax).
begin end
endtask
`ifdef DEBUGREGS
wire [31:0] dbg_reg_x0 = 0;
wire [31:0] dbg_reg_x1 = cpuregs[1];
wire [31:0] dbg_reg_x2 = cpuregs[2];
wire [31:0] dbg_reg_x3 = cpuregs[3];
wire [31:0] dbg_reg_x4 = cpuregs[4];
wire [31:0] dbg_reg_x5 = cpuregs[5];
wire [31:0] dbg_reg_x6 = cpuregs[6];
wire [31:0] dbg_reg_x7 = cpuregs[7];
wire [31:0] dbg_reg_x8 = cpuregs[8];
wire [31:0] dbg_reg_x9 = cpuregs[9];
wire [31:0] dbg_reg_x10 = cpuregs[10];
wire [31:0] dbg_reg_x11 = cpuregs[11];
wire [31:0] dbg_reg_x12 = cpuregs[12];
wire [31:0] dbg_reg_x13 = cpuregs[13];
wire [31:0] dbg_reg_x14 = cpuregs[14];
wire [31:0] dbg_reg_x15 = cpuregs[15];
wire [31:0] dbg_reg_x16 = cpuregs[16];
wire [31:0] dbg_reg_x17 = cpuregs[17];
wire [31:0] dbg_reg_x18 = cpuregs[18];
wire [31:0] dbg_reg_x19 = cpuregs[19];
wire [31:0] dbg_reg_x20 = cpuregs[20];
wire [31:0] dbg_reg_x21 = cpuregs[21];
wire [31:0] dbg_reg_x22 = cpuregs[22];
wire [31:0] dbg_reg_x23 = cpuregs[23];
wire [31:0] dbg_reg_x24 = cpuregs[24];
wire [31:0] dbg_reg_x25 = cpuregs[25];
wire [31:0] dbg_reg_x26 = cpuregs[26];
wire [31:0] dbg_reg_x27 = cpuregs[27];
wire [31:0] dbg_reg_x28 = cpuregs[28];
wire [31:0] dbg_reg_x29 = cpuregs[29];
wire [31:0] dbg_reg_x30 = cpuregs[30];
wire [31:0] dbg_reg_x31 = cpuregs[31];
`endif
// Internal PCPI Cores
wire pcpi_mul_wr;
wire [31:0] pcpi_mul_rd;
wire pcpi_mul_wait;
wire pcpi_mul_ready;
wire pcpi_div_wr;
wire [31:0] pcpi_div_rd;
wire pcpi_div_wait;
wire pcpi_div_ready;
reg pcpi_int_wr;
reg [31:0] pcpi_int_rd;
reg pcpi_int_wait;
reg pcpi_int_ready;
/*generate if (ENABLE_FAST_MUL) begin
picorv32_pcpi_fast_mul pcpi_mul (
.clk (clk ),
.resetn (resetn ),
.pcpi_valid(pcpi_valid ),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_mul_wr ),
.pcpi_rd (pcpi_mul_rd ),
.pcpi_wait (pcpi_mul_wait ),
.pcpi_ready(pcpi_mul_ready )
);
end else if (ENABLE_MUL) begin
picorv32_pcpi_mul pcpi_mul (
.clk (clk ),
.resetn (resetn ),
.pcpi_valid(pcpi_valid ),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_mul_wr ),
.pcpi_rd (pcpi_mul_rd ),
.pcpi_wait (pcpi_mul_wait ),
.pcpi_ready(pcpi_mul_ready )
);
end else begin
assign pcpi_mul_wr = 0;
assign pcpi_mul_rd = 32'bx;
assign pcpi_mul_wait = 0;
assign pcpi_mul_ready = 0;
end endgenerate
generate if (ENABLE_DIV) begin
picorv32_pcpi_div pcpi_div (
.clk (clk ),
.resetn (resetn ),
.pcpi_valid(pcpi_valid ),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_div_wr ),
.pcpi_rd (pcpi_div_rd ),
.pcpi_wait (pcpi_div_wait ),
.pcpi_ready(pcpi_div_ready )
);
end else begin
assign pcpi_div_wr = 0;
assign pcpi_div_rd = 32'bx;
assign pcpi_div_wait = 0;
assign pcpi_div_ready = 0;
end endgenerate
*/
always @* begin
pcpi_int_wr = 0;
pcpi_int_rd = 32'bx;
pcpi_int_wait = |{ENABLE_PCPI && pcpi_wait, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_wait, ENABLE_DIV && pcpi_div_wait};
pcpi_int_ready = |{ENABLE_PCPI && pcpi_ready, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready, ENABLE_DIV && pcpi_div_ready};
(* parallel_case *)
case (1'b1)
ENABLE_PCPI && pcpi_ready: begin
pcpi_int_wr = ENABLE_PCPI ? pcpi_wr : 0;
pcpi_int_rd = ENABLE_PCPI ? pcpi_rd : 0;
end
(ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready: begin
pcpi_int_wr = pcpi_mul_wr;
pcpi_int_rd = pcpi_mul_rd;
end
ENABLE_DIV && pcpi_div_ready: begin
pcpi_int_wr = pcpi_div_wr;
pcpi_int_rd = pcpi_div_rd;
end
endcase
end
// Memory Interface
reg [1:0] mem_state;
reg [1:0] mem_wordsize;
reg [31:0] mem_rdata_word;
reg [31:0] mem_rdata_q;
reg mem_do_prefetch;
reg mem_do_rinst;
reg mem_do_rdata;
reg mem_do_wdata;
wire mem_xfer;
reg mem_la_secondword, mem_la_firstword_reg, last_mem_valid;
wire mem_la_firstword = COMPRESSED_ISA && (mem_do_prefetch || mem_do_rinst) && next_pc[1] && !mem_la_secondword;
wire mem_la_firstword_xfer = COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg);
reg prefetched_high_word;
reg clear_prefetched_high_word;
reg [15:0] mem_16bit_buffer;
wire [31:0] mem_rdata_latched_noshuffle;
wire [31:0] mem_rdata_latched;
wire mem_la_use_prefetched_high_word = COMPRESSED_ISA && mem_la_firstword && prefetched_high_word && !clear_prefetched_high_word;
assign mem_xfer = (mem_valid && mem_ready) || (mem_la_use_prefetched_high_word && mem_do_rinst);
wire mem_busy = |{mem_do_prefetch, mem_do_rinst, mem_do_rdata, mem_do_wdata};
wire mem_done = resetn && ((mem_xfer && |mem_state && (mem_do_rinst || mem_do_rdata || mem_do_wdata)) || (&mem_state && mem_do_rinst)) &&
(!mem_la_firstword || (~&mem_rdata_latched[1:0] && mem_xfer));
assign mem_la_write = resetn && !mem_state && mem_do_wdata;
assign mem_la_read = resetn && ((!mem_la_use_prefetched_high_word && !mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata)) ||
(COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg) && !mem_la_secondword && &mem_rdata_latched[1:0]));
assign mem_la_addr = (mem_do_prefetch || mem_do_rinst) ? {next_pc[31:2] + mem_la_firstword_xfer, 2'b00} : {reg_op1[31:2], 2'b00};
assign mem_rdata_latched_noshuffle = (mem_xfer || LATCHED_MEM_RDATA) ? mem_rdata : mem_rdata_q;
assign mem_rdata_latched = COMPRESSED_ISA && mem_la_use_prefetched_high_word ? {16'bx, mem_16bit_buffer} :
COMPRESSED_ISA && mem_la_secondword ? {mem_rdata_latched_noshuffle[15:0], mem_16bit_buffer} :
COMPRESSED_ISA && mem_la_firstword ? {16'bx, mem_rdata_latched_noshuffle[31:16]} : mem_rdata_latched_noshuffle;
always @(posedge clk) begin
if (!resetn) begin
mem_la_firstword_reg <= 0;
last_mem_valid <= 0;
end else begin
if (!last_mem_valid)
mem_la_firstword_reg <= mem_la_firstword;
last_mem_valid <= mem_valid && !mem_ready;
end
end
always @* begin
(* full_case *)
case (mem_wordsize)
0: begin
mem_la_wdata = reg_op2;
mem_la_wstrb = 4'b1111;
mem_rdata_word = mem_rdata;
end
1: begin
mem_la_wdata = {2{reg_op2[15:0]}};
mem_la_wstrb = reg_op1[1] ? 4'b1100 : 4'b0011;
case (reg_op1[1])
1'b0: mem_rdata_word = {16'b0, mem_rdata[15: 0]};
1'b1: mem_rdata_word = {16'b0, mem_rdata[31:16]};
endcase
end
2: begin
mem_la_wdata = {4{reg_op2[7:0]}};
mem_la_wstrb = 4'b0001 << reg_op1[1:0];
case (reg_op1[1:0])
2'b00: mem_rdata_word = {24'b0, mem_rdata[ 7: 0]};
2'b01: mem_rdata_word = {24'b0, mem_rdata[15: 8]};
2'b10: mem_rdata_word = {24'b0, mem_rdata[23:16]};
2'b11: mem_rdata_word = {24'b0, mem_rdata[31:24]};
endcase
end
endcase
end
always @(posedge clk) begin
if (mem_xfer) begin
mem_rdata_q <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
next_insn_opcode <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
end
if (COMPRESSED_ISA && mem_done && (mem_do_prefetch || mem_do_rinst)) begin
case (mem_rdata_latched[1:0])
2'b00: begin // Quadrant 0
case (mem_rdata_latched[15:13])
3'b000: begin // C.ADDI4SPN
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= {2'b0, mem_rdata_latched[10:7], mem_rdata_latched[12:11], mem_rdata_latched[5], mem_rdata_latched[6], 2'b00};
end
3'b010: begin // C.LW
mem_rdata_q[31:20] <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00};
mem_rdata_q[14:12] <= 3'b 010;
end
3'b 110: begin // C.SW
{mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00};
mem_rdata_q[14:12] <= 3'b 010;
end
endcase
end
2'b01: begin // Quadrant 1
case (mem_rdata_latched[15:13])
3'b 000: begin // C.ADDI
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
end
3'b 010: begin // C.LI
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
end
3'b 011: begin
if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[4:3],
mem_rdata_latched[5], mem_rdata_latched[2], mem_rdata_latched[6], 4'b 0000});
end else begin // C.LUI
mem_rdata_q[31:12] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
end
end
3'b100: begin
if (mem_rdata_latched[11:10] == 2'b00) begin // C.SRLI
mem_rdata_q[31:25] <= 7'b0000000;
mem_rdata_q[14:12] <= 3'b 101;
end
if (mem_rdata_latched[11:10] == 2'b01) begin // C.SRAI
mem_rdata_q[31:25] <= 7'b0100000;
mem_rdata_q[14:12] <= 3'b 101;
end
if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI
mem_rdata_q[14:12] <= 3'b111;
mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
end
if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND
if (mem_rdata_latched[6:5] == 2'b00) mem_rdata_q[14:12] <= 3'b000;
if (mem_rdata_latched[6:5] == 2'b01) mem_rdata_q[14:12] <= 3'b100;
if (mem_rdata_latched[6:5] == 2'b10) mem_rdata_q[14:12] <= 3'b110;
if (mem_rdata_latched[6:5] == 2'b11) mem_rdata_q[14:12] <= 3'b111;
mem_rdata_q[31:25] <= mem_rdata_latched[6:5] == 2'b00 ? 7'b0100000 : 7'b0000000;
end
end
3'b 110: begin // C.BEQZ
mem_rdata_q[14:12] <= 3'b000;
{ mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
$signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
mem_rdata_latched[11:10], mem_rdata_latched[4:3]});
end
3'b 111: begin // C.BNEZ
mem_rdata_q[14:12] <= 3'b001;
{ mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
$signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
mem_rdata_latched[11:10], mem_rdata_latched[4:3]});
end
endcase
end
2'b10: begin // Quadrant 2
case (mem_rdata_latched[15:13])
3'b000: begin // C.SLLI
mem_rdata_q[31:25] <= 7'b0000000;
mem_rdata_q[14:12] <= 3'b 001;
end
3'b010: begin // C.LWSP
mem_rdata_q[31:20] <= {4'b0, mem_rdata_latched[3:2], mem_rdata_latched[12], mem_rdata_latched[6:4], 2'b00};
mem_rdata_q[14:12] <= 3'b 010;
end
3'b100: begin
if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] == 0) begin // C.JR
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= 12'b0;
end
if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:25] <= 7'b0000000;
end
if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= 12'b0;
end
if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:25] <= 7'b0000000;
end
end
3'b110: begin // C.SWSP
{mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {4'b0, mem_rdata_latched[8:7], mem_rdata_latched[12:9], 2'b00};
mem_rdata_q[14:12] <= 3'b 010;
end
endcase
end
endcase
end
end
always @(posedge clk) begin
if (resetn && !trap) begin
if (mem_do_prefetch || mem_do_rinst || mem_do_rdata)
`assert(!mem_do_wdata);
if (mem_do_prefetch || mem_do_rinst)
`assert(!mem_do_rdata);
if (mem_do_rdata)
`assert(!mem_do_prefetch && !mem_do_rinst);
if (mem_do_wdata)
`assert(!(mem_do_prefetch || mem_do_rinst || mem_do_rdata));
if (mem_state == 2 || mem_state == 3)
`assert(mem_valid || mem_do_prefetch);
end
end
always @(posedge clk) begin
if (!resetn || trap) begin
if (!resetn)
mem_state <= 0;
if (!resetn || mem_ready)
mem_valid <= 0;
mem_la_secondword <= 0;
prefetched_high_word <= 0;
end else begin
if (mem_la_read || mem_la_write) begin
mem_addr <= mem_la_addr;
mem_wstrb <= mem_la_wstrb & {4{mem_la_write}};
end
if (mem_la_write) begin
mem_wdata <= mem_la_wdata;
end
case (mem_state)
0: begin
if (mem_do_prefetch || mem_do_rinst || mem_do_rdata) begin
mem_valid <= !mem_la_use_prefetched_high_word;
mem_instr <= mem_do_prefetch || mem_do_rinst;
mem_wstrb <= 0;
mem_state <= 1;
end
if (mem_do_wdata) begin
mem_valid <= 1;
mem_instr <= 0;
mem_state <= 2;
end
end
1: begin
`assert(mem_wstrb == 0);
`assert(mem_do_prefetch || mem_do_rinst || mem_do_rdata);
`assert(mem_valid == !mem_la_use_prefetched_high_word);
`assert(mem_instr == (mem_do_prefetch || mem_do_rinst));
if (mem_xfer) begin
if (COMPRESSED_ISA && mem_la_read) begin
mem_valid <= 1;
mem_la_secondword <= 1;
if (!mem_la_use_prefetched_high_word)
mem_16bit_buffer <= mem_rdata[31:16];
end else begin
mem_valid <= 0;
mem_la_secondword <= 0;
if (COMPRESSED_ISA && !mem_do_rdata) begin
if (~&mem_rdata[1:0] || mem_la_secondword) begin
mem_16bit_buffer <= mem_rdata[31:16];
prefetched_high_word <= 1;
end else begin
prefetched_high_word <= 0;
end
end
mem_state <= mem_do_rinst || mem_do_rdata ? 0 : 3;
end
end
end
2: begin
`assert(mem_wstrb != 0);
`assert(mem_do_wdata);
if (mem_xfer) begin
mem_valid <= 0;
mem_state <= 0;
end
end
3: begin
`assert(mem_wstrb == 0);
`assert(mem_do_prefetch);
if (mem_do_rinst) begin
mem_state <= 0;
end
end
endcase
end
if (clear_prefetched_high_word)
prefetched_high_word <= 0;
end
// Instruction Decoder
reg instr_lui, instr_auipc, instr_jal, instr_jalr;
reg instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu;
reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw;
reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai;
reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and;
reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak;
reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer;
wire instr_trap;
reg [regindex_bits-1:0] decoded_rd, decoded_rs1, decoded_rs2;
reg [31:0] decoded_imm, decoded_imm_j;
reg decoder_trigger;
reg decoder_trigger_q;
reg decoder_pseudo_trigger;
reg decoder_pseudo_trigger_q;
reg compressed_instr;
reg is_lui_auipc_jal;
reg is_lb_lh_lw_lbu_lhu;
reg is_slli_srli_srai;
reg is_jalr_addi_slti_sltiu_xori_ori_andi;
reg is_sb_sh_sw;
reg is_sll_srl_sra;
reg is_lui_auipc_jal_jalr_addi_add_sub;
reg is_slti_blt_slt;
reg is_sltiu_bltu_sltu;
reg is_beq_bne_blt_bge_bltu_bgeu;
reg is_lbu_lhu_lw;
reg is_alu_reg_imm;
reg is_alu_reg_reg;
reg is_compare;
assign instr_trap = (CATCH_ILLINSN || WITH_PCPI) && !{instr_lui, instr_auipc, instr_jal, instr_jalr,
instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu,
instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw,
instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai,
instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and,
instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh,
instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer};
wire is_rdcycle_rdcycleh_rdinstr_rdinstrh;
assign is_rdcycle_rdcycleh_rdinstr_rdinstrh = |{instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh};
reg [63:0] new_ascii_instr;
`FORMAL_KEEP reg [63:0] dbg_ascii_instr;
`FORMAL_KEEP reg [31:0] dbg_insn_imm;
`FORMAL_KEEP reg [4:0] dbg_insn_rs1;
`FORMAL_KEEP reg [4:0] dbg_insn_rs2;
`FORMAL_KEEP reg [4:0] dbg_insn_rd;
`FORMAL_KEEP reg [31:0] dbg_rs1val;
`FORMAL_KEEP reg [31:0] dbg_rs2val;
`FORMAL_KEEP reg dbg_rs1val_valid;
`FORMAL_KEEP reg dbg_rs2val_valid;
always @* begin
new_ascii_instr = "";
if (instr_lui) new_ascii_instr = "lui";
if (instr_auipc) new_ascii_instr = "auipc";
if (instr_jal) new_ascii_instr = "jal";
if (instr_jalr) new_ascii_instr = "jalr";
if (instr_beq) new_ascii_instr = "beq";
if (instr_bne) new_ascii_instr = "bne";
if (instr_blt) new_ascii_instr = "blt";
if (instr_bge) new_ascii_instr = "bge";
if (instr_bltu) new_ascii_instr = "bltu";
if (instr_bgeu) new_ascii_instr = "bgeu";
if (instr_lb) new_ascii_instr = "lb";
if (instr_lh) new_ascii_instr = "lh";
if (instr_lw) new_ascii_instr = "lw";
if (instr_lbu) new_ascii_instr = "lbu";
if (instr_lhu) new_ascii_instr = "lhu";
if (instr_sb) new_ascii_instr = "sb";
if (instr_sh) new_ascii_instr = "sh";
if (instr_sw) new_ascii_instr = "sw";
if (instr_addi) new_ascii_instr = "addi";
if (instr_slti) new_ascii_instr = "slti";
if (instr_sltiu) new_ascii_instr = "sltiu";
if (instr_xori) new_ascii_instr = "xori";
if (instr_ori) new_ascii_instr = "ori";
if (instr_andi) new_ascii_instr = "andi";
if (instr_slli) new_ascii_instr = "slli";
if (instr_srli) new_ascii_instr = "srli";
if (instr_srai) new_ascii_instr = "srai";
if (instr_add) new_ascii_instr = "add";
if (instr_sub) new_ascii_instr = "sub";
if (instr_sll) new_ascii_instr = "sll";
if (instr_slt) new_ascii_instr = "slt";
if (instr_sltu) new_ascii_instr = "sltu";
if (instr_xor) new_ascii_instr = "xor";
if (instr_srl) new_ascii_instr = "srl";
if (instr_sra) new_ascii_instr = "sra";
if (instr_or) new_ascii_instr = "or";
if (instr_and) new_ascii_instr = "and";
if (instr_rdcycle) new_ascii_instr = "rdcycle";
if (instr_rdcycleh) new_ascii_instr = "rdcycleh";
if (instr_rdinstr) new_ascii_instr = "rdinstr";
if (instr_rdinstrh) new_ascii_instr = "rdinstrh";
if (instr_getq) new_ascii_instr = "getq";
if (instr_setq) new_ascii_instr = "setq";
if (instr_retirq) new_ascii_instr = "retirq";
if (instr_maskirq) new_ascii_instr = "maskirq";
if (instr_waitirq) new_ascii_instr = "waitirq";
if (instr_timer) new_ascii_instr = "timer";
end
reg [63:0] q_ascii_instr;
reg [31:0] q_insn_imm;
reg [31:0] q_insn_opcode;
reg [4:0] q_insn_rs1;
reg [4:0] q_insn_rs2;
reg [4:0] q_insn_rd;
reg dbg_next;
wire launch_next_insn;
reg dbg_valid_insn;
reg [63:0] cached_ascii_instr;
reg [31:0] cached_insn_imm;
reg [31:0] cached_insn_opcode;
reg [4:0] cached_insn_rs1;
reg [4:0] cached_insn_rs2;
reg [4:0] cached_insn_rd;
always @(posedge clk) begin
q_ascii_instr <= dbg_ascii_instr;
q_insn_imm <= dbg_insn_imm;
q_insn_opcode <= dbg_insn_opcode;
q_insn_rs1 <= dbg_insn_rs1;
q_insn_rs2 <= dbg_insn_rs2;
q_insn_rd <= dbg_insn_rd;
dbg_next <= launch_next_insn;
if (!resetn || trap)
dbg_valid_insn <= 0;
else if (launch_next_insn)
dbg_valid_insn <= 1;
if (decoder_trigger_q) begin
cached_ascii_instr <= new_ascii_instr;
cached_insn_imm <= decoded_imm;
if (&next_insn_opcode[1:0])
cached_insn_opcode <= next_insn_opcode;
else
cached_insn_opcode <= {16'b0, next_insn_opcode[15:0]};
cached_insn_rs1 <= decoded_rs1;
cached_insn_rs2 <= decoded_rs2;
cached_insn_rd <= decoded_rd;
end
if (launch_next_insn) begin
dbg_insn_addr <= next_pc;
end
end
always @* begin
dbg_ascii_instr = q_ascii_instr;
dbg_insn_imm = q_insn_imm;
dbg_insn_opcode = q_insn_opcode;
dbg_insn_rs1 = q_insn_rs1;
dbg_insn_rs2 = q_insn_rs2;
dbg_insn_rd = q_insn_rd;
if (dbg_next) begin
if (decoder_pseudo_trigger_q) begin
dbg_ascii_instr = cached_ascii_instr;
dbg_insn_imm = cached_insn_imm;
dbg_insn_opcode = cached_insn_opcode;
dbg_insn_rs1 = cached_insn_rs1;
dbg_insn_rs2 = cached_insn_rs2;
dbg_insn_rd = cached_insn_rd;
end else begin
dbg_ascii_instr = new_ascii_instr;
if (&next_insn_opcode[1:0])
dbg_insn_opcode = next_insn_opcode;
else
dbg_insn_opcode = {16'b0, next_insn_opcode[15:0]};
dbg_insn_imm = decoded_imm;
dbg_insn_rs1 = decoded_rs1;
dbg_insn_rs2 = decoded_rs2;
dbg_insn_rd = decoded_rd;
end
end
end
`ifdef DEBUGASM
always @(posedge clk) begin
if (dbg_next) begin
$display("debugasm %x %x %s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "*");
end
end
`endif
`ifdef DEBUG
always @(posedge clk) begin
if (dbg_next) begin
if (&dbg_insn_opcode[1:0])
$display("DECODE: 0x%08x 0x%08x %-0s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
else
$display("DECODE: 0x%08x 0x%04x %-0s", dbg_insn_addr, dbg_insn_opcode[15:0], dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
end
end
`endif
always @(posedge clk) begin
is_lui_auipc_jal <= |{instr_lui, instr_auipc, instr_jal};
is_lui_auipc_jal_jalr_addi_add_sub <= |{instr_lui, instr_auipc, instr_jal, instr_jalr, instr_addi, instr_add, instr_sub};
is_slti_blt_slt <= |{instr_slti, instr_blt, instr_slt};
is_sltiu_bltu_sltu <= |{instr_sltiu, instr_bltu, instr_sltu};
is_lbu_lhu_lw <= |{instr_lbu, instr_lhu, instr_lw};
is_compare <= |{is_beq_bne_blt_bge_bltu_bgeu, instr_slti, instr_slt, instr_sltiu, instr_sltu};
if (mem_do_rinst && mem_done) begin
instr_lui <= mem_rdata_latched[6:0] == 7'b0110111;
instr_auipc <= mem_rdata_latched[6:0] == 7'b0010111;
instr_jal <= mem_rdata_latched[6:0] == 7'b1101111;
instr_jalr <= mem_rdata_latched[6:0] == 7'b1100111 && mem_rdata_latched[14:12] == 3'b000;
instr_retirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ;
instr_waitirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000100 && ENABLE_IRQ;
is_beq_bne_blt_bge_bltu_bgeu <= mem_rdata_latched[6:0] == 7'b1100011;
is_lb_lh_lw_lbu_lhu <= mem_rdata_latched[6:0] == 7'b0000011;
is_sb_sh_sw <= mem_rdata_latched[6:0] == 7'b0100011;
is_alu_reg_imm <= mem_rdata_latched[6:0] == 7'b0010011;
is_alu_reg_reg <= mem_rdata_latched[6:0] == 7'b0110011;
{ decoded_imm_j[31:20], decoded_imm_j[10:1], decoded_imm_j[11], decoded_imm_j[19:12], decoded_imm_j[0] } <= $signed({mem_rdata_latched[31:12], 1'b0});
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[19:15];
decoded_rs2 <= mem_rdata_latched[24:20];
if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS)
decoded_rs1[regindex_bits-1] <= 1; // instr_getq
if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ)
decoded_rs1 <= ENABLE_IRQ_QREGS ? irqregs_offset : 3; // instr_retirq
compressed_instr <= 0;
if (COMPRESSED_ISA && mem_rdata_latched[1:0] != 2'b11) begin
compressed_instr <= 1;
decoded_rd <= 0;
decoded_rs1 <= 0;
decoded_rs2 <= 0;
{ decoded_imm_j[31:11], decoded_imm_j[4], decoded_imm_j[9:8], decoded_imm_j[10], decoded_imm_j[6],
decoded_imm_j[7], decoded_imm_j[3:1], decoded_imm_j[5], decoded_imm_j[0] } <= $signed({mem_rdata_latched[12:2], 1'b0});
case (mem_rdata_latched[1:0])
2'b00: begin // Quadrant 0
case (mem_rdata_latched[15:13])
3'b000: begin // C.ADDI4SPN
is_alu_reg_imm <= |mem_rdata_latched[12:5];
decoded_rs1 <= 2;
decoded_rd <= 8 + mem_rdata_latched[4:2];
end
3'b010: begin // C.LW
is_lb_lh_lw_lbu_lhu <= 1;
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rd <= 8 + mem_rdata_latched[4:2];
end
3'b110: begin // C.SW
is_sb_sh_sw <= 1;
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= 8 + mem_rdata_latched[4:2];
end
endcase
end
2'b01: begin // Quadrant 1
case (mem_rdata_latched[15:13])
3'b000: begin // C.NOP / C.ADDI
is_alu_reg_imm <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[11:7];
end
3'b001: begin // C.JAL
instr_jal <= 1;
decoded_rd <= 1;
end
3'b 010: begin // C.LI
is_alu_reg_imm <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= 0;
end
3'b 011: begin
if (mem_rdata_latched[12] || mem_rdata_latched[6:2]) begin
if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP
is_alu_reg_imm <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[11:7];
end else begin // C.LUI
instr_lui <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= 0;
end
end
end
3'b100: begin
if (!mem_rdata_latched[11] && !mem_rdata_latched[12]) begin // C.SRLI, C.SRAI
is_alu_reg_imm <= 1;
decoded_rd <= 8 + mem_rdata_latched[9:7];
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
end
if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI
is_alu_reg_imm <= 1;
decoded_rd <= 8 + mem_rdata_latched[9:7];
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
end
if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND
is_alu_reg_reg <= 1;
decoded_rd <= 8 + mem_rdata_latched[9:7];
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= 8 + mem_rdata_latched[4:2];
end
end
3'b101: begin // C.J
instr_jal <= 1;
end
3'b110: begin // C.BEQZ
is_beq_bne_blt_bge_bltu_bgeu <= 1;
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= 0;
end
3'b111: begin // C.BNEZ
is_beq_bne_blt_bge_bltu_bgeu <= 1;
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= 0;
end
endcase
end
2'b10: begin // Quadrant 2
case (mem_rdata_latched[15:13])
3'b000: begin // C.SLLI
if (!mem_rdata_latched[12]) begin
is_alu_reg_imm <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[11:7];
decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
end
end
3'b010: begin // C.LWSP
if (mem_rdata_latched[11:7]) begin
is_lb_lh_lw_lbu_lhu <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= 2;
end
end
3'b100: begin
if (mem_rdata_latched[12] == 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JR
instr_jalr <= 1;
decoded_rd <= 0;
decoded_rs1 <= mem_rdata_latched[11:7];
end
if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV
is_alu_reg_reg <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= 0;
decoded_rs2 <= mem_rdata_latched[6:2];
end
if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR
instr_jalr <= 1;
decoded_rd <= 1;
decoded_rs1 <= mem_rdata_latched[11:7];
end
if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD
is_alu_reg_reg <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[11:7];
decoded_rs2 <= mem_rdata_latched[6:2];
end
end
3'b110: begin // C.SWSP
is_sb_sh_sw <= 1;
decoded_rs1 <= 2;
decoded_rs2 <= mem_rdata_latched[6:2];
end
endcase
end
endcase
end
end
if (decoder_trigger && !decoder_pseudo_trigger) begin
pcpi_insn <= WITH_PCPI ? mem_rdata_q : 'bx;
instr_beq <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b000;
instr_bne <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b001;
instr_blt <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b100;
instr_bge <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b101;
instr_bltu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b110;
instr_bgeu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b111;
instr_lb <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b000;
instr_lh <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b001;
instr_lw <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b010;
instr_lbu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b100;
instr_lhu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b101;
instr_sb <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b000;
instr_sh <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b001;
instr_sw <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b010;
instr_addi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b000;
instr_slti <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b010;
instr_sltiu <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b011;
instr_xori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b100;
instr_ori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b110;
instr_andi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b111;
instr_slli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000;
instr_srli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000;
instr_srai <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000;
instr_add <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0000000;
instr_sub <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0100000;
instr_sll <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000;
instr_slt <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b010 && mem_rdata_q[31:25] == 7'b0000000;
instr_sltu <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b011 && mem_rdata_q[31:25] == 7'b0000000;
instr_xor <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b100 && mem_rdata_q[31:25] == 7'b0000000;
instr_srl <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000;
instr_sra <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000;
instr_or <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b110 && mem_rdata_q[31:25] == 7'b0000000;
instr_and <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b111 && mem_rdata_q[31:25] == 7'b0000000;
instr_rdcycle <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000000000010) ||
(mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000100000010)) && ENABLE_COUNTERS;
instr_rdcycleh <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000000000010) ||
(mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000100000010)) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
instr_rdinstr <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000001000000010) && ENABLE_COUNTERS;
instr_rdinstrh <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000001000000010) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
instr_ecall_ebreak <= ((mem_rdata_q[6:0] == 7'b1110011 && !mem_rdata_q[31:21] && !mem_rdata_q[19:7]) ||
(COMPRESSED_ISA && mem_rdata_q[15:0] == 16'h9002));
instr_getq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
instr_setq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000001 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
instr_maskirq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000011 && ENABLE_IRQ;
instr_timer <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000101 && ENABLE_IRQ && ENABLE_IRQ_TIMER;
is_slli_srli_srai <= is_alu_reg_imm && |{
mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000,
mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000,
mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000
};
is_jalr_addi_slti_sltiu_xori_ori_andi <= instr_jalr || is_alu_reg_imm && |{
mem_rdata_q[14:12] == 3'b000,
mem_rdata_q[14:12] == 3'b010,
mem_rdata_q[14:12] == 3'b011,
mem_rdata_q[14:12] == 3'b100,
mem_rdata_q[14:12] == 3'b110,
mem_rdata_q[14:12] == 3'b111
};
is_sll_srl_sra <= is_alu_reg_reg && |{
mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000,
mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000,
mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000
};
is_lui_auipc_jal_jalr_addi_add_sub <= 0;
is_compare <= 0;
(* parallel_case *)
case (1'b1)
instr_jal:
decoded_imm <= decoded_imm_j;
|{instr_lui, instr_auipc}:
decoded_imm <= mem_rdata_q[31:12] << 12;
|{instr_jalr, is_lb_lh_lw_lbu_lhu, is_alu_reg_imm}:
decoded_imm <= $signed(mem_rdata_q[31:20]);
is_beq_bne_blt_bge_bltu_bgeu:
decoded_imm <= $signed({mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8], 1'b0});
is_sb_sh_sw:
decoded_imm <= $signed({mem_rdata_q[31:25], mem_rdata_q[11:7]});
default:
decoded_imm <= 1'bx;
endcase
end
if (!resetn) begin
is_beq_bne_blt_bge_bltu_bgeu <= 0;
is_compare <= 0;
instr_beq <= 0;
instr_bne <= 0;
instr_blt <= 0;
instr_bge <= 0;
instr_bltu <= 0;
instr_bgeu <= 0;
instr_addi <= 0;
instr_slti <= 0;
instr_sltiu <= 0;
instr_xori <= 0;
instr_ori <= 0;
instr_andi <= 0;
instr_add <= 0;
instr_sub <= 0;
instr_sll <= 0;
instr_slt <= 0;
instr_sltu <= 0;
instr_xor <= 0;
instr_srl <= 0;
instr_sra <= 0;
instr_or <= 0;
instr_and <= 0;
end
end
// Main State Machine
localparam cpu_state_trap = 8'b10000000;
localparam cpu_state_fetch = 8'b01000000;
localparam cpu_state_ld_rs1 = 8'b00100000;
localparam cpu_state_ld_rs2 = 8'b00010000;
localparam cpu_state_exec = 8'b00001000;
localparam cpu_state_shift = 8'b00000100;
localparam cpu_state_stmem = 8'b00000010;
localparam cpu_state_ldmem = 8'b00000001;
reg [7:0] cpu_state;
reg [1:0] irq_state;
`FORMAL_KEEP reg [127:0] dbg_ascii_state;
always @* begin
dbg_ascii_state = "";
if (cpu_state == cpu_state_trap) dbg_ascii_state = "trap";
if (cpu_state == cpu_state_fetch) dbg_ascii_state = "fetch";
if (cpu_state == cpu_state_ld_rs1) dbg_ascii_state = "ld_rs1";
if (cpu_state == cpu_state_ld_rs2) dbg_ascii_state = "ld_rs2";
if (cpu_state == cpu_state_exec) dbg_ascii_state = "exec";
if (cpu_state == cpu_state_shift) dbg_ascii_state = "shift";
if (cpu_state == cpu_state_stmem) dbg_ascii_state = "stmem";
if (cpu_state == cpu_state_ldmem) dbg_ascii_state = "ldmem";
end
reg set_mem_do_rinst;
reg set_mem_do_rdata;
reg set_mem_do_wdata;
reg latched_store;
reg latched_stalu;
reg latched_branch;
reg latched_compr;
reg latched_trace;
reg latched_is_lu;
reg latched_is_lh;
reg latched_is_lb;
reg [regindex_bits-1:0] latched_rd;
reg [31:0] current_pc;
assign next_pc = latched_store && latched_branch ? reg_out & ~1 : reg_next_pc;
reg [3:0] pcpi_timeout_counter;
reg pcpi_timeout;
reg [31:0] next_irq_pending;
reg do_waitirq;
reg [31:0] alu_out, alu_out_q;
reg alu_out_0, alu_out_0_q;
reg alu_wait, alu_wait_2;
reg [31:0] alu_add_sub;
reg [31:0] alu_shl, alu_shr;
reg alu_eq, alu_ltu, alu_lts;
generate if (TWO_CYCLE_ALU) begin
always @(posedge clk) begin
alu_add_sub <= instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
alu_eq <= reg_op1 == reg_op2;
alu_lts <= $signed(reg_op1) < $signed(reg_op2);
alu_ltu <= reg_op1 < reg_op2;
alu_shl <= reg_op1 << reg_op2[4:0];
alu_shr <= $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
end
end else begin
always @* begin
alu_add_sub = instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
alu_eq = reg_op1 == reg_op2;
alu_lts = $signed(reg_op1) < $signed(reg_op2);
alu_ltu = reg_op1 < reg_op2;
alu_shl = reg_op1 << reg_op2[4:0];
alu_shr = $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
end
end endgenerate
always @* begin
alu_out_0 = 'bx;
(* parallel_case, full_case *)
case (1'b1)
instr_beq:
alu_out_0 = alu_eq;
instr_bne:
alu_out_0 = !alu_eq;
instr_bge:
alu_out_0 = !alu_lts;
instr_bgeu:
alu_out_0 = !alu_ltu;
is_slti_blt_slt && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
alu_out_0 = alu_lts;
is_sltiu_bltu_sltu && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
alu_out_0 = alu_ltu;
endcase
alu_out = 'bx;
(* parallel_case, full_case *)
case (1'b1)
is_lui_auipc_jal_jalr_addi_add_sub:
alu_out = alu_add_sub;
is_compare:
alu_out = alu_out_0;
instr_xori || instr_xor:
alu_out = reg_op1 ^ reg_op2;
instr_ori || instr_or:
alu_out = reg_op1 | reg_op2;
instr_andi || instr_and:
alu_out = reg_op1 & reg_op2;
BARREL_SHIFTER && (instr_sll || instr_slli):
alu_out = alu_shl;
BARREL_SHIFTER && (instr_srl || instr_srli || instr_sra || instr_srai):
alu_out = alu_shr;
endcase
`ifdef RISCV_FORMAL_BLACKBOX_ALU
alu_out_0 = $anyseq;
alu_out = $anyseq;
`endif
end
reg clear_prefetched_high_word_q;
always @(posedge clk) clear_prefetched_high_word_q <= clear_prefetched_high_word;
always @* begin
clear_prefetched_high_word = clear_prefetched_high_word_q;
if (!prefetched_high_word)
clear_prefetched_high_word = 0;
if (latched_branch || irq_state || !resetn)
clear_prefetched_high_word = COMPRESSED_ISA;
end
reg cpuregs_write;
reg [31:0] cpuregs_wrdata;
reg [31:0] cpuregs_rs1;
reg [31:0] cpuregs_rs2;
reg [regindex_bits-1:0] decoded_rs;
always @* begin
cpuregs_write = 0;
cpuregs_wrdata = 'bx;
if (cpu_state == cpu_state_fetch) begin
(* parallel_case *)
case (1'b1)
latched_branch: begin
cpuregs_wrdata = reg_pc + (latched_compr ? 2 : 4);
cpuregs_write = 1;
end
latched_store && !latched_branch: begin
cpuregs_wrdata = latched_stalu ? alu_out_q : reg_out;
cpuregs_write = 1;
end
ENABLE_IRQ && irq_state[0]: begin
cpuregs_wrdata = reg_next_pc | latched_compr;
cpuregs_write = 1;
end
ENABLE_IRQ && irq_state[1]: begin
cpuregs_wrdata = irq_pending & ~irq_mask;
cpuregs_write = 1;
end
endcase
end
end
`ifndef PICORV32_REGS
always @(posedge clk) begin
if (resetn && cpuregs_write && latched_rd)
cpuregs[latched_rd] <= cpuregs_wrdata;
end
always @* begin
decoded_rs = 'bx;
if (ENABLE_REGS_DUALPORT) begin
`ifndef RISCV_FORMAL_BLACKBOX_REGS
cpuregs_rs1 = decoded_rs1 ? cpuregs[decoded_rs1] : 0;
cpuregs_rs2 = decoded_rs2 ? cpuregs[decoded_rs2] : 0;
`else
cpuregs_rs1 = decoded_rs1 ? $anyseq : 0;
cpuregs_rs2 = decoded_rs2 ? $anyseq : 0;
`endif
end else begin
decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
`ifndef RISCV_FORMAL_BLACKBOX_REGS
cpuregs_rs1 = decoded_rs ? cpuregs[decoded_rs] : 0;
`else
cpuregs_rs1 = decoded_rs ? $anyseq : 0;
`endif
cpuregs_rs2 = cpuregs_rs1;
end
end
`else
wire[31:0] cpuregs_rdata1;
wire[31:0] cpuregs_rdata2;
wire [5:0] cpuregs_waddr = latched_rd;
wire [5:0] cpuregs_raddr1 = ENABLE_REGS_DUALPORT ? decoded_rs1 : decoded_rs;
wire [5:0] cpuregs_raddr2 = ENABLE_REGS_DUALPORT ? decoded_rs2 : 0;
`PICORV32_REGS cpuregs (
.clk(clk),
.wen(resetn && cpuregs_write && latched_rd),
.waddr(cpuregs_waddr),
.raddr1(cpuregs_raddr1),
.raddr2(cpuregs_raddr2),
.wdata(cpuregs_wrdata),
.rdata1(cpuregs_rdata1),
.rdata2(cpuregs_rdata2)
);
always @* begin
decoded_rs = 'bx;
if (ENABLE_REGS_DUALPORT) begin
cpuregs_rs1 = decoded_rs1 ? cpuregs_rdata1 : 0;
cpuregs_rs2 = decoded_rs2 ? cpuregs_rdata2 : 0;
end else begin
decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
cpuregs_rs1 = decoded_rs ? cpuregs_rdata1 : 0;
cpuregs_rs2 = cpuregs_rs1;
end
end
`endif
assign launch_next_insn = cpu_state == cpu_state_fetch && decoder_trigger && (!ENABLE_IRQ || irq_delay || irq_active || !(irq_pending & ~irq_mask));
always @(posedge clk) begin
trap <= 0;
reg_sh <= 'bx;
reg_out <= 'bx;
set_mem_do_rinst = 0;
set_mem_do_rdata = 0;
set_mem_do_wdata = 0;
alu_out_0_q <= alu_out_0;
alu_out_q <= alu_out;
alu_wait <= 0;
alu_wait_2 <= 0;
if (launch_next_insn) begin
dbg_rs1val <= 'bx;
dbg_rs2val <= 'bx;
dbg_rs1val_valid <= 0;
dbg_rs2val_valid <= 0;
end
if (WITH_PCPI && CATCH_ILLINSN) begin
if (resetn && pcpi_valid && !pcpi_int_wait) begin
if (pcpi_timeout_counter)
pcpi_timeout_counter <= pcpi_timeout_counter - 1;
end else
pcpi_timeout_counter <= ~0;
pcpi_timeout <= !pcpi_timeout_counter;
end
if (ENABLE_COUNTERS) begin
count_cycle <= resetn ? count_cycle + 1 : 0;
if (!ENABLE_COUNTERS64) count_cycle[63:32] <= 0;
end else begin
count_cycle <= 'bx;
count_instr <= 'bx;
end
next_irq_pending = ENABLE_IRQ ? irq_pending & LATCHED_IRQ : 'bx;
if (ENABLE_IRQ && ENABLE_IRQ_TIMER && timer) begin
if (timer - 1 == 0)
next_irq_pending[irq_timer] = 1;
timer <= timer - 1;
end
if (ENABLE_IRQ) begin
next_irq_pending = next_irq_pending | irq;
end
decoder_trigger <= mem_do_rinst && mem_done;
decoder_trigger_q <= decoder_trigger;
decoder_pseudo_trigger <= 0;
decoder_pseudo_trigger_q <= decoder_pseudo_trigger;
do_waitirq <= 0;
trace_valid <= 0;
if (!ENABLE_TRACE)
trace_data <= 'bx;
if (!resetn) begin
reg_pc <= PROGADDR_RESET;
reg_next_pc <= PROGADDR_RESET;
if (ENABLE_COUNTERS)
count_instr <= 0;
latched_store <= 0;
latched_stalu <= 0;
latched_branch <= 0;
latched_trace <= 0;
latched_is_lu <= 0;
latched_is_lh <= 0;
latched_is_lb <= 0;
pcpi_valid <= 0;
pcpi_timeout <= 0;
irq_active <= 0;
irq_delay <= 0;
irq_mask <= ~0;
next_irq_pending = 0;
irq_state <= 0;
eoi <= 0;
timer <= 0;
if (~STACKADDR) begin
latched_store <= 1;
latched_rd <= 2;
reg_out <= STACKADDR;
end
cpu_state <= cpu_state_fetch;
end else
(* parallel_case, full_case *)
case (cpu_state)
cpu_state_trap: begin
trap <= 1;
end
cpu_state_fetch: begin
mem_do_rinst <= !decoder_trigger && !do_waitirq;
mem_wordsize <= 0;
current_pc = reg_next_pc;
(* parallel_case *)
case (1'b1)
latched_branch: begin
current_pc = latched_store ? (latched_stalu ? alu_out_q : reg_out) & ~1 : reg_next_pc;
`debug($display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + (latched_compr ? 2 : 4), current_pc);)
end
latched_store && !latched_branch: begin
`debug($display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out);)
end
ENABLE_IRQ && irq_state[0]: begin
current_pc = PROGADDR_IRQ;
irq_active <= 1;
mem_do_rinst <= 1;
end
ENABLE_IRQ && irq_state[1]: begin
eoi <= irq_pending & ~irq_mask;
next_irq_pending = next_irq_pending & irq_mask;
end
endcase
if (ENABLE_TRACE && latched_trace) begin
latched_trace <= 0;
trace_valid <= 1;
if (latched_branch)
trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_BRANCH | (current_pc & 32'hfffffffe);
else
trace_data <= (irq_active ? TRACE_IRQ : 0) | (latched_stalu ? alu_out_q : reg_out);
end
reg_pc <= current_pc;
reg_next_pc <= current_pc;
latched_store <= 0;
latched_stalu <= 0;
latched_branch <= 0;
latched_is_lu <= 0;
latched_is_lh <= 0;
latched_is_lb <= 0;
latched_rd <= decoded_rd;
latched_compr <= compressed_instr;
if (ENABLE_IRQ && ((decoder_trigger && !irq_active && !irq_delay && |(irq_pending & ~irq_mask)) || irq_state)) begin
irq_state <=
irq_state == 2'b00 ? 2'b01 :
irq_state == 2'b01 ? 2'b10 : 2'b00;
latched_compr <= latched_compr;
if (ENABLE_IRQ_QREGS)
latched_rd <= irqregs_offset | irq_state[0];
else
latched_rd <= irq_state[0] ? 4 : 3;
end else
if (ENABLE_IRQ && (decoder_trigger || do_waitirq) && instr_waitirq) begin
if (irq_pending) begin
latched_store <= 1;
reg_out <= irq_pending;
reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
mem_do_rinst <= 1;
end else
do_waitirq <= 1;
end else
if (decoder_trigger) begin
`debug($display("-- %-0t", $time);)
irq_delay <= irq_active;
reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
if (ENABLE_TRACE)
latched_trace <= 1;
if (ENABLE_COUNTERS) begin
count_instr <= count_instr + 1;
if (!ENABLE_COUNTERS64) count_instr[63:32] <= 0;
end
if (instr_jal) begin
mem_do_rinst <= 1;
reg_next_pc <= current_pc + decoded_imm_j;
latched_branch <= 1;
end else begin
mem_do_rinst <= 0;
mem_do_prefetch <= !instr_jalr && !instr_retirq;
cpu_state <= cpu_state_ld_rs1;
end
end
end
cpu_state_ld_rs1: begin
reg_op1 <= 'bx;
reg_op2 <= 'bx;
(* parallel_case *)
case (1'b1)
(CATCH_ILLINSN || WITH_PCPI) && instr_trap: begin
if (WITH_PCPI) begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
if (ENABLE_REGS_DUALPORT) begin
pcpi_valid <= 1;
`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
reg_sh <= cpuregs_rs2;
reg_op2 <= cpuregs_rs2;
dbg_rs2val <= cpuregs_rs2;
dbg_rs2val_valid <= 1;
if (pcpi_int_ready) begin
mem_do_rinst <= 1;
pcpi_valid <= 0;
reg_out <= pcpi_int_rd;
latched_store <= pcpi_int_wr;
cpu_state <= cpu_state_fetch;
end else
if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin
pcpi_valid <= 0;
`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
next_irq_pending[irq_ebreak] = 1;
cpu_state <= cpu_state_fetch;
end else
cpu_state <= cpu_state_trap;
end
end else begin
cpu_state <= cpu_state_ld_rs2;
end
end else begin
`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
next_irq_pending[irq_ebreak] = 1;
cpu_state <= cpu_state_fetch;
end else
cpu_state <= cpu_state_trap;
end
end
ENABLE_COUNTERS && is_rdcycle_rdcycleh_rdinstr_rdinstrh: begin
(* parallel_case, full_case *)
case (1'b1)
instr_rdcycle:
reg_out <= count_cycle[31:0];
instr_rdcycleh && ENABLE_COUNTERS64:
reg_out <= count_cycle[63:32];
instr_rdinstr:
reg_out <= count_instr[31:0];
instr_rdinstrh && ENABLE_COUNTERS64:
reg_out <= count_instr[63:32];
endcase
latched_store <= 1;
cpu_state <= cpu_state_fetch;
end
is_lui_auipc_jal: begin
reg_op1 <= instr_lui ? 0 : reg_pc;
reg_op2 <= decoded_imm;
if (TWO_CYCLE_ALU)
alu_wait <= 1;
else
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec;
end
ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_getq: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_out <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
latched_store <= 1;
cpu_state <= cpu_state_fetch;
end
ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_setq: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_out <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
latched_rd <= latched_rd | irqregs_offset;
latched_store <= 1;
cpu_state <= cpu_state_fetch;
end
ENABLE_IRQ && instr_retirq: begin
eoi <= 0;
irq_active <= 0;
latched_branch <= 1;
latched_store <= 1;
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_out <= CATCH_MISALIGN ? (cpuregs_rs1 & 32'h fffffffe) : cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
cpu_state <= cpu_state_fetch;
end
ENABLE_IRQ && instr_maskirq: begin
latched_store <= 1;
reg_out <= irq_mask;
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
irq_mask <= cpuregs_rs1 | MASKED_IRQ;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
cpu_state <= cpu_state_fetch;
end
ENABLE_IRQ && ENABLE_IRQ_TIMER && instr_timer: begin
latched_store <= 1;
reg_out <= timer;
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
timer <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
cpu_state <= cpu_state_fetch;
end
is_lb_lh_lw_lbu_lhu && !instr_trap: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
cpu_state <= cpu_state_ldmem;
mem_do_rinst <= 1;
end
is_slli_srli_srai && !BARREL_SHIFTER: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
reg_sh <= decoded_rs2;
cpu_state <= cpu_state_shift;
end
is_jalr_addi_slti_sltiu_xori_ori_andi, is_slli_srli_srai && BARREL_SHIFTER: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
reg_op2 <= is_slli_srli_srai && BARREL_SHIFTER ? decoded_rs2 : decoded_imm;
if (TWO_CYCLE_ALU)
alu_wait <= 1;
else
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec;
end
default: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
if (ENABLE_REGS_DUALPORT) begin
`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
reg_sh <= cpuregs_rs2;
reg_op2 <= cpuregs_rs2;
dbg_rs2val <= cpuregs_rs2;
dbg_rs2val_valid <= 1;
(* parallel_case *)
case (1'b1)
is_sb_sh_sw: begin
cpu_state <= cpu_state_stmem;
mem_do_rinst <= 1;
end
is_sll_srl_sra && !BARREL_SHIFTER: begin
cpu_state <= cpu_state_shift;
end
default: begin
if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
alu_wait <= 1;
end else
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec;
end
endcase
end else
cpu_state <= cpu_state_ld_rs2;
end
endcase
end
cpu_state_ld_rs2: begin
`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
reg_sh <= cpuregs_rs2;
reg_op2 <= cpuregs_rs2;
dbg_rs2val <= cpuregs_rs2;
dbg_rs2val_valid <= 1;
(* parallel_case *)
case (1'b1)
WITH_PCPI && instr_trap: begin
pcpi_valid <= 1;
if (pcpi_int_ready) begin
mem_do_rinst <= 1;
pcpi_valid <= 0;
reg_out <= pcpi_int_rd;
latched_store <= pcpi_int_wr;
cpu_state <= cpu_state_fetch;
end else
if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin
pcpi_valid <= 0;
`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
next_irq_pending[irq_ebreak] = 1;
cpu_state <= cpu_state_fetch;
end else
cpu_state <= cpu_state_trap;
end
end
is_sb_sh_sw: begin
cpu_state <= cpu_state_stmem;
mem_do_rinst <= 1;
end
is_sll_srl_sra && !BARREL_SHIFTER: begin
cpu_state <= cpu_state_shift;
end
default: begin
if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
alu_wait <= 1;
end else
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec;
end
endcase
end
cpu_state_exec: begin
reg_out <= reg_pc + decoded_imm;
if ((TWO_CYCLE_ALU || TWO_CYCLE_COMPARE) && (alu_wait || alu_wait_2)) begin
mem_do_rinst <= mem_do_prefetch && !alu_wait_2;
alu_wait <= alu_wait_2;
end else
if (is_beq_bne_blt_bge_bltu_bgeu) begin
latched_rd <= 0;
latched_store <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
latched_branch <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
if (mem_done)
cpu_state <= cpu_state_fetch;
if (TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0) begin
decoder_trigger <= 0;
set_mem_do_rinst = 1;
end
end else begin
latched_branch <= instr_jalr;
latched_store <= 1;
latched_stalu <= 1;
cpu_state <= cpu_state_fetch;
end
end
cpu_state_shift: begin
latched_store <= 1;
if (reg_sh == 0) begin
reg_out <= reg_op1;
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_fetch;
end else if (TWO_STAGE_SHIFT && reg_sh >= 4) begin
(* parallel_case, full_case *)
case (1'b1)
instr_slli || instr_sll: reg_op1 <= reg_op1 << 4;
instr_srli || instr_srl: reg_op1 <= reg_op1 >> 4;
instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 4;
endcase
reg_sh <= reg_sh - 4;
end else begin
(* parallel_case, full_case *)
case (1'b1)
instr_slli || instr_sll: reg_op1 <= reg_op1 << 1;
instr_srli || instr_srl: reg_op1 <= reg_op1 >> 1;
instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 1;
endcase
reg_sh <= reg_sh - 1;
end
end
cpu_state_stmem: begin
if (ENABLE_TRACE)
reg_out <= reg_op2;
if (!mem_do_prefetch || mem_done) begin
if (!mem_do_wdata) begin
(* parallel_case, full_case *)
case (1'b1)
instr_sb: mem_wordsize <= 2;
instr_sh: mem_wordsize <= 1;
instr_sw: mem_wordsize <= 0;
endcase
if (ENABLE_TRACE) begin
trace_valid <= 1;
trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff);
end
reg_op1 <= reg_op1 + decoded_imm;
set_mem_do_wdata = 1;
end
if (!mem_do_prefetch && mem_done) begin
cpu_state <= cpu_state_fetch;
decoder_trigger <= 1;
decoder_pseudo_trigger <= 1;
end
end
end
cpu_state_ldmem: begin
latched_store <= 1;
if (!mem_do_prefetch || mem_done) begin
if (!mem_do_rdata) begin
(* parallel_case, full_case *)
case (1'b1)
instr_lb || instr_lbu: mem_wordsize <= 2;
instr_lh || instr_lhu: mem_wordsize <= 1;
instr_lw: mem_wordsize <= 0;
endcase
latched_is_lu <= is_lbu_lhu_lw;
latched_is_lh <= instr_lh;
latched_is_lb <= instr_lb;
if (ENABLE_TRACE) begin
trace_valid <= 1;
trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff);
end
reg_op1 <= reg_op1 + decoded_imm;
set_mem_do_rdata = 1;
end
if (!mem_do_prefetch && mem_done) begin
(* parallel_case, full_case *)
case (1'b1)
latched_is_lu: reg_out <= mem_rdata_word;
latched_is_lh: reg_out <= $signed(mem_rdata_word[15:0]);
latched_is_lb: reg_out <= $signed(mem_rdata_word[7:0]);
endcase
decoder_trigger <= 1;
decoder_pseudo_trigger <= 1;
cpu_state <= cpu_state_fetch;
end
end
end
endcase
if (CATCH_MISALIGN && resetn && (mem_do_rdata || mem_do_wdata)) begin
if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin
`debug($display("MISALIGNED WORD: 0x%08x", reg_op1);)
if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
next_irq_pending[irq_buserror] = 1;
end else
cpu_state <= cpu_state_trap;
end
if (mem_wordsize == 1 && reg_op1[0] != 0) begin
`debug($display("MISALIGNED HALFWORD: 0x%08x", reg_op1);)
if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
next_irq_pending[irq_buserror] = 1;
end else
cpu_state <= cpu_state_trap;
end
end
if (CATCH_MISALIGN && resetn && mem_do_rinst && (COMPRESSED_ISA ? reg_pc[0] : |reg_pc[1:0])) begin
`debug($display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);)
if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
next_irq_pending[irq_buserror] = 1;
end else
cpu_state <= cpu_state_trap;
end
if (!CATCH_ILLINSN && decoder_trigger_q && !decoder_pseudo_trigger_q && instr_ecall_ebreak) begin
cpu_state <= cpu_state_trap;
end
if (!resetn || mem_done) begin
mem_do_prefetch <= 0;
mem_do_rinst <= 0;
mem_do_rdata <= 0;
mem_do_wdata <= 0;
end
if (set_mem_do_rinst)
mem_do_rinst <= 1;
if (set_mem_do_rdata)
mem_do_rdata <= 1;
if (set_mem_do_wdata)
mem_do_wdata <= 1;
irq_pending <= next_irq_pending & ~MASKED_IRQ;
if (!CATCH_MISALIGN) begin
if (COMPRESSED_ISA) begin
reg_pc[0] <= 0;
reg_next_pc[0] <= 0;
end else begin
reg_pc[1:0] <= 0;
reg_next_pc[1:0] <= 0;
end
end
current_pc = 'bx;
end
`ifdef RISCV_FORMAL
reg dbg_irq_call;
reg dbg_irq_enter;
reg [31:0] dbg_irq_ret;
always @(posedge clk) begin
rvfi_valid <= resetn && (launch_next_insn || trap) && dbg_valid_insn;
rvfi_order <= resetn ? rvfi_order + rvfi_valid : 0;
rvfi_insn <= dbg_insn_opcode;
rvfi_rs1_addr <= dbg_rs1val_valid ? dbg_insn_rs1 : 0;
rvfi_rs2_addr <= dbg_rs2val_valid ? dbg_insn_rs2 : 0;
rvfi_pc_rdata <= dbg_insn_addr;
rvfi_rs1_rdata <= dbg_rs1val_valid ? dbg_rs1val : 0;
rvfi_rs2_rdata <= dbg_rs2val_valid ? dbg_rs2val : 0;
rvfi_trap <= trap;
rvfi_halt <= trap;
rvfi_intr <= dbg_irq_enter;
rvfi_mode <= 3;
if (!resetn) begin
dbg_irq_call <= 0;
dbg_irq_enter <= 0;
end else
if (rvfi_valid) begin
dbg_irq_call <= 0;
dbg_irq_enter <= dbg_irq_call;
end else
if (irq_state == 1) begin
dbg_irq_call <= 1;
dbg_irq_ret <= next_pc;
end
if (!resetn) begin
rvfi_rd_addr <= 0;
rvfi_rd_wdata <= 0;
end else
if (cpuregs_write && !irq_state) begin
rvfi_rd_addr <= latched_rd;
rvfi_rd_wdata <= latched_rd ? cpuregs_wrdata : 0;
end else
if (rvfi_valid) begin
rvfi_rd_addr <= 0;
rvfi_rd_wdata <= 0;
end
casez (dbg_insn_opcode)
32'b 0000000_?????_000??_???_?????_0001011: begin // getq
rvfi_rs1_addr <= 0;
rvfi_rs1_rdata <= 0;
end
32'b 0000001_?????_?????_???_000??_0001011: begin // setq
rvfi_rd_addr <= 0;
rvfi_rd_wdata <= 0;
end
32'b 0000010_?????_00000_???_00000_0001011: begin // retirq
rvfi_rs1_addr <= 0;
rvfi_rs1_rdata <= 0;
end
endcase
if (!dbg_irq_call) begin
if (dbg_mem_instr) begin
rvfi_mem_addr <= 0;
rvfi_mem_rmask <= 0;
rvfi_mem_wmask <= 0;
rvfi_mem_rdata <= 0;
rvfi_mem_wdata <= 0;
end else
if (dbg_mem_valid && dbg_mem_ready) begin
rvfi_mem_addr <= dbg_mem_addr;
rvfi_mem_rmask <= dbg_mem_wstrb ? 0 : ~0;
rvfi_mem_wmask <= dbg_mem_wstrb;
rvfi_mem_rdata <= dbg_mem_rdata;
rvfi_mem_wdata <= dbg_mem_wdata;
end
end
end
always @* begin
rvfi_pc_wdata = dbg_irq_call ? dbg_irq_ret : dbg_insn_addr;
end
`endif
// Formal Verification
`ifdef FORMAL
reg [3:0] last_mem_nowait;
always @(posedge clk)
last_mem_nowait <= {last_mem_nowait, mem_ready || !mem_valid};
// stall the memory interface for max 4 cycles
restrict property (|last_mem_nowait || mem_ready || !mem_valid);
// resetn low in first cycle, after that resetn high
restrict property (resetn != $initstate);
// this just makes it much easier to read traces. uncomment as needed.
// assume property (mem_valid || !mem_ready);
reg ok;
always @* begin
if (resetn) begin
// instruction fetches are read-only
if (mem_valid && mem_instr)
assert (mem_wstrb == 0);
// cpu_state must be valid
ok = 0;
if (cpu_state == cpu_state_trap) ok = 1;
if (cpu_state == cpu_state_fetch) ok = 1;
if (cpu_state == cpu_state_ld_rs1) ok = 1;
if (cpu_state == cpu_state_ld_rs2) ok = !ENABLE_REGS_DUALPORT;
if (cpu_state == cpu_state_exec) ok = 1;
if (cpu_state == cpu_state_shift) ok = 1;
if (cpu_state == cpu_state_stmem) ok = 1;
if (cpu_state == cpu_state_ldmem) ok = 1;
assert (ok);
end
end
reg last_mem_la_read = 0;
reg last_mem_la_write = 0;
reg [31:0] last_mem_la_addr;
reg [31:0] last_mem_la_wdata;
reg [3:0] last_mem_la_wstrb = 0;
always @(posedge clk) begin
last_mem_la_read <= mem_la_read;
last_mem_la_write <= mem_la_write;
last_mem_la_addr <= mem_la_addr;
last_mem_la_wdata <= mem_la_wdata;
last_mem_la_wstrb <= mem_la_wstrb;
if (last_mem_la_read) begin
assert(mem_valid);
assert(mem_addr == last_mem_la_addr);
assert(mem_wstrb == 0);
end
if (last_mem_la_write) begin
assert(mem_valid);
assert(mem_addr == last_mem_la_addr);
assert(mem_wdata == last_mem_la_wdata);
assert(mem_wstrb == last_mem_la_wstrb);
end
if (mem_la_read || mem_la_write) begin
assert(!mem_valid || mem_ready);
end
end
`endif
endmodule
|
//*//***************************************************************
//* picorv32_wb
//***************************************************************//*
module picorv32_wb #(
parameter [ 0:0] ENABLE_COUNTERS = 1,
parameter [ 0:0] ENABLE_COUNTERS64 = 1,
parameter [ 0:0] ENABLE_REGS_16_31 = 1,
parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
parameter [ 0:0] TWO_STAGE_SHIFT = 1,
parameter [ 0:0] BARREL_SHIFTER = 0,
parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
parameter [ 0:0] TWO_CYCLE_ALU = 0,
parameter [ 0:0] COMPRESSED_ISA = 0,
parameter [ 0:0] CATCH_MISALIGN = 1,
parameter [ 0:0] CATCH_ILLINSN = 1,
parameter [ 0:0] ENABLE_PCPI = 0,
parameter [ 0:0] ENABLE_MUL = 0,
parameter [ 0:0] ENABLE_FAST_MUL = 0,
parameter [ 0:0] ENABLE_DIV = 0,
parameter [ 0:0] ENABLE_IRQ = 0,
parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
parameter [ 0:0] ENABLE_TRACE = 0,
parameter [ 0:0] REGS_INIT_ZERO = 0,
parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
parameter [31:0] STACKADDR = 32'h ffff_ffff
) (
output trap,
// Wishbone interfaces
input wb_rst_i,
input wb_clk_i,
output reg [31:0] wbm_adr_o,
output reg [31:0] wbm_dat_o,
input [31:0] wbm_dat_i,
output reg wbm_we_o,
output reg [3:0] wbm_sel_o,
output reg wbm_stb_o,
input wbm_ack_i,
output reg wbm_cyc_o,
// Pico Co-Processor Interface (PCPI)
output pcpi_valid,
output [31:0] pcpi_insn,
output [31:0] pcpi_rs1,
output [31:0] pcpi_rs2,
input pcpi_wr,
input [31:0] pcpi_rd,
input pcpi_wait,
input pcpi_ready,
// IRQ interface
input [31:0] irq,
output [31:0] eoi,
`ifdef RISCV_FORMAL
output rvfi_valid,
output [63:0] rvfi_order,
output [31:0] rvfi_insn,
output rvfi_trap,
output rvfi_halt,
output rvfi_intr,
output [ 4:0] rvfi_rs1_addr,
output [ 4:0] rvfi_rs2_addr,
output [31:0] rvfi_rs1_rdata,
output [31:0] rvfi_rs2_rdata,
output [ 4:0] rvfi_rd_addr,
output [31:0] rvfi_rd_wdata,
output [31:0] rvfi_pc_rdata,
output [31:0] rvfi_pc_wdata,
output [31:0] rvfi_mem_addr,
output [ 3:0] rvfi_mem_rmask,
output [ 3:0] rvfi_mem_wmask,
output [31:0] rvfi_mem_rdata,
output [31:0] rvfi_mem_wdata,
`endif
// Trace Interface
output trace_valid,
output [35:0] trace_data,
output mem_instr
);
wire mem_valid;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [ 3:0] mem_wstrb;
reg mem_ready;
reg [31:0] mem_rdata;
wire clk;
wire resetn;
assign clk = wb_clk_i;
assign resetn = ~wb_rst_i;
picorv32 #(
.ENABLE_COUNTERS (ENABLE_COUNTERS ),
.ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ),
.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
.TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
.BARREL_SHIFTER (BARREL_SHIFTER ),
.TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ),
.TWO_CYCLE_ALU (TWO_CYCLE_ALU ),
.COMPRESSED_ISA (COMPRESSED_ISA ),
.CATCH_MISALIGN (CATCH_MISALIGN ),
.CATCH_ILLINSN (CATCH_ILLINSN ),
.ENABLE_PCPI (ENABLE_PCPI ),
.ENABLE_MUL (ENABLE_MUL ),
.ENABLE_FAST_MUL (ENABLE_FAST_MUL ),
.ENABLE_DIV (ENABLE_DIV ),
.ENABLE_IRQ (ENABLE_IRQ ),
.ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
.ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
.ENABLE_TRACE (ENABLE_TRACE ),
.REGS_INIT_ZERO (REGS_INIT_ZERO ),
.MASKED_IRQ (MASKED_IRQ ),
.LATCHED_IRQ (LATCHED_IRQ ),
.PROGADDR_RESET (PROGADDR_RESET ),
.PROGADDR_IRQ (PROGADDR_IRQ ),
.STACKADDR (STACKADDR )
) picorv32_core (
.clk (clk ),
.resetn (resetn),
.trap (trap ),
.mem_valid(mem_valid),
.mem_addr (mem_addr ),
.mem_wdata(mem_wdata),
.mem_wstrb(mem_wstrb),
.mem_instr(mem_instr),
.mem_ready(mem_ready),
.mem_rdata(mem_rdata),
.pcpi_valid(pcpi_valid),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_wr ),
.pcpi_rd (pcpi_rd ),
.pcpi_wait (pcpi_wait ),
.pcpi_ready(pcpi_ready),
.irq(irq),
.eoi(eoi),
`ifdef RISCV_FORMAL
.rvfi_valid (rvfi_valid ),
.rvfi_order (rvfi_order ),
.rvfi_insn (rvfi_insn ),
.rvfi_trap (rvfi_trap ),
.rvfi_halt (rvfi_halt ),
.rvfi_intr (rvfi_intr ),
.rvfi_rs1_addr (rvfi_rs1_addr ),
.rvfi_rs2_addr (rvfi_rs2_addr ),
.rvfi_rs1_rdata(rvfi_rs1_rdata),
.rvfi_rs2_rdata(rvfi_rs2_rdata),
.rvfi_rd_addr (rvfi_rd_addr ),
.rvfi_rd_wdata (rvfi_rd_wdata ),
.rvfi_pc_rdata (rvfi_pc_rdata ),
.rvfi_pc_wdata (rvfi_pc_wdata ),
.rvfi_mem_addr (rvfi_mem_addr ),
.rvfi_mem_rmask(rvfi_mem_rmask),
.rvfi_mem_wmask(rvfi_mem_wmask),
.rvfi_mem_rdata(rvfi_mem_rdata),
.rvfi_mem_wdata(rvfi_mem_wdata),
`endif
.trace_valid(trace_valid),
.trace_data (trace_data)
);
localparam IDLE = 2'b00;
localparam WBSTART = 2'b01;
localparam WBEND = 2'b10;
reg [1:0] state;
wire we;
assign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]);
always @(posedge wb_clk_i) begin
if (wb_rst_i) begin
wbm_adr_o <= 0;
wbm_dat_o <= 0;
wbm_we_o <= 0;
wbm_sel_o <= 0;
wbm_stb_o <= 0;
wbm_cyc_o <= 0;
state <= IDLE;
end else begin
case (state)
IDLE: begin
if (mem_valid) begin
wbm_adr_o <= mem_addr;
wbm_dat_o <= mem_wdata;
wbm_we_o <= we;
wbm_sel_o <= mem_wstrb;
wbm_stb_o <= 1'b1;
wbm_cyc_o <= 1'b1;
state <= WBSTART;
end else begin
mem_ready <= 1'b0;
wbm_stb_o <= 1'b0;
wbm_cyc_o <= 1'b0;
wbm_we_o <= 1'b0;
end
end
WBSTART:begin
if (wbm_ack_i) begin
mem_rdata <= wbm_dat_i;
mem_ready <= 1'b1;
state <= WBEND;
wbm_stb_o <= 1'b0;
wbm_cyc_o <= 1'b0;
wbm_we_o <= 1'b0;
end
end
WBEND: begin
mem_ready <= 1'b0;
state <= IDLE;
end
default:
state <= IDLE;
endcase
end
end
endmodule
|
//*//***************************************************************
//* picorv32_wb
//***************************************************************//*
module picorv32_wb_i #(
parameter [ 0:0] ENABLE_COUNTERS = 1,
parameter [ 0:0] ENABLE_COUNTERS64 = 1,
parameter [ 0:0] ENABLE_REGS_16_31 = 1,
parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
parameter [ 0:0] TWO_STAGE_SHIFT = 1,
parameter [ 0:0] BARREL_SHIFTER = 0,
parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
parameter [ 0:0] TWO_CYCLE_ALU = 0,
parameter [ 0:0] COMPRESSED_ISA = 0,
parameter [ 0:0] CATCH_MISALIGN = 1,
parameter [ 0:0] CATCH_ILLINSN = 1,
parameter [ 0:0] ENABLE_PCPI = 0,
parameter [ 0:0] ENABLE_MUL = 0,
parameter [ 0:0] ENABLE_FAST_MUL = 0,
parameter [ 0:0] ENABLE_DIV = 0,
parameter [ 0:0] ENABLE_IRQ = 0,
parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
parameter [ 0:0] ENABLE_TRACE = 0,
parameter [ 0:0] REGS_INIT_ZERO = 0,
parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
parameter [31:0] STACKADDR = 32'h ffff_ffff
) (
output trap,
// Wishbone interfaces
input wb_rst_i,
input wb_clk_i,
output reg [31:0] wbm_adr_o,
output reg [31:0] wbm_dat_o,
input [31:0] wbm_dat_i,
output reg wbm_we_o,
output reg [3:0] wbm_sel_o,
output reg wbm_stb_o,
input wbm_ack_i,
output reg wbm_cyc_o,
// Pico Co-Processor Interface (PCPI)
output pcpi_valid,
output [31:0] pcpi_insn,
output [31:0] pcpi_rs1,
output [31:0] pcpi_rs2,
input pcpi_wr,
input [31:0] pcpi_rd,
input pcpi_wait,
input pcpi_ready,
// IRQ interface
input [31:0] irq,
output [31:0] eoi,
`ifdef RISCV_FORMAL
output rvfi_valid,
output [63:0] rvfi_order,
output [31:0] rvfi_insn,
output rvfi_trap,
output rvfi_halt,
output rvfi_intr,
output [ 4:0] rvfi_rs1_addr,
output [ 4:0] rvfi_rs2_addr,
output [31:0] rvfi_rs1_rdata,
output [31:0] rvfi_rs2_rdata,
output [ 4:0] rvfi_rd_addr,
output [31:0] rvfi_rd_wdata,
output [31:0] rvfi_pc_rdata,
output [31:0] rvfi_pc_wdata,
output [31:0] rvfi_mem_addr,
output [ 3:0] rvfi_mem_rmask,
output [ 3:0] rvfi_mem_wmask,
output [31:0] rvfi_mem_rdata,
output [31:0] rvfi_mem_wdata,
`endif
// Trace Interface
output trace_valid,
output [35:0] trace_data,
output mem_instr
);
wire mem_valid;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [ 3:0] mem_wstrb;
reg mem_ready;
reg [31:0] mem_rdata;
wire clk;
wire resetn;
assign clk = wb_clk_i;
assign resetn = ~wb_rst_i;
picorv32 #(
.ENABLE_COUNTERS (ENABLE_COUNTERS ),
.ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ),
.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
.TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
.BARREL_SHIFTER (BARREL_SHIFTER ),
.TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ),
.TWO_CYCLE_ALU (TWO_CYCLE_ALU ),
.COMPRESSED_ISA (COMPRESSED_ISA ),
.CATCH_MISALIGN (CATCH_MISALIGN ),
.CATCH_ILLINSN (CATCH_ILLINSN ),
.ENABLE_PCPI (ENABLE_PCPI ),
.ENABLE_MUL (ENABLE_MUL ),
.ENABLE_FAST_MUL (ENABLE_FAST_MUL ),
.ENABLE_DIV (ENABLE_DIV ),
.ENABLE_IRQ (ENABLE_IRQ ),
.ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
.ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
.ENABLE_TRACE (ENABLE_TRACE ),
.REGS_INIT_ZERO (REGS_INIT_ZERO ),
.MASKED_IRQ (MASKED_IRQ ),
.LATCHED_IRQ (LATCHED_IRQ ),
.PROGADDR_RESET (PROGADDR_RESET ),
.PROGADDR_IRQ (PROGADDR_IRQ ),
.STACKADDR (STACKADDR )
) picorv32_core (
.clk (clk ),
.resetn (resetn),
.trap (trap ),
.mem_valid(mem_valid),
.mem_addr (mem_addr ),
.mem_wdata(mem_wdata),
.mem_wstrb(mem_wstrb),
.mem_instr(mem_instr),
.mem_ready(mem_ready),
.mem_rdata(mem_rdata),
.pcpi_valid(pcpi_valid),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_wr ),
.pcpi_rd (pcpi_rd ),
.pcpi_wait (pcpi_wait ),
.pcpi_ready(pcpi_ready),
.irq(irq),
.eoi(eoi),
`ifdef RISCV_FORMAL
.rvfi_valid (rvfi_valid ),
.rvfi_order (rvfi_order ),
.rvfi_insn (rvfi_insn ),
.rvfi_trap (rvfi_trap ),
.rvfi_halt (rvfi_halt ),
.rvfi_intr (rvfi_intr ),
.rvfi_rs1_addr (rvfi_rs1_addr ),
.rvfi_rs2_addr (rvfi_rs2_addr ),
.rvfi_rs1_rdata(rvfi_rs1_rdata),
.rvfi_rs2_rdata(rvfi_rs2_rdata),
.rvfi_rd_addr (rvfi_rd_addr ),
.rvfi_rd_wdata (rvfi_rd_wdata ),
.rvfi_pc_rdata (rvfi_pc_rdata ),
.rvfi_pc_wdata (rvfi_pc_wdata ),
.rvfi_mem_addr (rvfi_mem_addr ),
.rvfi_mem_rmask(rvfi_mem_rmask),
.rvfi_mem_wmask(rvfi_mem_wmask),
.rvfi_mem_rdata(rvfi_mem_rdata),
.rvfi_mem_wdata(rvfi_mem_wdata),
`endif
.trace_valid(trace_valid),
.trace_data (trace_data)
);
localparam IDLE = 2'b00;
localparam WBSTART = 2'b01;
localparam WBEND = 2'b10;
reg [1:0] state;
wire we;
assign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]);
always @(posedge wb_clk_i) begin
if (wb_rst_i) begin
wbm_adr_o <= 0;
wbm_dat_o <= 0;
wbm_we_o <= 0;
wbm_sel_o <= 0;
wbm_stb_o <= 0;
wbm_cyc_o <= 0;
state <= IDLE;
end else begin
case (state)
IDLE: begin
if (mem_valid) begin
wbm_adr_o <= mem_addr;
wbm_dat_o <= mem_wdata;
wbm_we_o <= we;
wbm_sel_o <= mem_wstrb;
wbm_stb_o <= 1'b1;
wbm_cyc_o <= 1'b1;
state <= WBSTART;
end else begin
mem_ready <= 1'b0;
wbm_stb_o <= 1'b0;
wbm_cyc_o <= 1'b0;
wbm_we_o <= 1'b0;
end
end
WBSTART:begin
if (wbm_ack_i) begin
mem_rdata <= wbm_dat_i;
mem_ready <= 1'b1;
state <= WBEND;
wbm_stb_o <= 1'b0;
wbm_cyc_o <= 1'b0;
wbm_we_o <= 1'b0;
end
end
WBEND: begin
mem_ready <= 1'b0;
state <= IDLE;
end
default:
state <= IDLE;
endcase
end
end
endmodule
|
//*//***************************************************************
//* picorv32_wb
//***************************************************************//*
module picorv32_wb_ic #(
parameter [ 0:0] ENABLE_COUNTERS = 1,
parameter [ 0:0] ENABLE_COUNTERS64 = 1,
parameter [ 0:0] ENABLE_REGS_16_31 = 1,
parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
parameter [ 0:0] TWO_STAGE_SHIFT = 1,
parameter [ 0:0] BARREL_SHIFTER = 0,
parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
parameter [ 0:0] TWO_CYCLE_ALU = 0,
parameter [ 0:0] COMPRESSED_ISA = 0,
parameter [ 0:0] CATCH_MISALIGN = 1,
parameter [ 0:0] CATCH_ILLINSN = 1,
parameter [ 0:0] ENABLE_PCPI = 0,
parameter [ 0:0] ENABLE_MUL = 0,
parameter [ 0:0] ENABLE_FAST_MUL = 0,
parameter [ 0:0] ENABLE_DIV = 0,
parameter [ 0:0] ENABLE_IRQ = 0,
parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
parameter [ 0:0] ENABLE_TRACE = 0,
parameter [ 0:0] REGS_INIT_ZERO = 0,
parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
parameter [31:0] STACKADDR = 32'h ffff_ffff
) (
output trap,
// Wishbone interfaces
input wb_rst_i,
input wb_clk_i,
output reg [31:0] wbm_adr_o,
output reg [31:0] wbm_dat_o,
input [31:0] wbm_dat_i,
output reg wbm_we_o,
output reg [3:0] wbm_sel_o,
output reg wbm_stb_o,
input wbm_ack_i,
output reg wbm_cyc_o,
// Pico Co-Processor Interface (PCPI)
output pcpi_valid,
output [31:0] pcpi_insn,
output [31:0] pcpi_rs1,
output [31:0] pcpi_rs2,
input pcpi_wr,
input [31:0] pcpi_rd,
input pcpi_wait,
input pcpi_ready,
// IRQ interface
input [31:0] irq,
output [31:0] eoi,
`ifdef RISCV_FORMAL
output rvfi_valid,
output [63:0] rvfi_order,
output [31:0] rvfi_insn,
output rvfi_trap,
output rvfi_halt,
output rvfi_intr,
output [ 4:0] rvfi_rs1_addr,
output [ 4:0] rvfi_rs2_addr,
output [31:0] rvfi_rs1_rdata,
output [31:0] rvfi_rs2_rdata,
output [ 4:0] rvfi_rd_addr,
output [31:0] rvfi_rd_wdata,
output [31:0] rvfi_pc_rdata,
output [31:0] rvfi_pc_wdata,
output [31:0] rvfi_mem_addr,
output [ 3:0] rvfi_mem_rmask,
output [ 3:0] rvfi_mem_wmask,
output [31:0] rvfi_mem_rdata,
output [31:0] rvfi_mem_wdata,
`endif
// Trace Interface
output trace_valid,
output [35:0] trace_data,
output mem_instr
);
wire mem_valid;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [ 3:0] mem_wstrb;
reg mem_ready;
reg [31:0] mem_rdata;
wire clk;
wire resetn;
assign clk = wb_clk_i;
assign resetn = ~wb_rst_i;
picorv32 #(
.ENABLE_COUNTERS (ENABLE_COUNTERS ),
.ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ),
.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
.TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
.BARREL_SHIFTER (BARREL_SHIFTER ),
.TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ),
.TWO_CYCLE_ALU (TWO_CYCLE_ALU ),
.COMPRESSED_ISA (COMPRESSED_ISA ),
.CATCH_MISALIGN (CATCH_MISALIGN ),
.CATCH_ILLINSN (CATCH_ILLINSN ),
.ENABLE_PCPI (ENABLE_PCPI ),
.ENABLE_MUL (ENABLE_MUL ),
.ENABLE_FAST_MUL (ENABLE_FAST_MUL ),
.ENABLE_DIV (ENABLE_DIV ),
.ENABLE_IRQ (ENABLE_IRQ ),
.ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
.ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
.ENABLE_TRACE (ENABLE_TRACE ),
.REGS_INIT_ZERO (REGS_INIT_ZERO ),
.MASKED_IRQ (MASKED_IRQ ),
.LATCHED_IRQ (LATCHED_IRQ ),
.PROGADDR_RESET (PROGADDR_RESET ),
.PROGADDR_IRQ (PROGADDR_IRQ ),
.STACKADDR (STACKADDR )
) picorv32_core (
.clk (clk ),
.resetn (resetn),
.trap (trap ),
.mem_valid(mem_valid),
.mem_addr (mem_addr ),
.mem_wdata(mem_wdata),
.mem_wstrb(mem_wstrb),
.mem_instr(mem_instr),
.mem_ready(mem_ready),
.mem_rdata(mem_rdata),
.pcpi_valid(pcpi_valid),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_wr ),
.pcpi_rd (pcpi_rd ),
.pcpi_wait (pcpi_wait ),
.pcpi_ready(pcpi_ready),
.irq(irq),
.eoi(eoi),
`ifdef RISCV_FORMAL
.rvfi_valid (rvfi_valid ),
.rvfi_order (rvfi_order ),
.rvfi_insn (rvfi_insn ),
.rvfi_trap (rvfi_trap ),
.rvfi_halt (rvfi_halt ),
.rvfi_intr (rvfi_intr ),
.rvfi_rs1_addr (rvfi_rs1_addr ),
.rvfi_rs2_addr (rvfi_rs2_addr ),
.rvfi_rs1_rdata(rvfi_rs1_rdata),
.rvfi_rs2_rdata(rvfi_rs2_rdata),
.rvfi_rd_addr (rvfi_rd_addr ),
.rvfi_rd_wdata (rvfi_rd_wdata ),
.rvfi_pc_rdata (rvfi_pc_rdata ),
.rvfi_pc_wdata (rvfi_pc_wdata ),
.rvfi_mem_addr (rvfi_mem_addr ),
.rvfi_mem_rmask(rvfi_mem_rmask),
.rvfi_mem_wmask(rvfi_mem_wmask),
.rvfi_mem_rdata(rvfi_mem_rdata),
.rvfi_mem_wdata(rvfi_mem_wdata),
`endif
.trace_valid(trace_valid),
.trace_data (trace_data)
);
localparam IDLE = 2'b00;
localparam WBSTART = 2'b01;
localparam WBEND = 2'b10;
reg [1:0] state;
wire we;
assign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]);
always @(posedge wb_clk_i) begin
if (wb_rst_i) begin
wbm_adr_o <= 0;
wbm_dat_o <= 0;
wbm_we_o <= 0;
wbm_sel_o <= 0;
wbm_stb_o <= 0;
wbm_cyc_o <= 0;
state <= IDLE;
end else begin
case (state)
IDLE: begin
if (mem_valid) begin
wbm_adr_o <= mem_addr;
wbm_dat_o <= mem_wdata;
wbm_we_o <= we;
wbm_sel_o <= mem_wstrb;
wbm_stb_o <= 1'b1;
wbm_cyc_o <= 1'b1;
state <= WBSTART;
end else begin
mem_ready <= 1'b0;
wbm_stb_o <= 1'b0;
wbm_cyc_o <= 1'b0;
wbm_we_o <= 1'b0;
end
end
WBSTART:begin
if (wbm_ack_i) begin
mem_rdata <= wbm_dat_i;
mem_ready <= 1'b1;
state <= WBEND;
wbm_stb_o <= 1'b0;
wbm_cyc_o <= 1'b0;
wbm_we_o <= 1'b0;
end
end
WBEND: begin
mem_ready <= 1'b0;
state <= IDLE;
end
default:
state <= IDLE;
endcase
end
end
endmodule
|
//*//***************************************************************
//* picorv32_wb
//***************************************************************//*
module picorv32_wb_im #(
parameter [ 0:0] ENABLE_COUNTERS = 1,
parameter [ 0:0] ENABLE_COUNTERS64 = 1,
parameter [ 0:0] ENABLE_REGS_16_31 = 1,
parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
parameter [ 0:0] TWO_STAGE_SHIFT = 1,
parameter [ 0:0] BARREL_SHIFTER = 0,
parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
parameter [ 0:0] TWO_CYCLE_ALU = 0,
parameter [ 0:0] COMPRESSED_ISA = 0,
parameter [ 0:0] CATCH_MISALIGN = 1,
parameter [ 0:0] CATCH_ILLINSN = 1,
parameter [ 0:0] ENABLE_PCPI = 0,
parameter [ 0:0] ENABLE_MUL = 0,
parameter [ 0:0] ENABLE_FAST_MUL = 0,
parameter [ 0:0] ENABLE_DIV = 0,
parameter [ 0:0] ENABLE_IRQ = 0,
parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
parameter [ 0:0] ENABLE_TRACE = 0,
parameter [ 0:0] REGS_INIT_ZERO = 0,
parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
parameter [31:0] STACKADDR = 32'h ffff_ffff
) (
output trap,
// Wishbone interfaces
input wb_rst_i,
input wb_clk_i,
output reg [31:0] wbm_adr_o,
output reg [31:0] wbm_dat_o,
input [31:0] wbm_dat_i,
output reg wbm_we_o,
output reg [3:0] wbm_sel_o,
output reg wbm_stb_o,
input wbm_ack_i,
output reg wbm_cyc_o,
// Pico Co-Processor Interface (PCPI)
output pcpi_valid,
output [31:0] pcpi_insn,
output [31:0] pcpi_rs1,
output [31:0] pcpi_rs2,
input pcpi_wr,
input [31:0] pcpi_rd,
input pcpi_wait,
input pcpi_ready,
// IRQ interface
input [31:0] irq,
output [31:0] eoi,
`ifdef RISCV_FORMAL
output rvfi_valid,
output [63:0] rvfi_order,
output [31:0] rvfi_insn,
output rvfi_trap,
output rvfi_halt,
output rvfi_intr,
output [ 4:0] rvfi_rs1_addr,
output [ 4:0] rvfi_rs2_addr,
output [31:0] rvfi_rs1_rdata,
output [31:0] rvfi_rs2_rdata,
output [ 4:0] rvfi_rd_addr,
output [31:0] rvfi_rd_wdata,
output [31:0] rvfi_pc_rdata,
output [31:0] rvfi_pc_wdata,
output [31:0] rvfi_mem_addr,
output [ 3:0] rvfi_mem_rmask,
output [ 3:0] rvfi_mem_wmask,
output [31:0] rvfi_mem_rdata,
output [31:0] rvfi_mem_wdata,
`endif
// Trace Interface
output trace_valid,
output [35:0] trace_data,
output mem_instr
);
wire mem_valid;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [ 3:0] mem_wstrb;
reg mem_ready;
reg [31:0] mem_rdata;
wire clk;
wire resetn;
assign clk = wb_clk_i;
assign resetn = ~wb_rst_i;
picorv32 #(
.ENABLE_COUNTERS (ENABLE_COUNTERS ),
.ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ),
.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
.TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
.BARREL_SHIFTER (BARREL_SHIFTER ),
.TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ),
.TWO_CYCLE_ALU (TWO_CYCLE_ALU ),
.COMPRESSED_ISA (COMPRESSED_ISA ),
.CATCH_MISALIGN (CATCH_MISALIGN ),
.CATCH_ILLINSN (CATCH_ILLINSN ),
.ENABLE_PCPI (ENABLE_PCPI ),
.ENABLE_MUL (ENABLE_MUL ),
.ENABLE_FAST_MUL (ENABLE_FAST_MUL ),
.ENABLE_DIV (ENABLE_DIV ),
.ENABLE_IRQ (ENABLE_IRQ ),
.ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
.ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
.ENABLE_TRACE (ENABLE_TRACE ),
.REGS_INIT_ZERO (REGS_INIT_ZERO ),
.MASKED_IRQ (MASKED_IRQ ),
.LATCHED_IRQ (LATCHED_IRQ ),
.PROGADDR_RESET (PROGADDR_RESET ),
.PROGADDR_IRQ (PROGADDR_IRQ ),
.STACKADDR (STACKADDR )
) picorv32_core (
.clk (clk ),
.resetn (resetn),
.trap (trap ),
.mem_valid(mem_valid),
.mem_addr (mem_addr ),
.mem_wdata(mem_wdata),
.mem_wstrb(mem_wstrb),
.mem_instr(mem_instr),
.mem_ready(mem_ready),
.mem_rdata(mem_rdata),
.pcpi_valid(pcpi_valid),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_wr ),
.pcpi_rd (pcpi_rd ),
.pcpi_wait (pcpi_wait ),
.pcpi_ready(pcpi_ready),
.irq(irq),
.eoi(eoi),
`ifdef RISCV_FORMAL
.rvfi_valid (rvfi_valid ),
.rvfi_order (rvfi_order ),
.rvfi_insn (rvfi_insn ),
.rvfi_trap (rvfi_trap ),
.rvfi_halt (rvfi_halt ),
.rvfi_intr (rvfi_intr ),
.rvfi_rs1_addr (rvfi_rs1_addr ),
.rvfi_rs2_addr (rvfi_rs2_addr ),
.rvfi_rs1_rdata(rvfi_rs1_rdata),
.rvfi_rs2_rdata(rvfi_rs2_rdata),
.rvfi_rd_addr (rvfi_rd_addr ),
.rvfi_rd_wdata (rvfi_rd_wdata ),
.rvfi_pc_rdata (rvfi_pc_rdata ),
.rvfi_pc_wdata (rvfi_pc_wdata ),
.rvfi_mem_addr (rvfi_mem_addr ),
.rvfi_mem_rmask(rvfi_mem_rmask),
.rvfi_mem_wmask(rvfi_mem_wmask),
.rvfi_mem_rdata(rvfi_mem_rdata),
.rvfi_mem_wdata(rvfi_mem_wdata),
`endif
.trace_valid(trace_valid),
.trace_data (trace_data)
);
localparam IDLE = 2'b00;
localparam WBSTART = 2'b01;
localparam WBEND = 2'b10;
reg [1:0] state;
wire we;
assign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]);
always @(posedge wb_clk_i) begin
if (wb_rst_i) begin
wbm_adr_o <= 0;
wbm_dat_o <= 0;
wbm_we_o <= 0;
wbm_sel_o <= 0;
wbm_stb_o <= 0;
wbm_cyc_o <= 0;
state <= IDLE;
end else begin
case (state)
IDLE: begin
if (mem_valid) begin
wbm_adr_o <= mem_addr;
wbm_dat_o <= mem_wdata;
wbm_we_o <= we;
wbm_sel_o <= mem_wstrb;
wbm_stb_o <= 1'b1;
wbm_cyc_o <= 1'b1;
state <= WBSTART;
end else begin
mem_ready <= 1'b0;
wbm_stb_o <= 1'b0;
wbm_cyc_o <= 1'b0;
wbm_we_o <= 1'b0;
end
end
WBSTART:begin
if (wbm_ack_i) begin
mem_rdata <= wbm_dat_i;
mem_ready <= 1'b1;
state <= WBEND;
wbm_stb_o <= 1'b0;
wbm_cyc_o <= 1'b0;
wbm_we_o <= 1'b0;
end
end
WBEND: begin
mem_ready <= 1'b0;
state <= IDLE;
end
default:
state <= IDLE;
endcase
end
end
endmodule
|
//*//***************************************************************
//* picorv32_wb
//***************************************************************//*
module picorv32_wb_imc #(
parameter [ 0:0] ENABLE_COUNTERS = 1,
parameter [ 0:0] ENABLE_COUNTERS64 = 1,
parameter [ 0:0] ENABLE_REGS_16_31 = 1,
parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
parameter [ 0:0] TWO_STAGE_SHIFT = 1,
parameter [ 0:0] BARREL_SHIFTER = 0,
parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
parameter [ 0:0] TWO_CYCLE_ALU = 0,
parameter [ 0:0] COMPRESSED_ISA = 0,
parameter [ 0:0] CATCH_MISALIGN = 1,
parameter [ 0:0] CATCH_ILLINSN = 1,
parameter [ 0:0] ENABLE_PCPI = 0,
parameter [ 0:0] ENABLE_MUL = 0,
parameter [ 0:0] ENABLE_FAST_MUL = 0,
parameter [ 0:0] ENABLE_DIV = 0,
parameter [ 0:0] ENABLE_IRQ = 0,
parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
parameter [ 0:0] ENABLE_TRACE = 0,
parameter [ 0:0] REGS_INIT_ZERO = 0,
parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
parameter [31:0] STACKADDR = 32'h ffff_ffff
) (
output trap,
// Wishbone interfaces
input wb_rst_i,
input wb_clk_i,
output reg [31:0] wbm_adr_o,
output reg [31:0] wbm_dat_o,
input [31:0] wbm_dat_i,
output reg wbm_we_o,
output reg [3:0] wbm_sel_o,
output reg wbm_stb_o,
input wbm_ack_i,
output reg wbm_cyc_o,
// Pico Co-Processor Interface (PCPI)
output pcpi_valid,
output [31:0] pcpi_insn,
output [31:0] pcpi_rs1,
output [31:0] pcpi_rs2,
input pcpi_wr,
input [31:0] pcpi_rd,
input pcpi_wait,
input pcpi_ready,
// IRQ interface
input [31:0] irq,
output [31:0] eoi,
`ifdef RISCV_FORMAL
output rvfi_valid,
output [63:0] rvfi_order,
output [31:0] rvfi_insn,
output rvfi_trap,
output rvfi_halt,
output rvfi_intr,
output [ 4:0] rvfi_rs1_addr,
output [ 4:0] rvfi_rs2_addr,
output [31:0] rvfi_rs1_rdata,
output [31:0] rvfi_rs2_rdata,
output [ 4:0] rvfi_rd_addr,
output [31:0] rvfi_rd_wdata,
output [31:0] rvfi_pc_rdata,
output [31:0] rvfi_pc_wdata,
output [31:0] rvfi_mem_addr,
output [ 3:0] rvfi_mem_rmask,
output [ 3:0] rvfi_mem_wmask,
output [31:0] rvfi_mem_rdata,
output [31:0] rvfi_mem_wdata,
`endif
// Trace Interface
output trace_valid,
output [35:0] trace_data,
output mem_instr
);
wire mem_valid;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [ 3:0] mem_wstrb;
reg mem_ready;
reg [31:0] mem_rdata;
wire clk;
wire resetn;
assign clk = wb_clk_i;
assign resetn = ~wb_rst_i;
picorv32 #(
.ENABLE_COUNTERS (ENABLE_COUNTERS ),
.ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ),
.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
.TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
.BARREL_SHIFTER (BARREL_SHIFTER ),
.TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ),
.TWO_CYCLE_ALU (TWO_CYCLE_ALU ),
.COMPRESSED_ISA (COMPRESSED_ISA ),
.CATCH_MISALIGN (CATCH_MISALIGN ),
.CATCH_ILLINSN (CATCH_ILLINSN ),
.ENABLE_PCPI (ENABLE_PCPI ),
.ENABLE_MUL (ENABLE_MUL ),
.ENABLE_FAST_MUL (ENABLE_FAST_MUL ),
.ENABLE_DIV (ENABLE_DIV ),
.ENABLE_IRQ (ENABLE_IRQ ),
.ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
.ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
.ENABLE_TRACE (ENABLE_TRACE ),
.REGS_INIT_ZERO (REGS_INIT_ZERO ),
.MASKED_IRQ (MASKED_IRQ ),
.LATCHED_IRQ (LATCHED_IRQ ),
.PROGADDR_RESET (PROGADDR_RESET ),
.PROGADDR_IRQ (PROGADDR_IRQ ),
.STACKADDR (STACKADDR )
) picorv32_core (
.clk (clk ),
.resetn (resetn),
.trap (trap ),
.mem_valid(mem_valid),
.mem_addr (mem_addr ),
.mem_wdata(mem_wdata),
.mem_wstrb(mem_wstrb),
.mem_instr(mem_instr),
.mem_ready(mem_ready),
.mem_rdata(mem_rdata),
.pcpi_valid(pcpi_valid),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_wr ),
.pcpi_rd (pcpi_rd ),
.pcpi_wait (pcpi_wait ),
.pcpi_ready(pcpi_ready),
.irq(irq),
.eoi(eoi),
`ifdef RISCV_FORMAL
.rvfi_valid (rvfi_valid ),
.rvfi_order (rvfi_order ),
.rvfi_insn (rvfi_insn ),
.rvfi_trap (rvfi_trap ),
.rvfi_halt (rvfi_halt ),
.rvfi_intr (rvfi_intr ),
.rvfi_rs1_addr (rvfi_rs1_addr ),
.rvfi_rs2_addr (rvfi_rs2_addr ),
.rvfi_rs1_rdata(rvfi_rs1_rdata),
.rvfi_rs2_rdata(rvfi_rs2_rdata),
.rvfi_rd_addr (rvfi_rd_addr ),
.rvfi_rd_wdata (rvfi_rd_wdata ),
.rvfi_pc_rdata (rvfi_pc_rdata ),
.rvfi_pc_wdata (rvfi_pc_wdata ),
.rvfi_mem_addr (rvfi_mem_addr ),
.rvfi_mem_rmask(rvfi_mem_rmask),
.rvfi_mem_wmask(rvfi_mem_wmask),
.rvfi_mem_rdata(rvfi_mem_rdata),
.rvfi_mem_wdata(rvfi_mem_wdata),
`endif
.trace_valid(trace_valid),
.trace_data (trace_data)
);
localparam IDLE = 2'b00;
localparam WBSTART = 2'b01;
localparam WBEND = 2'b10;
reg [1:0] state;
wire we;
assign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]);
always @(posedge wb_clk_i) begin
if (wb_rst_i) begin
wbm_adr_o <= 0;
wbm_dat_o <= 0;
wbm_we_o <= 0;
wbm_sel_o <= 0;
wbm_stb_o <= 0;
wbm_cyc_o <= 0;
state <= IDLE;
end else begin
case (state)
IDLE: begin
if (mem_valid) begin
wbm_adr_o <= mem_addr;
wbm_dat_o <= mem_wdata;
wbm_we_o <= we;
wbm_sel_o <= mem_wstrb;
wbm_stb_o <= 1'b1;
wbm_cyc_o <= 1'b1;
state <= WBSTART;
end else begin
mem_ready <= 1'b0;
wbm_stb_o <= 1'b0;
wbm_cyc_o <= 1'b0;
wbm_we_o <= 1'b0;
end
end
WBSTART:begin
if (wbm_ack_i) begin
mem_rdata <= wbm_dat_i;
mem_ready <= 1'b1;
state <= WBEND;
wbm_stb_o <= 1'b0;
wbm_cyc_o <= 1'b0;
wbm_we_o <= 1'b0;
end
end
WBEND: begin
mem_ready <= 1'b0;
state <= IDLE;
end
default:
state <= IDLE;
endcase
end
end
endmodule
|
/* Copyright (c) 2013 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* Wishbone SLAVE Adapter for the Memory Access Module (MAM)
*
* This adapter is made to be inserted in front of a Wishbone SLAVE memory.
*
* --------------- WB Slave ------------------ WB Slave ----------
* | WB INTERCON | ========== | mam_wb_adapter | ========== | Memory |
* --------------- wb_in ------------------ wb_out ----------
* ||
* wb_mam || WB Master
* ||
* -------
* | mam |
* -------
*
* If the global define OPTIMSOC_DEBUG_ENABLE_MAM is not set the adapter is
* transparent (e.g. reduced to wires).
*
* Author(s):
* Philipp Wagner <[email protected]>
*/
module mam_wb_adapter(
wb_mam_ack_i, wb_mam_rty_i, wb_mam_err_i, wb_mam_dat_i, wb_mam_bte_o,
wb_mam_adr_o, wb_mam_cyc_o, wb_mam_dat_o, wb_mam_sel_o, wb_mam_stb_o,
wb_mam_we_o, wb_mam_cab_o, wb_mam_cti_o,
/*AUTOARG*/
// Outputs
wb_in_ack_o, wb_in_err_o, wb_in_rty_o, wb_in_dat_o, wb_out_adr_i,
wb_out_bte_i, wb_out_cti_i, wb_out_cyc_i, wb_out_dat_i,
wb_out_sel_i, wb_out_stb_i, wb_out_we_i, wb_out_clk_i,
wb_out_rst_i,
// Inputs
wb_in_adr_i, wb_in_bte_i, wb_in_cti_i, wb_in_cyc_i, wb_in_dat_i,
wb_in_sel_i, wb_in_stb_i, wb_in_we_i, wb_in_clk_i, wb_in_rst_i,
wb_out_ack_o, wb_out_err_o, wb_out_rty_o, wb_out_dat_o
);
import optimsoc_functions::*;
// address width
parameter AW = 32;
// data width
parameter DW = 32;
parameter USE_DEBUG = 1;
// byte select width
localparam SW = (DW == 32) ? 4 :
(DW == 16) ? 2 :
(DW == 8) ? 1 : 'hx;
/*
* +--------------+--------------+
* | word address | byte in word |
* +--------------+--------------+
* WORD_AW BYTE_AW
* +----- AW -----+
*/
localparam BYTE_AW = SW >> 1;
localparam WORD_AW = AW - BYTE_AW;
// Wishbone SLAVE interface: input side (to the CPU etc.)
input [AW-1:0] wb_in_adr_i;
input [1:0] wb_in_bte_i;
input [2:0] wb_in_cti_i;
input wb_in_cyc_i;
input [DW-1:0] wb_in_dat_i;
input [SW-1:0] wb_in_sel_i;
input wb_in_stb_i;
input wb_in_we_i;
output wb_in_ack_o;
output wb_in_err_o;
output wb_in_rty_o;
output [DW-1:0] wb_in_dat_o;
input wb_in_clk_i;
input wb_in_rst_i;
// Wishbone SLAVE interface: output side (to the memory)
output [AW-1:0] wb_out_adr_i;
output [1:0] wb_out_bte_i;
output [2:0] wb_out_cti_i;
output wb_out_cyc_i;
output [DW-1:0] wb_out_dat_i;
output [SW-1:0] wb_out_sel_i;
output wb_out_stb_i;
output wb_out_we_i;
input wb_out_ack_o;
input wb_out_err_o;
input wb_out_rty_o;
input [DW-1:0] wb_out_dat_o;
output wb_out_clk_i;
output wb_out_rst_i;
// we use a common clock for all this module!
assign wb_out_clk_i = wb_in_clk_i;
assign wb_out_rst_i = wb_in_rst_i;
// MAM Wishbone MASTER interface (incoming)
input [AW-1:0] wb_mam_adr_o;
input wb_mam_cyc_o;
input [DW-1:0] wb_mam_dat_o;
input [SW-1:0] wb_mam_sel_o;
input wb_mam_stb_o;
input wb_mam_we_o;
input wb_mam_cab_o;
input [2:0] wb_mam_cti_o;
input [1:0] wb_mam_bte_o;
output wb_mam_ack_i;
output wb_mam_rty_i;
output wb_mam_err_i;
output [DW-1:0] wb_mam_dat_i;
if (USE_DEBUG == 1) begin
localparam STATE_ARB_WIDTH = 2;
localparam STATE_ARB_IDLE = 0;
localparam STATE_ARB_ACCESS_MAM = 1;
localparam STATE_ARB_ACCESS_CPU = 2;
reg [STATE_ARB_WIDTH-1:0] fsm_arb_state;
reg [STATE_ARB_WIDTH-1:0] fsm_arb_state_next;
reg grant_access_cpu;
reg grant_access_mam;
reg access_cpu;
// arbiter FSM: MAM has higher priority than CPU
always @(posedge wb_in_clk_i) begin
if (wb_in_rst_i) begin
fsm_arb_state <= STATE_ARB_IDLE;
end else begin
fsm_arb_state <= fsm_arb_state_next;
if (grant_access_cpu) begin
access_cpu <= 1'b1;
end else if (grant_access_mam) begin
access_cpu <= 1'b0;
end
end
end
always @(*) begin
grant_access_cpu = 1'b0;
grant_access_mam = 1'b0;
fsm_arb_state_next = STATE_ARB_IDLE;
case (fsm_arb_state)
STATE_ARB_IDLE: begin
if (wb_mam_cyc_o == 1'b1) begin
fsm_arb_state_next = STATE_ARB_ACCESS_MAM;
end else if (wb_in_cyc_i == 1'b1) begin
fsm_arb_state_next = STATE_ARB_ACCESS_CPU;
end else begin
fsm_arb_state_next = STATE_ARB_IDLE;
end
end
STATE_ARB_ACCESS_MAM: begin
grant_access_mam = 1'b1;
if (wb_mam_cyc_o == 1'b1) begin
fsm_arb_state_next = STATE_ARB_ACCESS_MAM;
end else begin
fsm_arb_state_next = STATE_ARB_IDLE;
end
end
//CPU may finish cycle before switching to MAM. May need changes if instant MAM access required
STATE_ARB_ACCESS_CPU: begin
grant_access_cpu = 1'b1;
if (wb_in_cyc_i == 1'b1) begin
fsm_arb_state_next = STATE_ARB_ACCESS_CPU;
end else if (wb_mam_cyc_o == 1'b1) begin
fsm_arb_state_next = STATE_ARB_ACCESS_MAM;
end else begin
fsm_arb_state_next = STATE_ARB_IDLE;
end
end
endcase
end
// MUX of signals TO the memory
assign wb_out_adr_i = access_cpu ? wb_in_adr_i : wb_mam_adr_o;
assign wb_out_bte_i = access_cpu ? wb_in_bte_i : wb_mam_bte_o;
assign wb_out_cti_i = access_cpu ? wb_in_cti_i : wb_mam_cti_o;
assign wb_out_cyc_i = access_cpu ? wb_in_cyc_i : wb_mam_cyc_o;
assign wb_out_dat_i = access_cpu ? wb_in_dat_i : wb_mam_dat_o;
assign wb_out_sel_i = access_cpu ? wb_in_sel_i : wb_mam_sel_o;
assign wb_out_stb_i = access_cpu ? wb_in_stb_i : wb_mam_stb_o;
assign wb_out_we_i = access_cpu ? wb_in_we_i : wb_mam_we_o;
// MUX of signals FROM the memory
assign wb_in_ack_o = access_cpu ? wb_out_ack_o : 1'b0;
assign wb_in_err_o = access_cpu ? wb_out_err_o : 1'b0;
assign wb_in_rty_o = access_cpu ? wb_out_rty_o : 1'b0;
assign wb_in_dat_o = access_cpu ? wb_out_dat_o : {DW{1'b0}};
assign wb_mam_ack_i = ~access_cpu ? wb_out_ack_o : 1'b0;
assign wb_mam_err_i = ~access_cpu ? wb_out_err_o : 1'b0;
assign wb_mam_rty_i = ~access_cpu ? wb_out_rty_o : 1'b0;
assign wb_mam_dat_i = ~access_cpu ? wb_out_dat_o : {DW{1'b0}};
end else begin // USE_DEBUG == 0
assign wb_out_adr_i = wb_in_adr_i;
assign wb_out_bte_i = wb_in_bte_i;
assign wb_out_cti_i = wb_in_cti_i;
assign wb_out_cyc_i = wb_in_cyc_i;
assign wb_out_dat_i = wb_in_dat_i;
assign wb_out_sel_i = wb_in_sel_i;
assign wb_out_stb_i = wb_in_stb_i;
assign wb_out_we_i = wb_in_we_i;
assign wb_in_ack_o = wb_out_ack_o;
assign wb_in_err_o = wb_out_err_o;
assign wb_in_rty_o = wb_out_rty_o;
assign wb_in_dat_o = wb_out_dat_o;
end // if(USE_DEBUG == 1)
endmodule
|
module ram_wb_01
#(//Wishbone parameters
parameter dw = 32,
parameter aw = 32,
// Memory parameters
parameter memory_file = "",
parameter mem_size_bytes = 32'h0000_5000, // 20KBytes
parameter mem_adr_width = 15) //(log2(mem_size_bytes));
(input wb_clk_i,
input wb_rst_i,
input [aw-1:0] wb_adr_i,
input [dw-1:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input [1:0] wb_bte_i,
input [2:0] wb_cti_i,
input wb_cyc_i,
input wb_stb_i,
output wb_ack_o,
output wb_err_o,
output wb_rty_o,
output [dw-1:0] wb_dat_o);
localparam bytes_per_dw = (dw/8);
localparam adr_width_for_num_word_bytes = 2; //(log2(bytes_per_dw))
localparam mem_words = (mem_size_bytes/bytes_per_dw);
// synthesis attribute ram_style of mem is block
reg [dw-1:0] mem [ 0 : mem_words-1 ] /* verilator public */ /* synthesis ram_style = no_rw_check */;
// Register to address internal memory array
reg [(mem_adr_width-adr_width_for_num_word_bytes)-1:0] addr_reg;
// Register to indicate if the cycle is a Wishbone B3-registered feedback
// type access
reg wb_b3_trans;
// Register to use for counting the addresses when doing burst accesses
reg [(mem_adr_width-adr_width_for_num_word_bytes)-1:0] burst_adr_r;
// Combinatorial next address calculation for bust accesses
reg [(mem_adr_width-adr_width_for_num_word_bytes)-1:0] adr;
// Logic to detect if there's a burst access going on
wire wb_b3_trans_start = ((wb_cti_i == 3'b001)|(wb_cti_i == 3'b010)) &
wb_stb_i & !wb_b3_trans & wb_cyc_i;
wire wb_b3_trans_stop = ((wb_cti_i == 3'b111) &
wb_stb_i & wb_b3_trans & wb_ack_o) | wb_err_o;
always @(posedge wb_clk_i)
if (wb_rst_i)
wb_b3_trans <= 0;
else if (wb_b3_trans_start)
wb_b3_trans <= 1;
else if (wb_b3_trans_stop)
wb_b3_trans <= 0;
// Register it locally
reg [1:0] wb_bte_i_r;
reg [2:0] wb_cti_i_r;
always @(posedge wb_clk_i) begin
wb_bte_i_r <= wb_bte_i;
wb_cti_i_r <= wb_cti_i;
end
// Burst address generation logic
always @(wb_ack_o or wb_b3_trans or wb_b3_trans_start
or wb_bte_i_r or wb_cti_i_r or wb_adr_i or burst_adr_r)
if (wb_b3_trans_start)
// Kick off adr, this assumes 4-byte words when getting
// address off incoming Wishbone bus address!
// So if dw is no longer 4 bytes, change this!
adr = wb_adr_i[mem_adr_width-1:2];
else if ((wb_cti_i_r == 3'b010) & wb_ack_o & wb_b3_trans) // Incrementing burst
case(wb_bte_i_r)
2'b00 : adr = burst_adr_r + 1; // Linear burst
2'b01 : begin
adr[1:0] = burst_adr_r[1:0] + 1; // 4-beat wrap burst
adr[(mem_adr_width-adr_width_for_num_word_bytes)-1:2] = burst_adr_r[(mem_adr_width-adr_width_for_num_word_bytes)-1:2];
end
2'b10 : begin
// 8-beat wrap burst
adr[2:0] = burst_adr_r[2:0] + 1;
adr[(mem_adr_width-adr_width_for_num_word_bytes)-1:3] = burst_adr_r[(mem_adr_width-adr_width_for_num_word_bytes)-1:3];
end
2'b11 : begin
// 16-beat wrap burst
adr[3:0] = burst_adr_r[3:0] + 1;
adr[(mem_adr_width-adr_width_for_num_word_bytes)-1:4] = burst_adr_r[(mem_adr_width-adr_width_for_num_word_bytes)-1:4];
end
default: adr = wb_adr_i[mem_adr_width-1:2];
endcase
else
adr = wb_adr_i[mem_adr_width-1:2];
wire using_burst_adr = wb_b3_trans;
wire burst_access_wrong_wb_adr = (using_burst_adr &
(burst_adr_r != wb_adr_i[mem_adr_width-1:2]));
// Address registering logic only for read
always@(posedge wb_clk_i)
if(wb_rst_i)
burst_adr_r <= 0;
else if (using_burst_adr)
burst_adr_r <= adr;
else if (wb_cyc_i & wb_stb_i)
burst_adr_r <= wb_adr_i[mem_adr_width-1:2];
assign wb_rty_o = 0;
// mux for data to ram, RMW on part sel != 4'hf
wire [31:0] wr_data;
assign wr_data[31:24] = wb_sel_i[3] ? wb_dat_i[31:24] : wb_dat_o[31:24];
assign wr_data[23:16] = wb_sel_i[2] ? wb_dat_i[23:16] : wb_dat_o[23:16];
assign wr_data[15: 8] = wb_sel_i[1] ? wb_dat_i[15: 8] : wb_dat_o[15: 8];
assign wr_data[ 7: 0] = wb_sel_i[0] ? wb_dat_i[ 7: 0] : wb_dat_o[ 7: 0];
wire ram_we = wb_we_i & wb_ack_o;
assign wb_dat_o = mem[addr_reg];
// Write logic
always @ (posedge wb_clk_i)
if (ram_we)
mem[adr] <= wr_data;
// Read logic
always @ (posedge wb_clk_i)
addr_reg <= adr;
// Ack Logic
reg wb_ack_o_r;
assign wb_ack_o = wb_ack_o_r & wb_stb_i & !burst_access_wrong_wb_adr;
//Handle wb_ack
always @ (posedge wb_clk_i)
if (wb_rst_i)
wb_ack_o_r <= 1'b0;
else if (wb_cyc_i) begin // We have bus
if (wb_cti_i == 3'b000) // Classic cycle acks
wb_ack_o_r <= wb_stb_i ^ wb_ack_o_r;
else if ((wb_cti_i == 3'b001) | (wb_cti_i == 3'b010)) // Increment/constant address bursts
wb_ack_o_r <= wb_stb_i;
else if (wb_cti_i == 3'b111) // End of cycle
wb_ack_o_r <= wb_stb_i & !wb_ack_o_r;
end else
wb_ack_o_r <= 0;
//
// Error signal generation
//
// OR in other errors here...
assign wb_err_o = wb_ack_o_r & wb_stb_i &
(burst_access_wrong_wb_adr);
//
// Access functions
//
/* Memory initialisation.
If not Verilator model, always do load, otherwise only load when called
from SystemC testbench.
*/
// Memory initialzation routine restored from old ram_wb component
integer k;
initial
begin
// synthesis translate_off
for(k = 0; k < (1 << mem_words); k = k + 1)
begin
mem[k] = 0;
end
// synthesis translate_on
$readmemh(memory_file, mem);
end
// synthesis translate_off
`ifdef verilator
// Function to access RAM (for use by Verilator).
function [31:0] get_mem32;
// verilator public
input [aw-1:0] addr;
get_mem32 = mem[addr];
endfunction // get_mem32
// Function to access RAM (for use by Verilator).
function [7:0] get_mem8;
// verilator public
input [aw-1:0] addr;
reg [31:0] temp_word;
begin
temp_word = mem[{addr[aw-1:2],2'd0}];
// Big endian mapping.
get_mem8 = (addr[1:0]==2'b00) ? temp_word[31:24] :
(addr[1:0]==2'b01) ? temp_word[23:16] :
(addr[1:0]==2'b10) ? temp_word[15:8] : temp_word[7:0];
end
endfunction // get_mem8
// Function to write RAM (for use by Verilator).
function set_mem32;
// verilator public
input [aw-1:0] addr;
input [dw-1:0] data;
begin
mem[addr] = data;
set_mem32 = data; // For avoiding ModelSim warning
end
endfunction // set_mem32
`endif // !`ifdef verilator
//synthesis translate_on
endmodule // ram_wb
|
module ram_wb_02
#(//Wishbone parameters
parameter dw = 32,
parameter aw = 32,
// Memory parameters
parameter memory_file = "",
parameter mem_size_bytes = 32'h0000_5000, // 20KBytes
parameter mem_adr_width = 15) //(log2(mem_size_bytes));
(input wb_clk_i,
input wb_rst_i,
input [aw-1:0] wb_adr_i,
input [dw-1:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input [1:0] wb_bte_i,
input [2:0] wb_cti_i,
input wb_cyc_i,
input wb_stb_i,
output wb_ack_o,
output wb_err_o,
output wb_rty_o,
output [dw-1:0] wb_dat_o);
localparam bytes_per_dw = (dw/8);
localparam adr_width_for_num_word_bytes = 2; //(log2(bytes_per_dw))
localparam mem_words = (mem_size_bytes/bytes_per_dw);
// synthesis attribute ram_style of mem is block
reg [dw-1:0] mem [ 0 : mem_words-1 ] /* verilator public */ /* synthesis ram_style = no_rw_check */;
// Register to address internal memory array
reg [(mem_adr_width-adr_width_for_num_word_bytes)-1:0] addr_reg;
// Register to indicate if the cycle is a Wishbone B3-registered feedback
// type access
reg wb_b3_trans;
// Register to use for counting the addresses when doing burst accesses
reg [(mem_adr_width-adr_width_for_num_word_bytes)-1:0] burst_adr_r;
// Combinatorial next address calculation for bust accesses
reg [(mem_adr_width-adr_width_for_num_word_bytes)-1:0] adr;
// Logic to detect if there's a burst access going on
wire wb_b3_trans_start = ((wb_cti_i == 3'b001)|(wb_cti_i == 3'b010)) &
wb_stb_i & !wb_b3_trans & wb_cyc_i;
wire wb_b3_trans_stop = ((wb_cti_i == 3'b111) &
wb_stb_i & wb_b3_trans & wb_ack_o) | wb_err_o;
always @(posedge wb_clk_i)
if (wb_rst_i)
wb_b3_trans <= 0;
else if (wb_b3_trans_start)
wb_b3_trans <= 1;
else if (wb_b3_trans_stop)
wb_b3_trans <= 0;
// Register it locally
reg [1:0] wb_bte_i_r;
reg [2:0] wb_cti_i_r;
always @(posedge wb_clk_i) begin
wb_bte_i_r <= wb_bte_i;
wb_cti_i_r <= wb_cti_i;
end
// Burst address generation logic
always @(wb_ack_o or wb_b3_trans or wb_b3_trans_start
or wb_bte_i_r or wb_cti_i_r or wb_adr_i or burst_adr_r)
if (wb_b3_trans_start)
// Kick off adr, this assumes 4-byte words when getting
// address off incoming Wishbone bus address!
// So if dw is no longer 4 bytes, change this!
adr = wb_adr_i[mem_adr_width-1:2];
else if ((wb_cti_i_r == 3'b010) & wb_ack_o & wb_b3_trans) // Incrementing burst
case(wb_bte_i_r)
2'b00 : adr = burst_adr_r + 1; // Linear burst
2'b01 : begin
adr[1:0] = burst_adr_r[1:0] + 1; // 4-beat wrap burst
adr[(mem_adr_width-adr_width_for_num_word_bytes)-1:2] = burst_adr_r[(mem_adr_width-adr_width_for_num_word_bytes)-1:2];
end
2'b10 : begin
// 8-beat wrap burst
adr[2:0] = burst_adr_r[2:0] + 1;
adr[(mem_adr_width-adr_width_for_num_word_bytes)-1:3] = burst_adr_r[(mem_adr_width-adr_width_for_num_word_bytes)-1:3];
end
2'b11 : begin
// 16-beat wrap burst
adr[3:0] = burst_adr_r[3:0] + 1;
adr[(mem_adr_width-adr_width_for_num_word_bytes)-1:4] = burst_adr_r[(mem_adr_width-adr_width_for_num_word_bytes)-1:4];
end
default: adr = wb_adr_i[mem_adr_width-1:2];
endcase
else
adr = wb_adr_i[mem_adr_width-1:2];
wire using_burst_adr = wb_b3_trans;
wire burst_access_wrong_wb_adr = (using_burst_adr &
(burst_adr_r != wb_adr_i[mem_adr_width-1:2]));
// Address registering logic only for read
always@(posedge wb_clk_i)
if(wb_rst_i)
burst_adr_r <= 0;
else if (using_burst_adr)
burst_adr_r <= adr;
else if (wb_cyc_i & wb_stb_i)
burst_adr_r <= wb_adr_i[mem_adr_width-1:2];
assign wb_rty_o = 0;
// mux for data to ram, RMW on part sel != 4'hf
wire [31:0] wr_data;
assign wr_data[31:24] = wb_sel_i[3] ? wb_dat_i[31:24] : wb_dat_o[31:24];
assign wr_data[23:16] = wb_sel_i[2] ? wb_dat_i[23:16] : wb_dat_o[23:16];
assign wr_data[15: 8] = wb_sel_i[1] ? wb_dat_i[15: 8] : wb_dat_o[15: 8];
assign wr_data[ 7: 0] = wb_sel_i[0] ? wb_dat_i[ 7: 0] : wb_dat_o[ 7: 0];
wire ram_we = wb_we_i & wb_ack_o;
assign wb_dat_o = mem[addr_reg];
// Write logic
always @ (posedge wb_clk_i)
if (ram_we)
mem[adr] <= wr_data;
// Read logic
always @ (posedge wb_clk_i)
addr_reg <= adr;
// Ack Logic
reg wb_ack_o_r;
assign wb_ack_o = wb_ack_o_r & wb_stb_i & !burst_access_wrong_wb_adr;
//Handle wb_ack
always @ (posedge wb_clk_i)
if (wb_rst_i)
wb_ack_o_r <= 1'b0;
else if (wb_cyc_i) begin // We have bus
if (wb_cti_i == 3'b000) // Classic cycle acks
wb_ack_o_r <= wb_stb_i ^ wb_ack_o_r;
else if ((wb_cti_i == 3'b001) | (wb_cti_i == 3'b010)) // Increment/constant address bursts
wb_ack_o_r <= wb_stb_i;
else if (wb_cti_i == 3'b111) // End of cycle
wb_ack_o_r <= wb_stb_i & !wb_ack_o_r;
end else
wb_ack_o_r <= 0;
//
// Error signal generation
//
// OR in other errors here...
assign wb_err_o = wb_ack_o_r & wb_stb_i &
(burst_access_wrong_wb_adr);
//
// Access functions
//
/* Memory initialisation.
If not Verilator model, always do load, otherwise only load when called
from SystemC testbench.
*/
// Memory initialzation routine restored from old ram_wb component
integer k;
initial
begin
// synthesis translate_off
for(k = 0; k < (1 << mem_words); k = k + 1)
begin
mem[k] = 0;
end
// synthesis translate_on
$readmemh(memory_file, mem);
end
// synthesis translate_off
`ifdef verilator
// Function to access RAM (for use by Verilator).
function [31:0] get_mem32;
// verilator public
input [aw-1:0] addr;
get_mem32 = mem[addr];
endfunction // get_mem32
// Function to access RAM (for use by Verilator).
function [7:0] get_mem8;
// verilator public
input [aw-1:0] addr;
reg [31:0] temp_word;
begin
temp_word = mem[{addr[aw-1:2],2'd0}];
// Big endian mapping.
get_mem8 = (addr[1:0]==2'b00) ? temp_word[31:24] :
(addr[1:0]==2'b01) ? temp_word[23:16] :
(addr[1:0]==2'b10) ? temp_word[15:8] : temp_word[7:0];
end
endfunction // get_mem8
// Function to write RAM (for use by Verilator).
function set_mem32;
// verilator public
input [aw-1:0] addr;
input [dw-1:0] data;
begin
mem[addr] = data;
set_mem32 = data; // For avoiding ModelSim warning
end
endfunction // set_mem32
`endif // !`ifdef verilator
//synthesis translate_on
endmodule // ram_wb
|
module ram_wb_03
#(//Wishbone parameters
parameter dw = 32,
parameter aw = 32,
// Memory parameters
parameter memory_file = "",
parameter mem_size_bytes = 32'h0000_5000, // 20KBytes
parameter mem_adr_width = 15) //(log2(mem_size_bytes));
(input wb_clk_i,
input wb_rst_i,
input [aw-1:0] wb_adr_i,
input [dw-1:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input [1:0] wb_bte_i,
input [2:0] wb_cti_i,
input wb_cyc_i,
input wb_stb_i,
output wb_ack_o,
output wb_err_o,
output wb_rty_o,
output [dw-1:0] wb_dat_o);
localparam bytes_per_dw = (dw/8);
localparam adr_width_for_num_word_bytes = 2; //(log2(bytes_per_dw))
localparam mem_words = (mem_size_bytes/bytes_per_dw);
// synthesis attribute ram_style of mem is block
reg [dw-1:0] mem [ 0 : mem_words-1 ] /* verilator public */ /* synthesis ram_style = no_rw_check */;
// Register to address internal memory array
reg [(mem_adr_width-adr_width_for_num_word_bytes)-1:0] addr_reg;
// Register to indicate if the cycle is a Wishbone B3-registered feedback
// type access
reg wb_b3_trans;
// Register to use for counting the addresses when doing burst accesses
reg [(mem_adr_width-adr_width_for_num_word_bytes)-1:0] burst_adr_r;
// Combinatorial next address calculation for bust accesses
reg [(mem_adr_width-adr_width_for_num_word_bytes)-1:0] adr;
// Logic to detect if there's a burst access going on
wire wb_b3_trans_start = ((wb_cti_i == 3'b001)|(wb_cti_i == 3'b010)) &
wb_stb_i & !wb_b3_trans & wb_cyc_i;
wire wb_b3_trans_stop = ((wb_cti_i == 3'b111) &
wb_stb_i & wb_b3_trans & wb_ack_o) | wb_err_o;
always @(posedge wb_clk_i)
if (wb_rst_i)
wb_b3_trans <= 0;
else if (wb_b3_trans_start)
wb_b3_trans <= 1;
else if (wb_b3_trans_stop)
wb_b3_trans <= 0;
// Register it locally
reg [1:0] wb_bte_i_r;
reg [2:0] wb_cti_i_r;
always @(posedge wb_clk_i) begin
wb_bte_i_r <= wb_bte_i;
wb_cti_i_r <= wb_cti_i;
end
// Burst address generation logic
always @(wb_ack_o or wb_b3_trans or wb_b3_trans_start
or wb_bte_i_r or wb_cti_i_r or wb_adr_i or burst_adr_r)
if (wb_b3_trans_start)
// Kick off adr, this assumes 4-byte words when getting
// address off incoming Wishbone bus address!
// So if dw is no longer 4 bytes, change this!
adr = wb_adr_i[mem_adr_width-1:2];
else if ((wb_cti_i_r == 3'b010) & wb_ack_o & wb_b3_trans) // Incrementing burst
case(wb_bte_i_r)
2'b00 : adr = burst_adr_r + 1; // Linear burst
2'b01 : begin
adr[1:0] = burst_adr_r[1:0] + 1; // 4-beat wrap burst
adr[(mem_adr_width-adr_width_for_num_word_bytes)-1:2] = burst_adr_r[(mem_adr_width-adr_width_for_num_word_bytes)-1:2];
end
2'b10 : begin
// 8-beat wrap burst
adr[2:0] = burst_adr_r[2:0] + 1;
adr[(mem_adr_width-adr_width_for_num_word_bytes)-1:3] = burst_adr_r[(mem_adr_width-adr_width_for_num_word_bytes)-1:3];
end
2'b11 : begin
// 16-beat wrap burst
adr[3:0] = burst_adr_r[3:0] + 1;
adr[(mem_adr_width-adr_width_for_num_word_bytes)-1:4] = burst_adr_r[(mem_adr_width-adr_width_for_num_word_bytes)-1:4];
end
default: adr = wb_adr_i[mem_adr_width-1:2];
endcase
else
adr = wb_adr_i[mem_adr_width-1:2];
wire using_burst_adr = wb_b3_trans;
wire burst_access_wrong_wb_adr = (using_burst_adr &
(burst_adr_r != wb_adr_i[mem_adr_width-1:2]));
// Address registering logic only for read
always@(posedge wb_clk_i)
if(wb_rst_i)
burst_adr_r <= 0;
else if (using_burst_adr)
burst_adr_r <= adr;
else if (wb_cyc_i & wb_stb_i)
burst_adr_r <= wb_adr_i[mem_adr_width-1:2];
assign wb_rty_o = 0;
// mux for data to ram, RMW on part sel != 4'hf
wire [31:0] wr_data;
assign wr_data[31:24] = wb_sel_i[3] ? wb_dat_i[31:24] : wb_dat_o[31:24];
assign wr_data[23:16] = wb_sel_i[2] ? wb_dat_i[23:16] : wb_dat_o[23:16];
assign wr_data[15: 8] = wb_sel_i[1] ? wb_dat_i[15: 8] : wb_dat_o[15: 8];
assign wr_data[ 7: 0] = wb_sel_i[0] ? wb_dat_i[ 7: 0] : wb_dat_o[ 7: 0];
wire ram_we = wb_we_i & wb_ack_o;
assign wb_dat_o = mem[addr_reg];
// Write logic
always @ (posedge wb_clk_i)
if (ram_we)
mem[adr] <= wr_data;
// Read logic
always @ (posedge wb_clk_i)
addr_reg <= adr;
// Ack Logic
reg wb_ack_o_r;
assign wb_ack_o = wb_ack_o_r & wb_stb_i & !burst_access_wrong_wb_adr;
//Handle wb_ack
always @ (posedge wb_clk_i)
if (wb_rst_i)
wb_ack_o_r <= 1'b0;
else if (wb_cyc_i) begin // We have bus
if (wb_cti_i == 3'b000) // Classic cycle acks
wb_ack_o_r <= wb_stb_i ^ wb_ack_o_r;
else if ((wb_cti_i == 3'b001) | (wb_cti_i == 3'b010)) // Increment/constant address bursts
wb_ack_o_r <= wb_stb_i;
else if (wb_cti_i == 3'b111) // End of cycle
wb_ack_o_r <= wb_stb_i & !wb_ack_o_r;
end else
wb_ack_o_r <= 0;
//
// Error signal generation
//
// OR in other errors here...
assign wb_err_o = wb_ack_o_r & wb_stb_i &
(burst_access_wrong_wb_adr);
//
// Access functions
//
/* Memory initialisation.
If not Verilator model, always do load, otherwise only load when called
from SystemC testbench.
*/
// Memory initialzation routine restored from old ram_wb component
integer k;
initial
begin
// synthesis translate_off
for(k = 0; k < (1 << mem_words); k = k + 1)
begin
mem[k] = 0;
end
// synthesis translate_on
$readmemh(memory_file, mem);
end
// synthesis translate_off
`ifdef verilator
// Function to access RAM (for use by Verilator).
function [31:0] get_mem32;
// verilator public
input [aw-1:0] addr;
get_mem32 = mem[addr];
endfunction // get_mem32
// Function to access RAM (for use by Verilator).
function [7:0] get_mem8;
// verilator public
input [aw-1:0] addr;
reg [31:0] temp_word;
begin
temp_word = mem[{addr[aw-1:2],2'd0}];
// Big endian mapping.
get_mem8 = (addr[1:0]==2'b00) ? temp_word[31:24] :
(addr[1:0]==2'b01) ? temp_word[23:16] :
(addr[1:0]==2'b10) ? temp_word[15:8] : temp_word[7:0];
end
endfunction // get_mem8
// Function to write RAM (for use by Verilator).
function set_mem32;
// verilator public
input [aw-1:0] addr;
input [dw-1:0] data;
begin
mem[addr] = data;
set_mem32 = data; // For avoiding ModelSim warning
end
endfunction // set_mem32
`endif // !`ifdef verilator
//synthesis translate_on
endmodule // ram_wb
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* Single Port RAM with Byte Select
*
* The width of the data and address bus can be configured using the DW and
* AW parameters. To support byte selects DW must be a multiple of 8.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
* Markus Goehrle <[email protected]>
* Philipp Wagner <[email protected]>
*/
module sram_sp(/*AUTOARG*/
// Outputs
dout,
// Inputs
clk, rst, ce, we, oe, waddr, din, sel
);
import optimsoc_functions::*;
parameter MEM_SIZE_BYTE = 'hx;
// address width
parameter AW = 32;
// data width (word size)
// Valid values: 32, 16 and 8
parameter DW = 32;
// type of the memory implementation
parameter MEM_IMPL_TYPE = "PLAIN";
// VMEM memory file to load in simulation
parameter MEM_FILE = "sram.vmem";
// byte select width (must be a power of two)
localparam SW = (DW == 32) ? 4 :
(DW == 16) ? 2 :
(DW == 8) ? 1 : 'hx;
// word address width
parameter WORD_AW = AW - (SW >> 1);
// ensure that parameters are set to allowed values
initial begin
if (DW % 8 != 0) begin
$display("sram_sp: the data port width (parameter DW) must be a multiple of 8");
$stop;
end
if ((1 << $clog2(SW)) != SW) begin
$display("sram_sp: the byte select width (paramter SW = DW/8) must be a power of two");
$stop;
end
end
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [WORD_AW-1:0] waddr; // word address
input [DW-1:0] din; // input data bus
input [SW-1:0] sel; // select bytes
output [DW-1:0] dout; // output data bus
// validate the memory address (check if it's inside the memory size bounds)
`ifdef OPTIMSOC_SRAM_VALIDATE_ADDRESS
logic [AW-1:0] addr;
assign addr = {waddr, (AW - WORD_AW)'{1'b0}};
always @(posedge clk) begin
if (addr > MEM_SIZE_BYTE) begin
$display("sram_sp: access to out-of-bounds memory address detected! Trying to access byte address 0x%x, MEM_SIZE_BYTE is %d bytes.",
addr, MEM_SIZE_BYTE);
$stop;
end
end
`endif
generate
if (MEM_IMPL_TYPE == "PLAIN") begin : gen_sram_sp_impl
sram_sp_impl_plain
#(.AW (AW),
.WORD_AW (WORD_AW),
.DW (DW),
.MEM_SIZE_BYTE (MEM_SIZE_BYTE),
.MEM_FILE (MEM_FILE))
u_impl(/*AUTOINST*/
// Outputs
.dout (dout[DW-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.ce (ce),
.we (we),
.oe (oe),
.waddr (waddr),
.din (din[DW-1:0]),
.sel (sel[SW-1:0]));
end else begin : gen_sram_sp_impl // block: gen_sram_sp_impl
// $display("Unsupported memory type: ", MEM_IMPL_TYPE);
// $stop;
end
endgenerate
endmodule
|
/* Copyright (c) 2012-2018 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* Single-Port memory implemented as plain registers
*
* The main use case for this memory implementation are simulations, but
* depending on the used Synthesis tool it might also be used in synthesized
* systems, if the right memory blocks for the target hardware are inferred.
*
* The code has been written to follow the inferrence guidelines from Vivado
* (UG 901, v2017.4) for Single-Port Block RAMs, and tested in Xilinx 7series
* devices to ensure blockram is inferred.
*
* When using Verilator, this memory can be initialized from MEM_FILE by calling
* the do_readmemh() function. It is also possible to read and write the memory
* using the get_mem() and set_mem() functions.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
* Stefan Wallentowitz <[email protected]>
* Philipp Wagner <[email protected]>
*/
module sram_sp_impl_plain(/*AUTOARG*/
// Outputs
dout,
// Inputs
clk, rst, ce, we, oe, waddr, din, sel
);
import optimsoc_functions::*;
// byte address width
parameter AW = 32;
// data width (must be multiple of 8 for byte selects to work)
parameter DW = 32;
localparam SW = (DW == 32) ? 4 :
(DW == 16) ? 2 :
(DW == 8) ? 1 : 'hx;
// word address width
parameter WORD_AW = AW - (SW >> 1);
// size of the memory in bytes
parameter MEM_SIZE_BYTE = 'hx;
localparam MEM_SIZE_WORDS = MEM_SIZE_BYTE / SW;
// VMEM file used to initialize the memory in simulation
parameter MEM_FILE = "ct.vmem";
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [WORD_AW-1:0] waddr; // word address
input [DW-1:0] din; // input data bus
input [SW-1:0] sel; // select bytes
output reg [DW-1:0] dout; // output data bus
(* ram_style = "block" *) reg [DW-1:0] mem [MEM_SIZE_WORDS-1:0] /*synthesis syn_ramstyle = "block_ram" */;
always_ff @ (posedge clk) begin
if (we) begin
// memory write
for (int i = 0; i < SW; i = i + 1) begin
if (sel[i] == 1'b1) begin
mem[waddr][i*8 +: 8] <= din[i*8 +: 8];
end
end
end
// memory read
dout <= mem[waddr];
end
`ifdef verilator
export "DPI-C" task do_readmemh;
task do_readmemh;
$readmemh(MEM_FILE, mem);
endtask
export "DPI-C" task do_readmemh_file;
task do_readmemh_file;
input string file;
$readmemh(file, mem);
endtask
// Function to access RAM (for use by Verilator).
function [DW-1:0] get_mem;
// verilator public
input [WORD_AW-1:0] waddr; // word address
get_mem = mem[waddr];
endfunction
// Function to write RAM (for use by Verilator).
function set_mem;
// verilator public
input [WORD_AW-1:0] waddr; // word address
input [DW-1:0] data; // data to write
mem[waddr] = data;
endfunction // set_mem
`else
initial
begin
$readmemh(MEM_FILE, mem);
end
`endif
endmodule
|
/* Copyright (c) 2010-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* RAM interface translation: Generic RAM interface to Wishbone
*
* See the README file in this directory for information about the common
* ports and parameters used in all memory modules.
*
* The original code has been taken from wb_ram_b3.v, part of the ORPSoCv2
* project on opencores.org.
*
* Author(s):
* Julius Baxter <[email protected]> (original author)
* Stefan Wallentowitz <[email protected]>
* Markus Goehrle <[email protected]>
*/
module wb2sram(/*AUTOARG*/
// Outputs
wb_ack_o, wb_err_o, wb_rty_o, wb_dat_o, sram_ce, sram_we,
sram_waddr, sram_din, sram_sel,
// Inputs
wb_adr_i, wb_bte_i, wb_cti_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i, wb_clk_i, wb_rst_i, sram_dout
);
import optimsoc_functions::*;
// Memory parameters
// data width (word size)
// Valid values: 32, 16 and 8
parameter DW = 32;
// address width
parameter AW = 32;
// byte select width
localparam SW = (DW == 32) ? 4 :
(DW == 16) ? 2 :
(DW == 8) ? 1 : 'hx;
/*
* +--------------+--------------+
* | word address | byte in word |
* +--------------+--------------+
* WORD_AW BYTE_AW
* +----- AW -----+
*/
localparam BYTE_AW = SW >> 1;
localparam WORD_AW = AW - BYTE_AW;
// wishbone ports
input [AW-1:0] wb_adr_i;
input [1:0] wb_bte_i;
input [2:0] wb_cti_i;
input wb_cyc_i;
input [DW-1:0] wb_dat_i;
input [SW-1:0] wb_sel_i;
input wb_stb_i;
input wb_we_i;
output wb_ack_o;
output wb_err_o;
output wb_rty_o;
output [DW-1:0] wb_dat_o;
input wb_clk_i;
input wb_rst_i;
wire [WORD_AW-1:0] word_addr_in;
assign word_addr_in = wb_adr_i[AW-1:BYTE_AW];
// generic RAM ports
output sram_ce;
output sram_we;
output [WORD_AW-1:0] sram_waddr;
output [DW-1:0] sram_din;
output [SW-1:0] sram_sel;
input [DW-1:0] sram_dout;
reg [WORD_AW-1:0] word_addr_reg;
reg [WORD_AW-1:0] word_addr;
// Register to indicate if the cycle is a Wishbone B3-registered feedback
// type access
reg wb_b3_trans;
wire wb_b3_trans_start, wb_b3_trans_stop;
// Register to use for counting the addresses when doing burst accesses
reg [WORD_AW-1:0] burst_adr_counter;
reg [2:0] wb_cti_i_r;
reg [1:0] wb_bte_i_r;
wire using_burst_adr;
wire burst_access_wrong_wb_adr;
// assignments from wb to memory
assign sram_ce = 1'b1;
assign sram_we = wb_we_i & wb_ack_o;
assign sram_waddr = (wb_we_i) ? word_addr_reg : word_addr;
assign sram_din = wb_dat_i;
assign sram_sel = wb_sel_i;
assign wb_dat_o = sram_dout;
// Logic to detect if there's a burst access going on
assign wb_b3_trans_start = ((wb_cti_i == 3'b001)|(wb_cti_i == 3'b010)) &
wb_stb_i & !wb_b3_trans;
assign wb_b3_trans_stop = (wb_cti_i == 3'b111) &
wb_stb_i & wb_b3_trans & wb_ack_o;
always @(posedge wb_clk_i) begin
if (wb_rst_i) begin
wb_b3_trans <= 0;
end else if (wb_b3_trans_start) begin
wb_b3_trans <= 1;
end else if (wb_b3_trans_stop) begin
wb_b3_trans <= 0;
end
end
// Burst address generation logic
always @(*) begin
if (wb_rst_i) begin
burst_adr_counter = 0;
end else begin
burst_adr_counter = word_addr_reg;
if (wb_b3_trans_start) begin
burst_adr_counter = word_addr_in;
end else if ((wb_cti_i_r == 3'b010) & wb_ack_o & wb_b3_trans) begin
// Incrementing burst
if (wb_bte_i_r == 2'b00) begin // Linear burst
burst_adr_counter = word_addr_reg + 1;
end
if (wb_bte_i_r == 2'b01) begin // 4-beat wrap burst
burst_adr_counter[1:0] = word_addr_reg[1:0] + 1;
end
if (wb_bte_i_r == 2'b10) begin // 8-beat wrap burst
burst_adr_counter[2:0] = word_addr_reg[2:0] + 1;
end
if (wb_bte_i_r == 2'b11) begin // 16-beat wrap burst
burst_adr_counter[3:0] = word_addr_reg[3:0] + 1;
end
end else if (!wb_ack_o & wb_b3_trans) begin
burst_adr_counter = word_addr_reg;
end
end
end
// Register it locally
always @(posedge wb_clk_i) begin
wb_bte_i_r <= wb_bte_i;
end
always @(posedge wb_clk_i) begin
wb_cti_i_r <= wb_cti_i;
end
assign using_burst_adr = wb_b3_trans;
assign burst_access_wrong_wb_adr = (using_burst_adr & (word_addr_reg != word_addr_in));
// Address logic
always @(*) begin
if (using_burst_adr) begin
word_addr = burst_adr_counter;
end else if (wb_cyc_i & wb_stb_i) begin
word_addr = word_addr_in;
end else begin
word_addr = word_addr_reg;
end
end
// Address registering logic
always @(posedge wb_clk_i) begin
if (wb_rst_i) begin
word_addr_reg <= {WORD_AW{1'bx}};
end else begin
word_addr_reg <= word_addr;
end
end
assign wb_rty_o = 0;
// Ack Logic
reg wb_ack;
reg nxt_wb_ack;
assign wb_ack_o = wb_ack & wb_stb_i & ~burst_access_wrong_wb_adr;
always @(*) begin
if (wb_cyc_i) begin
if (wb_cti_i == 3'b000) begin
// Classic cycle acks
if (wb_stb_i) begin
if (!wb_ack) begin
nxt_wb_ack = 1;
end else begin
nxt_wb_ack = 0;
end
end else begin
nxt_wb_ack = 0;
end
end else if ((wb_cti_i == 3'b001) ||
(wb_cti_i == 3'b010)) begin
// Increment/constant address bursts
if (wb_stb_i) begin
nxt_wb_ack = 1;
end else begin
nxt_wb_ack = 0;
end
end else if (wb_cti_i == 3'b111) begin
// End of cycle
if (wb_stb_i) begin
if (!wb_ack) begin
nxt_wb_ack = 1;
end else begin
nxt_wb_ack = 0;
end
end else begin
nxt_wb_ack = 0;
end
end else begin
nxt_wb_ack = 0;
end
end else begin
nxt_wb_ack = 0;
end
end // always @ begin
always @(posedge wb_clk_i) begin
if (wb_rst_i) begin
wb_ack <= 1'b0;
end else begin
wb_ack <= nxt_wb_ack;
end
end
assign wb_err_o = wb_ack & wb_stb_i & (burst_access_wrong_wb_adr);
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* Single-Port RAM with Wishbone Interface
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
* Markus Goehrle <[email protected]>
* Philipp Wagner <[email protected]>
*/
module wb_sram_sp(/*AUTOARG*/
// Outputs
wb_ack_o, wb_err_o, wb_rty_o, wb_dat_o,
// Inputs
wb_adr_i, wb_bte_i, wb_cti_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i, wb_clk_i, wb_rst_i
);
import optimsoc_functions::*;
// Memory size in bytes
parameter MEM_SIZE_BYTE = 'hx;
// VMEM file used to initialize the memory in simulation
parameter MEM_FILE = "sram.vmem";
// address width
parameter AW = $clog2(MEM_SIZE_BYTE);
// data width (must be multiple of 8 for byte selects to work)
// Valid values: 32, 16 and 8
parameter DW = 32;
// byte select width
localparam SW = (DW == 32) ? 4 :
(DW == 16) ? 2 :
(DW == 8) ? 1 : 'hx;
// Allowed values:
// * PLAIN
parameter MEM_IMPL_TYPE = "PLAIN";
/*
* +--------------+--------------+
* | word address | byte in word |
* +--------------+--------------+
* WORD_AW BYTE_AW
* +----- AW -----+
*/
localparam BYTE_AW = SW >> 1;
localparam WORD_AW = AW - BYTE_AW;
// Wishbone SLAVE interface
input [AW-1:0] wb_adr_i;
input [1:0] wb_bte_i;
input [2:0] wb_cti_i;
input wb_cyc_i;
input [DW-1:0] wb_dat_i;
input [SW-1:0] wb_sel_i;
input wb_stb_i;
input wb_we_i;
output wb_ack_o;
output wb_err_o;
output wb_rty_o;
output [DW-1:0] wb_dat_o;
input wb_clk_i; // unused
input wb_rst_i; // unused
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [WORD_AW-1:0] sram_waddr; // From wb_ram of wb2sram.v
wire sram_ce; // From wb_ram of wb2sram.v
wire [DW-1:0] sram_din; // From wb_ram of wb2sram.v
wire [DW-1:0] sram_dout; // From sp_ram of sram_sp.v
wire [SW-1:0] sram_sel; // From wb_ram of wb2sram.v
wire sram_we; // From wb_ram of wb2sram.v
// End of automatics
wb2sram
#(.DW(DW),
.AW(AW))
wb_ram(/*AUTOINST*/
// Outputs
.wb_ack_o (wb_ack_o),
.wb_err_o (wb_err_o),
.wb_rty_o (wb_rty_o),
.wb_dat_o (wb_dat_o[DW-1:0]),
.sram_ce (sram_ce),
.sram_we (sram_we),
.sram_waddr (sram_waddr),
.sram_din (sram_din[DW-1:0]),
.sram_sel (sram_sel[SW-1:0]),
// Inputs
.wb_adr_i (wb_adr_i[AW-1:0]),
.wb_bte_i (wb_bte_i[1:0]),
.wb_cti_i (wb_cti_i[2:0]),
.wb_cyc_i (wb_cyc_i),
.wb_dat_i (wb_dat_i[DW-1:0]),
.wb_sel_i (wb_sel_i[SW-1:0]),
.wb_stb_i (wb_stb_i),
.wb_we_i (wb_we_i),
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.sram_dout (sram_dout[DW-1:0]));
/* sram_sp AUTO_TEMPLATE(
.clk (wb_clk_i),
.rst (wb_rst_i),
.ce (sram_ce),
.we (sram_we),
.oe (1'b1),
.waddr (sram_waddr),
.sel (sram_sel),
.din (sram_din),
.dout (sram_dout[]),
); */
sram_sp
#(.DW (DW),
.MEM_SIZE_BYTE (MEM_SIZE_BYTE),
.AW (AW),
.WORD_AW (WORD_AW),
.MEM_IMPL_TYPE (MEM_IMPL_TYPE),
.MEM_FILE (MEM_FILE))
sp_ram(/*AUTOINST*/
// Outputs
.dout (sram_dout[DW-1:0]), // Templated
// Inputs
.clk (wb_clk_i), // Templated
.rst (wb_rst_i), // Templated
.ce (sram_ce), // Templated
.we (sram_we), // Templated
.oe (1'b1), // Templated
.waddr (sram_waddr), // Templated
.din (sram_din), // Templated
.sel (sram_sel)); // Templated
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is a round-robin arbiter for N participants, which is a
* parameter. The arbiter itself contains no register but is purely
* combinational which allows for various use cases. It simply
* calculates the next grant (nxt_gnt) based on the current grant
* (gnt) and the requests (req).
*
* That means, the gnt should in general be a register and especially
* there must be no combinational path from nxt_gnt to gnt!
*
* The normal usage is something like registering the gnt from
* nxt_gnt. Furthermore it is important that the gnt has an initial
* value which also must be one hot!
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module arb_rr
#(parameter N = 2)
(
input [N-1:0] req,
input en,
input [N-1:0] gnt,
output [N-1:0] nxt_gnt
);
// At a first glance, the computation of the nxt_gnt signal looks
// strange, but the principle is easy:
//
// * For each participant we compute a mask of width N. Based on
// the current gnt signal the mask contains a 1 at the position
// of other participants that will be served in round robin
// before the participant in case they request it.
//
// * The mask is 0 on all positions for the participant "left" of
// the currently granted participant as no other has precedence
// over this one. The mask has all one except the participant
// itself for the currently arbitrated participant.
//
// * From the mask and the request the nxt_gnt is calculated,
// roughly said as: if there is no other participant which has a
// higher precedence that also requests, the participant gets
// granted.
//
// Example 1:
// req = 1010
// gnt = 1000
// nxt_gnt = 0010
//
// mask[0] = 0000
// mask[1] = 0001
// mask[2] = 0011
// mask[3] = 0111
//
// Example 2:
// req = 1010
// gnt = 0100
// nxt_gnt = 1000
//
// mask[0] = 1000
// mask[1] = 1001
// mask[2] = 1011
// mask[3] = 0000
// Mask net
reg [N-1:0] mask [0:N-1];
// Calculate the mask
always @(*) begin : calc_mask
integer i,j;
for (i=0;i<N;i=i+1) begin
// Initialize mask as 0
mask[i] = {N{1'b0}};
// All participants to the "right" up to the current grant
// holder have precendence and therefore a 1 in the mask.
// First check if the next right from us has the grant.
// Afterwards the mask is calculated iteratively based on
// this.
if(i>0)
// For i=N:1 the next right is i-1
mask[i][i-1] = ~gnt[i-1];
else
// For i=0 the next right is N-1
mask[i][N-1] = ~gnt[N-1];
// Now the mask contains a 1 when the next right to us is not
// the grant holder. If it is the grant holder that means,
// that we are the next served (if necessary) as no other has
// higher precendence, which is then calculated in the
// following by filling up 1s up to the grant holder. To stop
// filling up there and not fill up any after this is
// iterative by always checking if the one before was not
// before the grant holder.
for (j=2;j<N;j=j+1) begin
if (i-j>=0)
mask[i][i-j] = mask[i][i-j+1] & ~gnt[i-j];
else if(i-j+1>=0)
mask[i][i-j+N] = mask[i][i-j+1] & ~gnt[i-j+N];
else
mask[i][i-j+N] = mask[i][i-j+N+1] & ~gnt[i-j+N];
end
end
end // always @ (*)
// Calculate the nxt_gnt
genvar k;
generate
for (k=0;k<N;k=k+1) begin : gen_nxt_gnt
// (mask[k] & req) masks all requests with higher precendence
// Example 1: 0: 0000 1: 0000 2: 0010 3: 0010
// Example 2: 0: 1000 1: 1000 2: 1010 3: 0000
//
// ~|(mask[k] & req) is there is none of them
// Example 1: 0: 1 1: 1 2: 0 3: 0
// Example 2: 1: 0 1: 0 2: 0 3: 1
//
// One might expect at this point that there was only one of
// them that matches, but this is guaranteed by the last part
// that is checking if this one has a request itself. In
// example 1, k=0 does not have a request, if it had, the
// result of the previous calculation would be 0 for k=1.
// Therefore: (~|(mask[k] & req) & req[k]) selects the next one.
// Example 1: 0: 0 1: 1 2: 0 3: 0
// Example 2: 0: 0 1: 0 2: 0 3: 1
//
// This is already the result. (0010 and 1000). Nevertheless,
// it is necessary to capture the case of no request at all
// (~|req). In that case, nxt_gnt would be 0, what iself
// leads to a problem in the next cycle (always grants).
// Therefore the current gnt is hold in case of no request by
// (~|req & gnt[k]).
//
// Finally, we only arbitrate when enable is set.
assign nxt_gnt[k] = en ? (~|(mask[k] & req) & req[k]) | (~|req & gnt[k])
: gnt[k];
end
endgenerate
endmodule // arb_rr
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* As SystemVerilog allows for better definition of datatypes than
* the macros in lisnoc_def.vh this is provided for convenience.
* You always must assure that the settings correspond to the ones
* in Verilog.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
* Andreas Lankes <[email protected]>
* Michael Tempelmeier <[email protected]>
*/
typedef enum bit[4:0] {SELECT_NONE=0,SELECT_NORTH=1,SELECT_EAST=2,SELECT_SOUTH=4,SELECT_WEST=8,SELECT_LOCAL=16} dir_select_t;
`define NORTH 0
`define EAST 1
`define SOUTH 2
`define WEST 3
`define LOCAL 4
typedef enum bit [1:0] { HEADER=2'b01, SINGLE=2'b11, PAYLOAD=2'b00, LAST=2'b10 } flit_type_t;
class flit_t #(int data_width=32,int type_width=2);
bit [type_width-1:0] ftype;
bit [data_width-1:0] content;
endclass
class flit_header_t #(int data_width=32);
bit [4:0] dest;
bit [3:0] prio;
bit [2:0] packet_class;
bit [data_width-13:0] class_specific;
endclass
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the definition file. All Verilog macros are defined here.
* Please note, that it is not intended to be used for configuration
* (which should be done via parameters) but more for specific
* constants, that might change over longer time periods.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
* Andreas Lankes <[email protected]>
* Michael Tempelmeier <[email protected]>
*/
`define FLIT_TYPE_PAYLOAD 2'b00
`define FLIT_TYPE_HEADER 2'b01
`define FLIT_TYPE_LAST 2'b10
`define FLIT_TYPE_SINGLE 2'b11
// Convenience definitions for mesh
`define SELECT_NONE 5'b00000
`define SELECT_NORTH 5'b00001
`define SELECT_EAST 5'b00010
`define SELECT_SOUTH 5'b00100
`define SELECT_WEST 5'b01000
`define SELECT_LOCAL 5'b10000
`define NORTH 0
`define EAST 1
`define SOUTH 2
`define WEST 3
`define LOCAL 4
|
`include "lisnoc_def.vh"
`define FLIT_WIDTH 34
// Type of flit
// The coding is chosen, so that
// type[0] signals that this is the first flit of a packet
// type[1] signals that this is the last flit of a packet
`define FLIT_TYPE_MSB (`FLIT_WIDTH - 1)
`define FLIT_TYPE_WIDTH 2
`define FLIT_TYPE_LSB (`FLIT_TYPE_MSB - `FLIT_TYPE_WIDTH + 1)
// This is the flit content size
`define FLIT_CONTENT_WIDTH 32
`define FLIT_CONTENT_MSB 31
`define FLIT_CONTENT_LSB 0
// The following fields are only valid for header flits
`define FLIT_DEST_WIDTH 5
// destination address field of header flit
`define FLIT_DEST_MSB `FLIT_CONTENT_MSB
`define FLIT_DEST_LSB `FLIT_DEST_MSB - `FLIT_DEST_WIDTH + 1
// packet type field of header flit
`define PACKET_CLASS_MSB (`FLIT_DEST_LSB - 1)
`define PACKET_CLASS_WIDTH 3
`define PACKET_CLASS_LSB (`PACKET_CLASS_MSB - `PACKET_CLASS_WIDTH + 1)
`define PACKET_CLASS_DMA 3'b010
// source address field of header flit
`define SOURCE_MSB 23
`define SOURCE_WIDTH 5
`define SOURCE_LSB 19
// packet id field of header flit
`define PACKET_ID_MSB 18
`define PACKET_ID_WIDTH 4
`define PACKET_ID_LSB 15
`define PACKET_TYPE_MSB 14
`define PACKET_TYPE_WIDTH 2
`define PACKET_TYPE_LSB 13
`define PACKET_TYPE_L2R_REQ 2'b00
`define PACKET_TYPE_R2L_REQ 2'b01
`define PACKET_TYPE_L2R_RESP 2'b10
`define PACKET_TYPE_R2L_RESP 2'b11
`define PACKET_REQ_LAST 12
`define PACKET_RESP_LAST 12
`define SIZE_MSB 31
`define SIZE_WIDTH 32
`define SIZE_LSB 0
`define DMA_REQUEST_WIDTH 103
`define DMA_REQFIELD_LADDR_WIDTH 32
`define DMA_REQFIELD_SIZE_WIDTH 32
`define DMA_REQFIELD_RTILE_WIDTH 5
`define DMA_REQFIELD_RADDR_WIDTH 32
`define DMA_REQFIELD_LADDR_MSB 102
`define DMA_REQFIELD_LADDR_LSB 70
`define DMA_REQFIELD_SIZE_MSB 69
`define DMA_REQFIELD_SIZE_LSB 38
`define DMA_REQFIELD_RTILE_MSB 37
`define DMA_REQFIELD_RTILE_LSB 33
`define DMA_REQFIELD_RADDR_MSB 32
`define DMA_REQFIELD_RADDR_LSB 1
`define DMA_REQFIELD_DIR 0
`define DMA_REQUEST_INVALID 1'b0
`define DMA_REQUEST_VALID 1'b1
`define DMA_REQUEST_L2R 1'b0
`define DMA_REQUEST_R2L 1'b1
`define DMA_REQMASK_WIDTH 5
`define DMA_REQMASK_LADDR 0
`define DMA_REQMASK_SIZE 1
`define DMA_REQMASK_RTILE 2
`define DMA_REQMASK_RADDR 3
`define DMA_REQMASK_DIR 4
`define DMA_RESPFIELD_SIZE_WIDTH 14
|
`include "lisnoc_def.vh"
`undef FLIT_WIDTH
`undef FLIT_TYPE_MSB
`undef FLIT_TYPE_WIDTH
`undef FLIT_TYPE_LSB
`undef FLIT_CONTENT_WIDTH
`undef FLIT_CONTENT_MSB
`undef FLIT_CONTENT_LSB
`undef FLIT_DEST_WIDTH
`undef FLIT_DEST_MSB
`undef FLIT_DEST_LSB
`undef PACKET_CLASS_MSB
`undef PACKET_CLASS_WIDTH
`undef PACKET_CLASS_LSB
`undef PACKET_CLASS_DMA
// source address field of header flit
`undef SOURCE_MSB
`undef SOURCE_WIDTH
`undef SOURCE_LSB
// packet id field of header flit
`undef PACKET_ID_MSB
`undef PACKET_ID_WIDTH
`undef PACKET_ID_LSB
`undef PACKET_TYPE_MSB
`undef PACKET_TYPE_WIDTH
`undef PACKET_TYPE_LSB
`undef PACKET_TYPE_L2R_REQ
`undef PACKET_TYPE_R2L_REQ
`undef PACKET_TYPE_L2R_RESP
`undef PACKET_TYPE_R2L_RESP
`undef PACKET_REQ_LAST
`undef PACKET_RESP_LAST
`undef SIZE_MSB
`undef SIZE_WIDTH
`undef SIZE_LSB
`undef DMA_REQUEST_WIDTH
`undef DMA_REQFIELD_LADDR_WIDTH
`undef DMA_REQFIELD_SIZE_WIDTH
`undef DMA_REQFIELD_RTILE_WIDTH
`undef DMA_REQFIELD_RADDR_WIDTH
`undef DMA_REQFIELD_LADDR_MSB
`undef DMA_REQFIELD_LADDR_LSB
`undef DMA_REQFIELD_SIZE_MSB
`undef DMA_REQFIELD_SIZE_LSB
`undef DMA_REQFIELD_RTILE_MSB
`undef DMA_REQFIELD_RTILE_LSB
`undef DMA_REQFIELD_RADDR_MSB
`undef DMA_REQFIELD_RADDR_LSB
`undef DMA_REQFIELD_DIR
`undef DMA_REQUEST_INVALID
`undef DMA_REQUEST_VALID
`undef DMA_REQMASK_WIDTH
`undef DMA_REQMASK_LADDR
`undef DMA_REQMASK_SIZE
`undef DMA_REQMASK_RTILE
`undef DMA_REQMASK_RADDR
`undef DMA_REQMASK_DIR
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This file should be included at the end of every file that
* includes lisnoc_def.vh. It avoids any conflicts with your system.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
* Andreas Lankes <[email protected]>
* Michael Tempelmeier <[email protected]>
*/
`undef FLIT_TYPE_PAYLOAD
`undef FLIT_TYPE_HEADER
`undef FLIT_TYPE_LAST
`undef FLIT_TYPE_SINGLE
`undef SELECT_NORTH
`undef SELECT_EAST
`undef SELECT_SOUTH
`undef SELECT_WEST
`undef SELECT_LOCAL
`undef NORTH
`undef EAST
`undef SOUTH
`undef WEST
`undef LOCAL
|
/* Copyright (c) 2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* Buffer for NoC packets
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
* Wei Song <[email protected]>
*/
module noc_buffer
#(parameter FLIT_WIDTH = 32,
parameter DEPTH = 16,
parameter FULLPACKET = 0,
localparam ID_W = $clog2(DEPTH) // the width of the index
)(
input clk,
input rst,
// FIFO input side
input [FLIT_WIDTH-1:0] in_flit,
input in_last,
input in_valid,
output in_ready,
//FIFO output side
output reg [FLIT_WIDTH-1:0] out_flit,
output reg out_last,
output reg out_valid,
input out_ready,
output [ID_W-1:0] packet_size
);
// internal shift register
reg [DEPTH-1:0][FLIT_WIDTH:0] data;
reg [ID_W:0] rp; // read pointer
logic reg_out_valid; // local output valid
logic in_fire, out_fire;
assign in_ready = (rp != DEPTH - 1) || !reg_out_valid;
assign in_fire = in_valid && in_ready;
assign out_fire = out_valid && out_ready;
always_ff @(posedge clk)
if(rst)
reg_out_valid <= 0;
else if(in_valid)
reg_out_valid <= 1;
else if(out_fire && rp == 0)
reg_out_valid <= 0;
always_ff @(posedge clk)
if(rst)
rp <= 0;
else if(in_fire && !out_fire && reg_out_valid)
rp <= rp + 1;
else if(out_fire && !in_fire && rp != 0)
rp <= rp - 1;
always @(posedge clk)
if(in_fire)
data <= {data, {in_last, in_flit}};
generate // SRL does not allow parallel read
if(FULLPACKET != 0) begin
logic [DEPTH-1:0] data_last_buf, data_last_shifted;
always @(posedge clk)
if(rst)
data_last_buf <= 0;
else if(in_fire)
data_last_buf <= {data_last_buf, in_last && in_valid};
// extra logic to get the packet size in a stable manner
assign data_last_shifted = data_last_buf << DEPTH - 1 - rp;
function logic [ID_W:0] find_first_one(input logic [DEPTH-1:0] data);
automatic int i;
for(i=DEPTH-1; i>=0; i--)
if(data[i]) return i;
return DEPTH;
endfunction // size_count
assign packet_size = DEPTH - find_first_one(data_last_shifted);
always_comb begin
out_flit = data[rp][FLIT_WIDTH-1:0];
out_last = data[rp][FLIT_WIDTH];
out_valid = reg_out_valid && |data_last_shifted;
end
end else begin // if (FULLPACKET)
assign packet_size = 0;
always_comb begin
out_flit = data[rp][FLIT_WIDTH-1:0];
out_last = data[rp][FLIT_WIDTH];
out_valid = reg_out_valid;
end
end
endgenerate
endmodule // noc_buffer
|
/* Copyright (c) 2015-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* Route packets to an output port depending on the class
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module noc_demux
import optimsoc_config::*;
import optimsoc_constants::*;
#(
parameter FLIT_WIDTH = 32,
parameter CHANNELS = 2,
parameter [63:0] MAPPING = 'x
)
(
input clk, rst,
input [FLIT_WIDTH-1:0] in_flit,
input in_last,
input in_valid,
output reg in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] out_flit,
output [CHANNELS-1:0] out_last,
output reg [CHANNELS-1:0] out_valid,
input [CHANNELS-1:0] out_ready
);
reg [CHANNELS-1:0] active;
reg [CHANNELS-1:0] nxt_active;
wire [2:0] packet_class;
reg [CHANNELS-1:0] select;
assign packet_class = in_flit[NOC_CLASS_MSB:NOC_CLASS_LSB];
always @(*) begin : gen_select
select = MAPPING[8*packet_class +: CHANNELS];
if (select == 0) begin
select = { {CHANNELS-1{1'b0}}, 1'b1};
end
end
assign out_flit = {CHANNELS{in_flit}};
assign out_last = {CHANNELS{in_last}};
always @(*) begin
nxt_active = active;
out_valid = 0;
in_ready = 0;
if (active == 0) begin
in_ready = |(select & out_ready);
out_valid = select & {CHANNELS{in_valid}};
if (in_valid & ~in_last) begin
nxt_active = select;
end
end else begin
in_ready = |(active & out_ready);
out_valid = active & {CHANNELS{in_valid}};
if (in_valid & in_last) begin
nxt_active = 0;
end
end
end
always @(posedge clk)
if (rst) begin
active <= '0;
end else begin
active <= nxt_active;
end
endmodule // noc_demux
|
/* Copyright (c) 2015-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* Arbitrate between different channels, don't break worms.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
* Andreas Lankes <[email protected]>
*/
module noc_mux
import optimsoc_config::*;
#(
parameter FLIT_WIDTH = 32,
parameter CHANNELS = 2
)
(
input clk, rst,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] in_flit,
input [CHANNELS-1:0] in_last,
input [CHANNELS-1:0] in_valid,
output reg [CHANNELS-1:0] in_ready,
output reg [FLIT_WIDTH-1:0] out_flit,
output reg out_last,
output reg out_valid,
input out_ready
);
wire [CHANNELS-1:0] select;
reg [CHANNELS-1:0] active;
reg activeroute, nxt_activeroute;
wire [CHANNELS-1:0] req_masked;
assign req_masked = {CHANNELS{~activeroute & out_ready}} & in_valid;
always @(*) begin
out_flit = {FLIT_WIDTH{1'b0}};
out_last = 1'b0;
for (int c = 0; c < CHANNELS; c = c + 1) begin
if (select[c]) begin
out_flit = in_flit[c];
out_last = in_last[c];
end
end
end
always @(*) begin
nxt_activeroute = activeroute;
in_ready = {CHANNELS{1'b0}};
if (activeroute) begin
if (|(in_valid & active) && out_ready) begin
in_ready = active;
out_valid = 1;
if (out_last)
nxt_activeroute = 0;
end else begin
out_valid = 1'b0;
in_ready = 0;
end
end else begin
out_valid = 0;
if (|in_valid) begin
out_valid = 1'b1;
nxt_activeroute = ~out_last;
in_ready = select & {CHANNELS{out_ready}};
end
end
end // always @ (*)
always @(posedge clk) begin
if (rst) begin
activeroute <= 0;
active <= {{CHANNELS-1{1'b0}},1'b1};
end else begin
activeroute <= nxt_activeroute;
active <= select;
end
end
arb_rr
#(.N(CHANNELS))
u_arb
(.nxt_gnt (select),
.req (req_masked),
.gnt (active),
.en (1));
endmodule // noc_mux
|
/* Copyright (c) 2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is a NoC router. It has a configurable number of input ports
* and output ports, that are not necessarily equal. It supports
* virtual channels, meaning that the flit signal between routers is
* shared logically.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module noc_router
#(parameter FLIT_WIDTH = 32,
parameter VCHANNELS = 1,
parameter INPUTS = 'x,
parameter OUTPUTS = 'x,
parameter BUFFER_SIZE_IN = 4,
parameter BUFFER_SIZE_OUT = 4,
parameter DESTS = 'x,
parameter [OUTPUTS*DESTS-1:0] ROUTES = {DESTS*OUTPUTS{1'b0}}
)
(
input clk, rst,
output [OUTPUTS-1:0][FLIT_WIDTH-1:0] out_flit,
output [OUTPUTS-1:0] out_last,
output [OUTPUTS-1:0][VCHANNELS-1:0] out_valid,
input [OUTPUTS-1:0][VCHANNELS-1:0] out_ready,
input [INPUTS-1:0][FLIT_WIDTH-1:0] in_flit,
input [INPUTS-1:0] in_last,
input [INPUTS-1:0][VCHANNELS-1:0] in_valid,
output [INPUTS-1:0][VCHANNELS-1:0] in_ready
);
// The "switch" is just wiring (all logic is in input and
// output). All inputs generate their requests for the outputs and
// the output arbitrate between the input requests.
// The input valid signals are one (or zero) hot and hence share
// the flit signal.
wire [INPUTS-1:0][VCHANNELS-1:0][FLIT_WIDTH-1:0] switch_in_flit;
wire [INPUTS-1:0][VCHANNELS-1:0] switch_in_last;
wire [INPUTS-1:0][VCHANNELS-1:0][OUTPUTS-1:0] switch_in_valid;
wire [INPUTS-1:0][VCHANNELS-1:0][OUTPUTS-1:0] switch_in_ready;
// Outputs are fully wired to receive all input requests.
wire [OUTPUTS-1:0][VCHANNELS-1:0][INPUTS-1:0][FLIT_WIDTH-1:0] switch_out_flit;
wire [OUTPUTS-1:0][VCHANNELS-1:0][INPUTS-1:0] switch_out_last;
wire [OUTPUTS-1:0][VCHANNELS-1:0][INPUTS-1:0] switch_out_valid;
wire [OUTPUTS-1:0][VCHANNELS-1:0][INPUTS-1:0] switch_out_ready;
genvar i, v, o;
generate
for (i = 0; i < INPUTS; i++) begin : inputs
// The input stages
noc_router_input
#(.FLIT_WIDTH(FLIT_WIDTH), .VCHANNELS(VCHANNELS),
.DESTS(DESTS), .OUTPUTS(OUTPUTS), .ROUTES(ROUTES),
.BUFFER_DEPTH (BUFFER_SIZE_IN))
u_input
(.*,
.in_flit (in_flit[i]),
.in_last (in_last[i]),
.in_valid (in_valid[i]),
.in_ready (in_ready[i]),
.out_flit (switch_in_flit[i]),
.out_last (switch_in_last[i]),
.out_valid (switch_in_valid[i]),
.out_ready (switch_in_ready[i])
);
end // block: inputs
// The switching logic
for (o = 0; o < OUTPUTS; o++) begin
for (v = 0; v < VCHANNELS; v++) begin
for (i = 0; i < INPUTS; i++) begin
assign switch_out_flit[o][v][i] = switch_in_flit[i][v];
assign switch_out_last[o][v][i] = switch_in_last[i][v];
assign switch_out_valid[o][v][i] = switch_in_valid[i][v][o];
assign switch_in_ready[i][v][o] = switch_out_ready[o][v][i];
end
end
end
for (o = 0; o < OUTPUTS; o++) begin : outputs
// The output stages
noc_router_output
#(.FLIT_WIDTH(FLIT_WIDTH), .VCHANNELS(VCHANNELS),
.INPUTS(INPUTS), .BUFFER_DEPTH(BUFFER_SIZE_OUT))
u_output
(.*,
.in_flit (switch_out_flit[o]),
.in_last (switch_out_last[o]),
.in_valid (switch_out_valid[o]),
.in_ready (switch_out_ready[o]),
.out_flit (out_flit[o]),
.out_last (out_last[o]),
.out_valid (out_valid[o]),
.out_ready (out_ready[o]));
end
endgenerate
endmodule // noc_router
|
/* Copyright (c) 2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the input stage of the router. It buffers the flits and
* routes them to the proper output.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module noc_router_input
#(parameter FLIT_WIDTH = 'x,
parameter VCHANNELS = 1,
parameter DESTS = 1,
parameter OUTPUTS = 1,
parameter [OUTPUTS*DESTS-1:0] ROUTES = {DESTS*OUTPUTS{1'b0}},
parameter BUFFER_DEPTH = 4
)
(
input clk,
input rst,
input [FLIT_WIDTH-1:0] in_flit,
input in_last,
input [VCHANNELS-1:0] in_valid,
output [VCHANNELS-1:0] in_ready,
output [VCHANNELS-1:0][OUTPUTS-1:0] out_valid,
output [VCHANNELS-1:0] out_last,
output [VCHANNELS-1:0][FLIT_WIDTH-1:0] out_flit,
input [VCHANNELS-1:0][OUTPUTS-1:0] out_ready
);
generate
genvar v;
for (v = 0; v < VCHANNELS; v++) begin : vc
wire [FLIT_WIDTH-1:0] buffer_flit;
wire buffer_last;
wire buffer_valid;
wire buffer_ready;
noc_buffer
#(.FLIT_WIDTH (FLIT_WIDTH),
.DEPTH (BUFFER_DEPTH))
u_buffer
(.*,
.in_valid (in_valid[v]),
.in_ready (in_ready[v]),
.out_flit (buffer_flit),
.out_last (buffer_last),
.out_valid (buffer_valid),
.out_ready (buffer_ready),
.packet_size ()
);
noc_router_lookup
#(.FLIT_WIDTH (FLIT_WIDTH), .DESTS (DESTS),
.OUTPUTS (OUTPUTS), .ROUTES (ROUTES))
u_lookup
(.*,
.in_flit (buffer_flit),
.in_last (buffer_last),
.in_valid (buffer_valid),
.in_ready (buffer_ready),
.out_flit (out_flit[v]),
.out_last (out_last[v]),
.out_valid (out_valid[v]),
.out_ready (out_ready[v])
);
end
endgenerate
endmodule // noc_router_input
|
/* Copyright (c) 2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the route lookup. It uses a given table of routes. It first
* extracts the destination of the incoming NoC packets and then looks
* the output port up. The output valid and ready signals contain bits
* for each output and the flit and last are shared by the outputs.
*
* The output of this module is registered, minimizing the critical
* path to the lookup function.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module noc_router_lookup
#(parameter FLIT_WIDTH = 32,
parameter DEST_WIDTH = 5,
parameter DESTS = 1,
parameter OUTPUTS = 1,
parameter [DESTS*OUTPUTS-1:0] ROUTES = {DESTS*OUTPUTS{1'b0}}
)
(
input clk,
input rst,
input [FLIT_WIDTH-1:0] in_flit,
input in_last,
input in_valid,
output in_ready,
output [OUTPUTS-1:0] out_valid,
output out_last,
output [FLIT_WIDTH-1:0] out_flit,
input [OUTPUTS-1:0] out_ready
);
// We need to track worms and directly encode the output of the
// current worm.
reg [OUTPUTS-1:0] worm;
logic [OUTPUTS-1:0] nxt_worm;
// This is high if we are in a worm
logic wormhole;
assign wormhole = |worm;
// Extract destination from flit
logic [DEST_WIDTH-1:0] dest;
assign dest = in_flit[FLIT_WIDTH-1 -: DEST_WIDTH];
// This is the selection signal of the slave, one hot so that it
// directly serves as flow control valid
logic [OUTPUTS-1:0] valid;
// Register slice at the output.
noc_router_lookup_slice
#(.FLIT_WIDTH (FLIT_WIDTH),
.OUTPUTS (OUTPUTS))
u_slice
(.*,
.in_valid (valid));
always_comb begin
nxt_worm = worm;
valid = 0;
if (!wormhole) begin
// We are waiting for a flit
if (in_valid) begin
// This is a header. Lookup output
valid = ROUTES[dest*OUTPUTS +: OUTPUTS];
if (in_ready & !in_last) begin
// If we can push it further and it is not the only
// flit, enter a worm and store the output
nxt_worm = ROUTES[dest*OUTPUTS +: OUTPUTS];
end
end
end else begin // if (!wormhole)
// We are in a worm
// The valid is set on the currently select output
valid = worm & {OUTPUTS{in_valid}};
if (in_ready & in_last) begin
// End of worm
nxt_worm = 0;
end
end
end
always_ff @(posedge clk) begin
if (rst) begin
worm <= 0;
end else begin
worm <= nxt_worm;
end
end
endmodule
|
/* Copyright (c) 2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
*
* This is a register slice at the routing stage of the router. It
* latches the current flit and decouples the outputs and the input
* entirely. That means that there is no combinational path from input
* to output and vice versa. Hence it allows for higher clock
* speeds. To avoid stop-and-go behavior it has a second register to
* be able to store the extra register on backpressure. The
* backpressure then manifests with one cycle delay.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module noc_router_lookup_slice
#(parameter FLIT_WIDTH = 32,
parameter OUTPUTS = 1
)
(
input clk,
input rst,
input [FLIT_WIDTH-1:0] in_flit,
input in_last,
input [OUTPUTS-1:0] in_valid,
output in_ready,
output reg [OUTPUTS-1:0] out_valid,
output reg out_last,
output reg [FLIT_WIDTH-1:0] out_flit,
input [OUTPUTS-1:0] out_ready
);
// This is an intermediate register that we use to avoid
// stop-and-go behavior
reg [FLIT_WIDTH-1:0] reg_flit;
reg reg_last;
reg [OUTPUTS-1:0] reg_valid;
// This signal selects where to store the next incoming flit
reg pressure;
// A backpressure in the output port leads to backpressure on the
// input with one cycle delay
assign in_ready = !pressure;
always_ff @(posedge clk) begin
if (rst) begin
pressure <= 0;
out_valid <= 0;
end else begin
if (!pressure) begin
// We are accepting the input in this cycle, determine
// where to store it..
if (// There is no flit waiting in the register, or
~|out_valid
// The current flit is transfered this cycle
| (|(out_ready & out_valid))) begin
out_flit <= in_flit;
out_last <= in_last;
out_valid <= in_valid;
end else if (|out_valid & ~|out_ready) begin
// Otherwise if there is a flit waiting and upstream
// not ready, push it to the second register. Enter the
// backpressure mode.
reg_flit <= in_flit;
reg_last <= in_last;
reg_valid <= in_valid;
pressure <= 1;
end
end else begin // if (!pressure)
// We can be sure that a flit is waiting now (don't need
// to check)
if (|out_ready) begin
// If the output accepted this flit, go back to
// accepting input flits.
out_flit <= reg_flit;
out_last <= reg_last;
out_valid <= reg_valid;
pressure <= 0;
end
end
end
end
endmodule // noc_router_lookup_slice
|
/* Copyright (c) 2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
*
* This is the output port. It muxes between concurrent input packets
* and buffers them before forwarding to the next router. If virtual
* channels are used, it muxes between the different virtual channels
* in this output port.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module noc_router_output
#(parameter FLIT_WIDTH = 'x,
parameter VCHANNELS = 1,
parameter INPUTS = 1,
parameter BUFFER_DEPTH = 4
)
(
input clk,
input rst,
input [VCHANNELS-1:0][INPUTS-1:0][FLIT_WIDTH-1:0] in_flit,
input [VCHANNELS-1:0][INPUTS-1:0] in_last,
input [VCHANNELS-1:0][INPUTS-1:0] in_valid,
output [VCHANNELS-1:0][INPUTS-1:0] in_ready,
output [FLIT_WIDTH-1:0] out_flit,
output out_last,
output [VCHANNELS-1:0] out_valid,
input [VCHANNELS-1:0] out_ready
);
genvar v;
wire [VCHANNELS-1:0][FLIT_WIDTH-1:0] channel_flit;
wire [VCHANNELS-1:0] channel_last;
wire [VCHANNELS-1:0] channel_valid;
wire [VCHANNELS-1:0] channel_ready;
generate
for (v = 0; v < VCHANNELS; v++) begin
wire [FLIT_WIDTH-1:0] buffer_flit;
wire buffer_last;
wire buffer_valid;
wire buffer_ready;
noc_mux
#(.FLIT_WIDTH (FLIT_WIDTH), .CHANNELS (INPUTS))
u_mux
(.*,
.in_flit (in_flit[v]),
.in_last (in_last[v]),
.in_valid (in_valid[v]),
.in_ready (in_ready[v]),
.out_flit (buffer_flit),
.out_last (buffer_last),
.out_valid (buffer_valid),
.out_ready (buffer_ready));
noc_buffer
#(.FLIT_WIDTH (FLIT_WIDTH), .DEPTH(BUFFER_DEPTH))
u_buffer
(.*,
.in_flit (buffer_flit),
.in_last (buffer_last),
.in_valid (buffer_valid),
.in_ready (buffer_ready),
.out_flit (channel_flit[v]),
.out_last (channel_last[v]),
.out_valid (channel_valid[v]),
.out_ready (channel_ready[v]),
.packet_size ()
);
end // for (v = 0; v < VCHANNELS; v++)
if (VCHANNELS > 1) begin : vc_mux
noc_vchannel_mux
#(.FLIT_WIDTH (FLIT_WIDTH), .CHANNELS(VCHANNELS))
u_mux
(.*,
.in_flit (channel_flit),
.in_last (channel_last),
.in_valid (channel_valid),
.in_ready (channel_ready)
);
end else begin // block: vc_mux
assign out_flit = channel_flit[0];
assign out_last = channel_last[0];
assign out_valid = channel_valid[0];
assign channel_ready[0] = out_ready;
end
endgenerate
endmodule // noc_router_output
|
/* Copyright (c) 2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* Mux virtual channels
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module noc_vchannel_mux
#(parameter FLIT_WIDTH = 32,
parameter CHANNELS = 2)
(
input clk,
input rst,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] in_flit,
input [CHANNELS-1:0] in_last,
input [CHANNELS-1:0] in_valid,
output [CHANNELS-1:0] in_ready,
output reg [FLIT_WIDTH-1:0] out_flit,
output reg out_last,
output [CHANNELS-1:0] out_valid,
input [CHANNELS-1:0] out_ready
);
reg [CHANNELS-1:0] select;
logic [CHANNELS-1:0] nxt_select;
assign out_valid = in_valid & select;
assign in_ready = out_ready & select;
always @(*) begin
out_flit = 'x;
out_last = 'x;
for (int c = 0; c < CHANNELS; c++) begin
if (select[c]) begin
out_flit = in_flit[c];
out_last = in_last[c];
end
end
end
arb_rr
#(.N (CHANNELS))
u_arbiter
(.req (in_valid & out_ready),
.en (1),
.gnt (select),
.nxt_gnt (nxt_select));
always_ff @(posedge clk) begin
if (rst) begin
select <= {{CHANNELS-1{1'b0}},1'b1};
end else begin
select <= nxt_select;
end
end
endmodule // noc_vchannel_mux
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the compute tile for distributed memory systems.
*
*
* The assignment of the 32 bit IRQ vector connected to core 0 is as follows:
* - Bit [1:0]: N/A
* - Bit 2: UART
* - Bit 3: NA - message passing
* - Bit 4: NA - DMA
* - Bit [31:5]: N/A
*
* The address ranges of the bus slaves are as follows:
* - Slave 0 - DM: 0x00000000-0x7fffffff
* - Slave 1 - PGAS: not used
* - Slave 2 - NA: 0xe0000000-0xefffffff
* - Slave 3 - BOOT: 0xf0000000-0xffffffff
* - Slave 4 - UART: 0x90000000-0x9000000f
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module compute_tile_dm_crypto1_top
import dii_package::dii_flit;
import opensocdebug::mor1kx_trace_exec;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
parameter ID = 'x,
parameter COREBASE = 'x,
parameter DEBUG_BASEID = 'x,
parameter MEM_FILE = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH
)
(
input dii_flit [1:0] debug_ring_in,
output [1:0] debug_ring_in_ready,
output dii_flit [1:0] debug_ring_out,
input [1:0] debug_ring_out_ready,
output [31:0] wb_ext_adr_i,
output wb_ext_cyc_i,
output [31:0] wb_ext_dat_i,
output [3:0] wb_ext_sel_i,
output wb_ext_stb_i,
output wb_ext_we_i,
output wb_ext_cab_i,
output [2:0] wb_ext_cti_i,
output [1:0] wb_ext_bte_i,
input wb_ext_ack_o,
input wb_ext_rty_o,
input wb_ext_err_o,
input [31:0] wb_ext_dat_o,
input clk,
input rst_cpu, rst_sys, rst_dbg,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
import optimsoc_functions::*;
localparam NR_MASTERS = 0;
localparam NR_SLAVES = 4;
localparam SLAVE_DES3 = 0;
localparam SLAVE_SHA = 1;
localparam SLAVE_NA = 2;
localparam SLAVE_AES_192 = 3;
logic wb_mem_clk_i;
logic wb_mem_rst_i;
logic [31:0] wb_mem_adr_i;
logic wb_mem_cyc_i;
logic [31:0] wb_mem_dat_i;
logic [3:0] wb_mem_sel_i;
logic wb_mem_stb_i;
logic wb_mem_we_i;
logic wb_mem_cab_i;
logic [2:0] wb_mem_cti_i;
logic [1:0] wb_mem_bte_i;
logic wb_mem_ack_o;
logic wb_mem_rty_o;
logic wb_mem_err_o;
logic [31:0] wb_mem_dat_o;
// create DI ring segment with routers
localparam DEBUG_MODS_PER_TILE_NONZERO = (CONFIG.DEBUG_MODS_PER_TILE == 0) ? 1 : CONFIG.DEBUG_MODS_PER_TILE;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in_ready;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out_ready;
generate
if (CONFIG.USE_DEBUG == 1) begin : gen_debug_ring
genvar i;
logic [CONFIG.DEBUG_MODS_PER_TILE-1:0][15:0] id_map;
for (i = 0; i < CONFIG.DEBUG_MODS_PER_TILE; i = i+1) begin
assign id_map[i][15:0] = 16'(DEBUG_BASEID+i);
end
debug_ring_expand
#(.BUFFER_SIZE(CONFIG.DEBUG_ROUTER_BUFFER_SIZE),
.PORTS(CONFIG.DEBUG_MODS_PER_TILE))
u_debug_ring_segment
(.clk (clk),
.rst (rst_dbg),
.id_map (id_map),
.dii_in (dii_in),
.dii_in_ready (dii_in_ready),
.dii_out (dii_out),
.dii_out_ready (dii_out_ready),
.ext_in (debug_ring_in),
.ext_in_ready (debug_ring_in_ready),
.ext_out (debug_ring_out),
.ext_out_ready (debug_ring_out_ready));
end // if (USE_DEBUG)
endgenerate
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
wire [31:0] pic_ints_i [0:CONFIG.CORES_PER_TILE-1];
assign pic_ints_i[0][31:5] = 27'h0;
assign pic_ints_i[0][1:0] = 2'b00;
genvar c, m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
#(.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(CONFIG.ENABLE_DM),
.S0_RANGE_WIDTH(CONFIG.DM_RANGE_WIDTH),.S0_RANGE_MATCH(CONFIG.DM_RANGE_MATCH),
.S1_ENABLE(CONFIG.ENABLE_PGAS),
.S1_RANGE_WIDTH(CONFIG.PGAS_RANGE_WIDTH),.S1_RANGE_MATCH(CONFIG.PGAS_RANGE_MATCH),
.S2_RANGE_WIDTH(4),.S2_RANGE_MATCH(4'he),
.S3_ENABLE(CONFIG.ENABLE_BOOTROM),
.S3_RANGE_WIDTH(4),.S3_RANGE_MATCH(4'hf)
//.S4_ENABLE(CONFIG.DEBUG_DEM_UART),
//.S4_RANGE_WIDTH(28),.S4_RANGE_MATCH(28'h9000000)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
networkadapter_ct
#(.CONFIG(CONFIG),
.TILEID(ID),
.COREBASE(COREBASE))
u_na(
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
.cdc_conf (cdc_conf[2:0]),
.cdc_enable (cdc_enable),
`endif
`endif
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[SLAVE_NA]),
.wbs_rty_o (bussl_rty_o[SLAVE_NA]),
.wbs_err_o (bussl_err_o[SLAVE_NA]),
.wbs_dat_o (bussl_dat_o[SLAVE_NA]),
.irq (pic_ints_i[0][4:3]),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[SLAVE_NA]),
.wbs_cyc_i (bussl_cyc_i[SLAVE_NA]),
.wbs_dat_i (bussl_dat_i[SLAVE_NA]),
.wbs_sel_i (bussl_sel_i[SLAVE_NA]),
.wbs_stb_i (bussl_stb_i[SLAVE_NA]),
.wbs_we_i (bussl_we_i[SLAVE_NA]),
.wbs_cab_i (bussl_cab_i[SLAVE_NA]),
.wbs_cti_i (bussl_cti_i[SLAVE_NA]),
.wbs_bte_i (bussl_bte_i[SLAVE_NA]));
aes_top_192 aes_top_192_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_AES_192]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_AES_192]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_AES_192]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_AES_192]), // Templated
.wb_we_i (bussl_we_i[SLAVE_AES_192]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_AES_192]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_AES_192]), // Templated
.wb_err_o (bussl_err_o[SLAVE_AES_192])); // Templated
des3_top des3_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_DES3]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_DES3]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_DES3]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_DES3]), // Templated
.wb_we_i (bussl_we_i[SLAVE_DES3]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_DES3]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_DES3]), // Templated
.wb_err_o (bussl_err_o[SLAVE_DES3])); // Templated
sha256_top sha256_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_SHA]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_SHA]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_SHA]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_SHA]), // Templated
.wb_we_i (bussl_we_i[SLAVE_SHA]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_SHA]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_SHA]), // Templated
.wb_err_o (bussl_err_o[SLAVE_SHA])); // Templated
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the compute tile for distributed memory systems.
*
*
* The assignment of the 32 bit IRQ vector connected to core 0 is as follows:
* - Bit [1:0]: N/A
* - Bit 2: UART
* - Bit 3: NA - message passing
* - Bit 4: NA - DMA
* - Bit [31:5]: N/A
*
* The address ranges of the bus slaves are as follows:
* - Slave 0 - DM: 0x00000000-0x7fffffff
* - Slave 1 - PGAS: not used
* - Slave 2 - NA: 0xe0000000-0xefffffff
* - Slave 3 - BOOT: 0xf0000000-0xffffffff
* - Slave 4 - UART: 0x90000000-0x9000000f
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module connsubsys1
import dii_package::dii_flit;
import opensocdebug::mor1kx_trace_exec;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
parameter ID = 'x,
parameter COREBASE = 'x,
parameter DEBUG_BASEID = 'x,
parameter MEM_FILE = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH
)
(
input dii_flit [1:0] debug_ring_in,
output [1:0] debug_ring_in_ready,
output dii_flit [1:0] debug_ring_out,
input [1:0] debug_ring_out_ready,
output [31:0] wb_ext_adr_i,
output wb_ext_cyc_i,
output [31:0] wb_ext_dat_i,
output [3:0] wb_ext_sel_i,
output wb_ext_stb_i,
output wb_ext_we_i,
output wb_ext_cab_i,
output [2:0] wb_ext_cti_i,
output [1:0] wb_ext_bte_i,
input wb_ext_ack_o,
input wb_ext_rty_o,
input wb_ext_err_o,
input [31:0] wb_ext_dat_o,
input clk,
input rst_cpu, rst_sys, rst_dbg,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
import optimsoc_functions::*;
localparam NR_MASTERS = 0;
localparam NR_SLAVES = 5;
localparam SLAVE_DM = 0;
localparam SLAVE_GPS = 1;
localparam SLAVE_NA = 2;
localparam SLAVE_UART = 3;
logic wb_mem_clk_i;
logic wb_mem_rst_i;
logic [31:0] wb_mem_adr_i;
logic wb_mem_cyc_i;
logic [31:0] wb_mem_dat_i;
logic [3:0] wb_mem_sel_i;
logic wb_mem_stb_i;
logic wb_mem_we_i;
logic wb_mem_cab_i;
logic [2:0] wb_mem_cti_i;
logic [1:0] wb_mem_bte_i;
logic wb_mem_ack_o;
logic wb_mem_rty_o;
logic wb_mem_err_o;
logic [31:0] wb_mem_dat_o;
// create DI ring segment with routers
localparam DEBUG_MODS_PER_TILE_NONZERO = (CONFIG.DEBUG_MODS_PER_TILE == 0) ? 1 : CONFIG.DEBUG_MODS_PER_TILE;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in_ready;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out_ready;
generate
if (CONFIG.USE_DEBUG == 1) begin : gen_debug_ring
genvar i;
logic [CONFIG.DEBUG_MODS_PER_TILE-1:0][15:0] id_map;
for (i = 0; i < CONFIG.DEBUG_MODS_PER_TILE; i = i+1) begin
assign id_map[i][15:0] = 16'(DEBUG_BASEID+i);
end
debug_ring_expand
#(.BUFFER_SIZE(CONFIG.DEBUG_ROUTER_BUFFER_SIZE),
.PORTS(CONFIG.DEBUG_MODS_PER_TILE))
u_debug_ring_segment
(.clk (clk),
.rst (rst_dbg),
.id_map (id_map),
.dii_in (dii_in),
.dii_in_ready (dii_in_ready),
.dii_out (dii_out),
.dii_out_ready (dii_out_ready),
.ext_in (debug_ring_in),
.ext_in_ready (debug_ring_in_ready),
.ext_out (debug_ring_out),
.ext_out_ready (debug_ring_out_ready));
end // if (USE_DEBUG)
endgenerate
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
wire [31:0] pic_ints_i [0:CONFIG.CORES_PER_TILE-1];
assign pic_ints_i[0][31:5] = 27'h0;
assign pic_ints_i[0][1:0] = 2'b00;
genvar c, m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
#(.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(CONFIG.ENABLE_DM),
.S0_RANGE_WIDTH(CONFIG.DM_RANGE_WIDTH),.S0_RANGE_MATCH(CONFIG.DM_RANGE_MATCH),
.S1_ENABLE(CONFIG.ENABLE_PGAS),
.S1_RANGE_WIDTH(CONFIG.PGAS_RANGE_WIDTH),.S1_RANGE_MATCH(CONFIG.PGAS_RANGE_MATCH),
.S2_RANGE_WIDTH(4),.S2_RANGE_MATCH(4'he),
.S3_ENABLE(CONFIG.ENABLE_BOOTROM),
.S3_RANGE_WIDTH(4),.S3_RANGE_MATCH(4'hf)
//.S4_ENABLE(CONFIG.DEBUG_DEM_UART),
//.S4_RANGE_WIDTH(28),.S4_RANGE_MATCH(28'h9000000)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
networkadapter_ct
#(.CONFIG(CONFIG),
.TILEID(ID),
.COREBASE(COREBASE))
u_na(
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
.cdc_conf (cdc_conf[2:0]),
.cdc_enable (cdc_enable),
`endif
`endif
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[SLAVE_NA]),
.wbs_rty_o (bussl_rty_o[SLAVE_NA]),
.wbs_err_o (bussl_err_o[SLAVE_NA]),
.wbs_dat_o (bussl_dat_o[SLAVE_NA]),
.irq (pic_ints_i[0][4:3]),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[SLAVE_NA]),
.wbs_cyc_i (bussl_cyc_i[SLAVE_NA]),
.wbs_dat_i (bussl_dat_i[SLAVE_NA]),
.wbs_sel_i (bussl_sel_i[SLAVE_NA]),
.wbs_stb_i (bussl_stb_i[SLAVE_NA]),
.wbs_we_i (bussl_we_i[SLAVE_NA]),
.wbs_cab_i (bussl_cab_i[SLAVE_NA]),
.wbs_cti_i (bussl_cti_i[SLAVE_NA]),
.wbs_bte_i (bussl_bte_i[SLAVE_NA]));
uart_top uart_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_UART]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_UART]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_UART]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_UART]), // Templated
.wb_we_i (bussl_we_i[SLAVE_UART]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_UART]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_UART]), // Templated
.wb_err_o (bussl_err_o[SLAVE_UART])); // Templated
gps_top gps_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_GPS]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_GPS]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_GPS]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_GPS]), // Templated
.wb_we_i (bussl_we_i[SLAVE_GPS]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_GPS]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_GPS]), // Templated
.wb_err_o (bussl_err_o[SLAVE_GPS])); // Templated
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the compute tile for distributed memory systems.
*
*
* The assignment of the 32 bit IRQ vector connected to core 0 is as follows:
* - Bit [1:0]: N/A
* - Bit 2: UART
* - Bit 3: NA - message passing
* - Bit 4: NA - DMA
* - Bit [31:5]: N/A
*
* The address ranges of the bus slaves are as follows:
* - Slave 0 - DM: 0x00000000-0x7fffffff
* - Slave 1 - PGAS: not used
* - Slave 2 - NA: 0xe0000000-0xefffffff
* - Slave 3 - BOOT: 0xf0000000-0xffffffff
* - Slave 4 - UART: 0x90000000-0x9000000f
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module connsubsys2
import dii_package::dii_flit;
import opensocdebug::mor1kx_trace_exec;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
parameter ID = 'x,
parameter COREBASE = 'x,
parameter DEBUG_BASEID = 'x,
parameter MEM_FILE = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH
)
(
input dii_flit [1:0] debug_ring_in,
output [1:0] debug_ring_in_ready,
output dii_flit [1:0] debug_ring_out,
input [1:0] debug_ring_out_ready,
output [31:0] wb_ext_adr_i,
output wb_ext_cyc_i,
output [31:0] wb_ext_dat_i,
output [3:0] wb_ext_sel_i,
output wb_ext_stb_i,
output wb_ext_we_i,
output wb_ext_cab_i,
output [2:0] wb_ext_cti_i,
output [1:0] wb_ext_bte_i,
input wb_ext_ack_o,
input wb_ext_rty_o,
input wb_ext_err_o,
input [31:0] wb_ext_dat_o,
input clk,
input rst_cpu, rst_sys, rst_dbg,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
import optimsoc_functions::*;
localparam NR_MASTERS = 0;
localparam NR_SLAVES = 5;
localparam SLAVE_DM = 0;
localparam SLAVE_SPI = 1;
localparam SLAVE_NA = 2;
localparam SLAVE_ETH = 3;
logic wb_mem_clk_i;
logic wb_mem_rst_i;
logic [31:0] wb_mem_adr_i;
logic wb_mem_cyc_i;
logic [31:0] wb_mem_dat_i;
logic [3:0] wb_mem_sel_i;
logic wb_mem_stb_i;
logic wb_mem_we_i;
logic wb_mem_cab_i;
logic [2:0] wb_mem_cti_i;
logic [1:0] wb_mem_bte_i;
logic wb_mem_ack_o;
logic wb_mem_rty_o;
logic wb_mem_err_o;
logic [31:0] wb_mem_dat_o;
// create DI ring segment with routers
localparam DEBUG_MODS_PER_TILE_NONZERO = (CONFIG.DEBUG_MODS_PER_TILE == 0) ? 1 : CONFIG.DEBUG_MODS_PER_TILE;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in_ready;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out_ready;
generate
if (CONFIG.USE_DEBUG == 1) begin : gen_debug_ring
genvar i;
logic [CONFIG.DEBUG_MODS_PER_TILE-1:0][15:0] id_map;
for (i = 0; i < CONFIG.DEBUG_MODS_PER_TILE; i = i+1) begin
assign id_map[i][15:0] = 16'(DEBUG_BASEID+i);
end
debug_ring_expand
#(.BUFFER_SIZE(CONFIG.DEBUG_ROUTER_BUFFER_SIZE),
.PORTS(CONFIG.DEBUG_MODS_PER_TILE))
u_debug_ring_segment
(.clk (clk),
.rst (rst_dbg),
.id_map (id_map),
.dii_in (dii_in),
.dii_in_ready (dii_in_ready),
.dii_out (dii_out),
.dii_out_ready (dii_out_ready),
.ext_in (debug_ring_in),
.ext_in_ready (debug_ring_in_ready),
.ext_out (debug_ring_out),
.ext_out_ready (debug_ring_out_ready));
end // if (USE_DEBUG)
endgenerate
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
wire [31:0] pic_ints_i [0:CONFIG.CORES_PER_TILE-1];
assign pic_ints_i[0][31:5] = 27'h0;
assign pic_ints_i[0][1:0] = 2'b00;
genvar c, m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
#(.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(CONFIG.ENABLE_DM),
.S0_RANGE_WIDTH(CONFIG.DM_RANGE_WIDTH),.S0_RANGE_MATCH(CONFIG.DM_RANGE_MATCH),
.S1_ENABLE(CONFIG.ENABLE_PGAS),
.S1_RANGE_WIDTH(CONFIG.PGAS_RANGE_WIDTH),.S1_RANGE_MATCH(CONFIG.PGAS_RANGE_MATCH),
.S2_RANGE_WIDTH(4),.S2_RANGE_MATCH(4'he),
.S3_ENABLE(CONFIG.ENABLE_BOOTROM),
.S3_RANGE_WIDTH(4),.S3_RANGE_MATCH(4'hf)
//.S4_ENABLE(CONFIG.DEBUG_DEM_UART),
//.S4_RANGE_WIDTH(28),.S4_RANGE_MATCH(28'h9000000)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
networkadapter_ct
#(.CONFIG(CONFIG),
.TILEID(ID),
.COREBASE(COREBASE))
u_na(
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
.cdc_conf (cdc_conf[2:0]),
.cdc_enable (cdc_enable),
`endif
`endif
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[SLAVE_NA]),
.wbs_rty_o (bussl_rty_o[SLAVE_NA]),
.wbs_err_o (bussl_err_o[SLAVE_NA]),
.wbs_dat_o (bussl_dat_o[SLAVE_NA]),
.irq (pic_ints_i[0][4:3]),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[SLAVE_NA]),
.wbs_cyc_i (bussl_cyc_i[SLAVE_NA]),
.wbs_dat_i (bussl_dat_i[SLAVE_NA]),
.wbs_sel_i (bussl_sel_i[SLAVE_NA]),
.wbs_stb_i (bussl_stb_i[SLAVE_NA]),
.wbs_we_i (bussl_we_i[SLAVE_NA]),
.wbs_cab_i (bussl_cab_i[SLAVE_NA]),
.wbs_cti_i (bussl_cti_i[SLAVE_NA]),
.wbs_bte_i (bussl_bte_i[SLAVE_NA]));
uart_top uart_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_SPI]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_SPI]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_SPI]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_SPI]), // Templated
.wb_we_i (bussl_we_i[SLAVE_SPI]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_SPI]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_SPI]), // Templated
.wb_err_o (bussl_err_o[SLAVE_SPI])); // Templated
gps_top gps_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_ETH]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_ETH]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_ETH]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_ETH]), // Templated
.wb_we_i (bussl_we_i[SLAVE_ETH]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_ETH]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_ETH]), // Templated
.wb_err_o (bussl_err_o[SLAVE_ETH])); // Templated
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the compute tile for distributed memory systems.
*
*
* The assignment of the 32 bit IRQ vector connected to core 0 is as follows:
* - Bit [1:0]: N/A
* - Bit 2: UART
* - Bit 3: NA - message passing
* - Bit 4: NA - DMA
* - Bit [31:5]: N/A
*
* The address ranges of the bus slaves are as follows:
* - Slave 0 - DM: 0x00000000-0x7fffffff
* - Slave 1 - PGAS: not used
* - Slave 2 - NA: 0xe0000000-0xefffffff
* - Slave 3 - BOOT: 0xf0000000-0xffffffff
* - Slave 4 - UART: 0x90000000-0x9000000f
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module cryptosubsys1
import dii_package::dii_flit;
import opensocdebug::mor1kx_trace_exec;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
parameter ID = 'x,
parameter COREBASE = 'x,
parameter DEBUG_BASEID = 'x,
parameter MEM_FILE = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH
)
(
input dii_flit [1:0] debug_ring_in,
output [1:0] debug_ring_in_ready,
output dii_flit [1:0] debug_ring_out,
input [1:0] debug_ring_out_ready,
output [31:0] wb_ext_adr_i,
output wb_ext_cyc_i,
output [31:0] wb_ext_dat_i,
output [3:0] wb_ext_sel_i,
output wb_ext_stb_i,
output wb_ext_we_i,
output wb_ext_cab_i,
output [2:0] wb_ext_cti_i,
output [1:0] wb_ext_bte_i,
input wb_ext_ack_o,
input wb_ext_rty_o,
input wb_ext_err_o,
input [31:0] wb_ext_dat_o,
input clk,
input rst_cpu, rst_sys, rst_dbg,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
import optimsoc_functions::*;
localparam NR_MASTERS = 0;
localparam NR_SLAVES = 4;
localparam SLAVE_DES3 = 0;
localparam SLAVE_SHA = 1;
localparam SLAVE_NA = 2;
localparam SLAVE_AES_192 = 3;
logic wb_mem_clk_i;
logic wb_mem_rst_i;
logic [31:0] wb_mem_adr_i;
logic wb_mem_cyc_i;
logic [31:0] wb_mem_dat_i;
logic [3:0] wb_mem_sel_i;
logic wb_mem_stb_i;
logic wb_mem_we_i;
logic wb_mem_cab_i;
logic [2:0] wb_mem_cti_i;
logic [1:0] wb_mem_bte_i;
logic wb_mem_ack_o;
logic wb_mem_rty_o;
logic wb_mem_err_o;
logic [31:0] wb_mem_dat_o;
// create DI ring segment with routers
localparam DEBUG_MODS_PER_TILE_NONZERO = (CONFIG.DEBUG_MODS_PER_TILE == 0) ? 1 : CONFIG.DEBUG_MODS_PER_TILE;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in_ready;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out_ready;
generate
if (CONFIG.USE_DEBUG == 1) begin : gen_debug_ring
genvar i;
logic [CONFIG.DEBUG_MODS_PER_TILE-1:0][15:0] id_map;
for (i = 0; i < CONFIG.DEBUG_MODS_PER_TILE; i = i+1) begin
assign id_map[i][15:0] = 16'(DEBUG_BASEID+i);
end
debug_ring_expand
#(.BUFFER_SIZE(CONFIG.DEBUG_ROUTER_BUFFER_SIZE),
.PORTS(CONFIG.DEBUG_MODS_PER_TILE))
u_debug_ring_segment
(.clk (clk),
.rst (rst_dbg),
.id_map (id_map),
.dii_in (dii_in),
.dii_in_ready (dii_in_ready),
.dii_out (dii_out),
.dii_out_ready (dii_out_ready),
.ext_in (debug_ring_in),
.ext_in_ready (debug_ring_in_ready),
.ext_out (debug_ring_out),
.ext_out_ready (debug_ring_out_ready));
end // if (USE_DEBUG)
endgenerate
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
wire [31:0] pic_ints_i [0:CONFIG.CORES_PER_TILE-1];
assign pic_ints_i[0][31:5] = 27'h0;
assign pic_ints_i[0][1:0] = 2'b00;
genvar c, m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
#(.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(CONFIG.ENABLE_DM),
.S0_RANGE_WIDTH(CONFIG.DM_RANGE_WIDTH),.S0_RANGE_MATCH(CONFIG.DM_RANGE_MATCH),
.S1_ENABLE(CONFIG.ENABLE_PGAS),
.S1_RANGE_WIDTH(CONFIG.PGAS_RANGE_WIDTH),.S1_RANGE_MATCH(CONFIG.PGAS_RANGE_MATCH),
.S2_RANGE_WIDTH(4),.S2_RANGE_MATCH(4'he),
.S3_ENABLE(CONFIG.ENABLE_BOOTROM),
.S3_RANGE_WIDTH(4),.S3_RANGE_MATCH(4'hf)
//.S4_ENABLE(CONFIG.DEBUG_DEM_UART),
//.S4_RANGE_WIDTH(28),.S4_RANGE_MATCH(28'h9000000)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
networkadapter_ct
#(.CONFIG(CONFIG),
.TILEID(ID),
.COREBASE(COREBASE))
u_na(
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
.cdc_conf (cdc_conf[2:0]),
.cdc_enable (cdc_enable),
`endif
`endif
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[SLAVE_NA]),
.wbs_rty_o (bussl_rty_o[SLAVE_NA]),
.wbs_err_o (bussl_err_o[SLAVE_NA]),
.wbs_dat_o (bussl_dat_o[SLAVE_NA]),
.irq (pic_ints_i[0][4:3]),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[SLAVE_NA]),
.wbs_cyc_i (bussl_cyc_i[SLAVE_NA]),
.wbs_dat_i (bussl_dat_i[SLAVE_NA]),
.wbs_sel_i (bussl_sel_i[SLAVE_NA]),
.wbs_stb_i (bussl_stb_i[SLAVE_NA]),
.wbs_we_i (bussl_we_i[SLAVE_NA]),
.wbs_cab_i (bussl_cab_i[SLAVE_NA]),
.wbs_cti_i (bussl_cti_i[SLAVE_NA]),
.wbs_bte_i (bussl_bte_i[SLAVE_NA]));
aes_top_192 aes_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_AES_192]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_AES_192]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_AES_192]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_AES_192]), // Templated
.wb_we_i (bussl_we_i[SLAVE_AES_192]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_AES_192]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_AES_192]), // Templated
.wb_err_o (bussl_err_o[SLAVE_AES_192])); // Templated
des3_top des3_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_DES3]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_DES3]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_DES3]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_DES3]), // Templated
.wb_we_i (bussl_we_i[SLAVE_DES3]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_DES3]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_DES3]), // Templated
.wb_err_o (bussl_err_o[SLAVE_DES3])); // Templated
sha256_top sha256_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_SHA]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_SHA]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_SHA]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_SHA]), // Templated
.wb_we_i (bussl_we_i[SLAVE_SHA]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_SHA]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_SHA]), // Templated
.wb_err_o (bussl_err_o[SLAVE_SHA])); // Templated
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the compute tile for distributed memory systems.
*
*
* The assignment of the 32 bit IRQ vector connected to core 0 is as follows:
* - Bit [1:0]: N/A
* - Bit 2: UART
* - Bit 3: NA - message passing
* - Bit 4: NA - DMA
* - Bit [31:5]: N/A
*
* The address ranges of the bus slaves are as follows:
* - Slave 0 - DM: 0x00000000-0x7fffffff
* - Slave 1 - PGAS: not used
* - Slave 2 - NA: 0xe0000000-0xefffffff
* - Slave 3 - BOOT: 0xf0000000-0xffffffff
* - Slave 4 - UART: 0x90000000-0x9000000f
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module cryptosubsys2
import dii_package::dii_flit;
import opensocdebug::mor1kx_trace_exec;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
parameter ID = 'x,
parameter COREBASE = 'x,
parameter DEBUG_BASEID = 'x,
parameter MEM_FILE = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH
)
(
input dii_flit [1:0] debug_ring_in,
output [1:0] debug_ring_in_ready,
output dii_flit [1:0] debug_ring_out,
input [1:0] debug_ring_out_ready,
output [31:0] wb_ext_adr_i,
output wb_ext_cyc_i,
output [31:0] wb_ext_dat_i,
output [3:0] wb_ext_sel_i,
output wb_ext_stb_i,
output wb_ext_we_i,
output wb_ext_cab_i,
output [2:0] wb_ext_cti_i,
output [1:0] wb_ext_bte_i,
input wb_ext_ack_o,
input wb_ext_rty_o,
input wb_ext_err_o,
input [31:0] wb_ext_dat_o,
input clk,
input rst_cpu, rst_sys, rst_dbg,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
import optimsoc_functions::*;
localparam NR_MASTERS = 0;
localparam NR_SLAVES = 4;
localparam SLAVE_RSA = 0;
localparam SLAVE_AES128 = 1;
localparam SLAVE_NA = 2;
localparam SLAVE_MD5 = 3;
logic wb_mem_clk_i;
logic wb_mem_rst_i;
logic [31:0] wb_mem_adr_i;
logic wb_mem_cyc_i;
logic [31:0] wb_mem_dat_i;
logic [3:0] wb_mem_sel_i;
logic wb_mem_stb_i;
logic wb_mem_we_i;
logic wb_mem_cab_i;
logic [2:0] wb_mem_cti_i;
logic [1:0] wb_mem_bte_i;
logic wb_mem_ack_o;
logic wb_mem_rty_o;
logic wb_mem_err_o;
logic [31:0] wb_mem_dat_o;
// create DI ring segment with routers
localparam DEBUG_MODS_PER_TILE_NONZERO = (CONFIG.DEBUG_MODS_PER_TILE == 0) ? 1 : CONFIG.DEBUG_MODS_PER_TILE;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in_ready;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out_ready;
generate
if (CONFIG.USE_DEBUG == 1) begin : gen_debug_ring
genvar i;
logic [CONFIG.DEBUG_MODS_PER_TILE-1:0][15:0] id_map;
for (i = 0; i < CONFIG.DEBUG_MODS_PER_TILE; i = i+1) begin
assign id_map[i][15:0] = 16'(DEBUG_BASEID+i);
end
debug_ring_expand
#(.BUFFER_SIZE(CONFIG.DEBUG_ROUTER_BUFFER_SIZE),
.PORTS(CONFIG.DEBUG_MODS_PER_TILE))
u_debug_ring_segment
(.clk (clk),
.rst (rst_dbg),
.id_map (id_map),
.dii_in (dii_in),
.dii_in_ready (dii_in_ready),
.dii_out (dii_out),
.dii_out_ready (dii_out_ready),
.ext_in (debug_ring_in),
.ext_in_ready (debug_ring_in_ready),
.ext_out (debug_ring_out),
.ext_out_ready (debug_ring_out_ready));
end // if (USE_DEBUG)
endgenerate
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
wire [31:0] pic_ints_i [0:CONFIG.CORES_PER_TILE-1];
assign pic_ints_i[0][31:5] = 27'h0;
assign pic_ints_i[0][1:0] = 2'b00;
genvar c, m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
#(.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(CONFIG.ENABLE_DM),
.S0_RANGE_WIDTH(CONFIG.DM_RANGE_WIDTH),.S0_RANGE_MATCH(CONFIG.DM_RANGE_MATCH),
.S1_ENABLE(CONFIG.ENABLE_PGAS),
.S1_RANGE_WIDTH(CONFIG.PGAS_RANGE_WIDTH),.S1_RANGE_MATCH(CONFIG.PGAS_RANGE_MATCH),
.S2_RANGE_WIDTH(4),.S2_RANGE_MATCH(4'he),
.S3_ENABLE(CONFIG.ENABLE_BOOTROM),
.S3_RANGE_WIDTH(4),.S3_RANGE_MATCH(4'hf)
//.S4_ENABLE(CONFIG.DEBUG_DEM_UART),
//.S4_RANGE_WIDTH(28),.S4_RANGE_MATCH(28'h9000000)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
networkadapter_ct
#(.CONFIG(CONFIG),
.TILEID(ID),
.COREBASE(COREBASE))
u_na(
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
.cdc_conf (cdc_conf[2:0]),
.cdc_enable (cdc_enable),
`endif
`endif
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[SLAVE_NA]),
.wbs_rty_o (bussl_rty_o[SLAVE_NA]),
.wbs_err_o (bussl_err_o[SLAVE_NA]),
.wbs_dat_o (bussl_dat_o[SLAVE_NA]),
.irq (pic_ints_i[0][4:3]),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[SLAVE_NA]),
.wbs_cyc_i (bussl_cyc_i[SLAVE_NA]),
.wbs_dat_i (bussl_dat_i[SLAVE_NA]),
.wbs_sel_i (bussl_sel_i[SLAVE_NA]),
.wbs_stb_i (bussl_stb_i[SLAVE_NA]),
.wbs_we_i (bussl_we_i[SLAVE_NA]),
.wbs_cab_i (bussl_cab_i[SLAVE_NA]),
.wbs_cti_i (bussl_cti_i[SLAVE_NA]),
.wbs_bte_i (bussl_bte_i[SLAVE_NA]));
md5_top md5_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_MD5]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_MD5]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_MD5]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_MD5]), // Templated
.wb_we_i (bussl_we_i[SLAVE_MD5]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_MD5]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_MD5]), // Templated
.wb_err_o (bussl_err_o[SLAVE_MD5])); // Templated
aes_top_128 aes_top_128_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_AES128]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_AES128]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_AES128]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_AES128]), // Templated
.wb_we_i (bussl_we_i[SLAVE_AES128]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_AES128]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_AES128]), // Templated
.wb_err_o (bussl_err_o[SLAVE_AES128])); // Templated
rsa_top rsa_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_RSA]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_RSA]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_RSA]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_RSA]), // Templated
.wb_we_i (bussl_we_i[SLAVE_RSA]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_RSA]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_RSA]), // Templated
.wb_err_o (bussl_err_o[SLAVE_RSA])); // Templated
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the compute tile for distributed memory systems.
*
*
* The assignment of the 32 bit IRQ vector connected to core 0 is as follows:
* - Bit [1:0]: N/A
* - Bit 2: UART
* - Bit 3: NA - message passing
* - Bit 4: NA - DMA
* - Bit [31:5]: N/A
*
* The address ranges of the bus slaves are as follows:
* - Slave 0 - DM: 0x00000000-0x7fffffff
* - Slave 1 - PGAS: not used
* - Slave 2 - NA: 0xe0000000-0xefffffff
* - Slave 3 - BOOT: 0xf0000000-0xffffffff
* - Slave 4 - UART: 0x90000000-0x9000000f
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module compute_tile_dm_crypto2_top
import dii_package::dii_flit;
import opensocdebug::mor1kx_trace_exec;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
parameter ID = 'x,
parameter COREBASE = 'x,
parameter DEBUG_BASEID = 'x,
parameter MEM_FILE = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH
)
(
input dii_flit [1:0] debug_ring_in,
output [1:0] debug_ring_in_ready,
output dii_flit [1:0] debug_ring_out,
input [1:0] debug_ring_out_ready,
output [31:0] wb_ext_adr_i,
output wb_ext_cyc_i,
output [31:0] wb_ext_dat_i,
output [3:0] wb_ext_sel_i,
output wb_ext_stb_i,
output wb_ext_we_i,
output wb_ext_cab_i,
output [2:0] wb_ext_cti_i,
output [1:0] wb_ext_bte_i,
input wb_ext_ack_o,
input wb_ext_rty_o,
input wb_ext_err_o,
input [31:0] wb_ext_dat_o,
input clk,
input rst_cpu, rst_sys, rst_dbg,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
import optimsoc_functions::*;
localparam NR_MASTERS = 0;
localparam NR_SLAVES = 4;
localparam SLAVE_RSA = 0;
localparam SLAVE_AES128 = 1;
localparam SLAVE_NA = 2;
localparam SLAVE_MD5 = 3;
logic wb_mem_clk_i;
logic wb_mem_rst_i;
logic [31:0] wb_mem_adr_i;
logic wb_mem_cyc_i;
logic [31:0] wb_mem_dat_i;
logic [3:0] wb_mem_sel_i;
logic wb_mem_stb_i;
logic wb_mem_we_i;
logic wb_mem_cab_i;
logic [2:0] wb_mem_cti_i;
logic [1:0] wb_mem_bte_i;
logic wb_mem_ack_o;
logic wb_mem_rty_o;
logic wb_mem_err_o;
logic [31:0] wb_mem_dat_o;
// create DI ring segment with routers
localparam DEBUG_MODS_PER_TILE_NONZERO = (CONFIG.DEBUG_MODS_PER_TILE == 0) ? 1 : CONFIG.DEBUG_MODS_PER_TILE;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in_ready;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out_ready;
generate
if (CONFIG.USE_DEBUG == 1) begin : gen_debug_ring
genvar i;
logic [CONFIG.DEBUG_MODS_PER_TILE-1:0][15:0] id_map;
for (i = 0; i < CONFIG.DEBUG_MODS_PER_TILE; i = i+1) begin
assign id_map[i][15:0] = 16'(DEBUG_BASEID+i);
end
debug_ring_expand
#(.BUFFER_SIZE(CONFIG.DEBUG_ROUTER_BUFFER_SIZE),
.PORTS(CONFIG.DEBUG_MODS_PER_TILE))
u_debug_ring_segment
(.clk (clk),
.rst (rst_dbg),
.id_map (id_map),
.dii_in (dii_in),
.dii_in_ready (dii_in_ready),
.dii_out (dii_out),
.dii_out_ready (dii_out_ready),
.ext_in (debug_ring_in),
.ext_in_ready (debug_ring_in_ready),
.ext_out (debug_ring_out),
.ext_out_ready (debug_ring_out_ready));
end // if (USE_DEBUG)
endgenerate
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
wire [31:0] pic_ints_i [0:CONFIG.CORES_PER_TILE-1];
assign pic_ints_i[0][31:5] = 27'h0;
assign pic_ints_i[0][1:0] = 2'b00;
genvar c, m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
#(.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(CONFIG.ENABLE_DM),
.S0_RANGE_WIDTH(CONFIG.DM_RANGE_WIDTH),.S0_RANGE_MATCH(CONFIG.DM_RANGE_MATCH),
.S1_ENABLE(CONFIG.ENABLE_PGAS),
.S1_RANGE_WIDTH(CONFIG.PGAS_RANGE_WIDTH),.S1_RANGE_MATCH(CONFIG.PGAS_RANGE_MATCH),
.S2_RANGE_WIDTH(4),.S2_RANGE_MATCH(4'he),
.S3_ENABLE(CONFIG.ENABLE_BOOTROM),
.S3_RANGE_WIDTH(4),.S3_RANGE_MATCH(4'hf)
//.S4_ENABLE(CONFIG.DEBUG_DEM_UART),
//.S4_RANGE_WIDTH(28),.S4_RANGE_MATCH(28'h9000000)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
networkadapter_ct
#(.CONFIG(CONFIG),
.TILEID(ID),
.COREBASE(COREBASE))
u_na(
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
.cdc_conf (cdc_conf[2:0]),
.cdc_enable (cdc_enable),
`endif
`endif
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[SLAVE_NA]),
.wbs_rty_o (bussl_rty_o[SLAVE_NA]),
.wbs_err_o (bussl_err_o[SLAVE_NA]),
.wbs_dat_o (bussl_dat_o[SLAVE_NA]),
.irq (pic_ints_i[0][4:3]),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[SLAVE_NA]),
.wbs_cyc_i (bussl_cyc_i[SLAVE_NA]),
.wbs_dat_i (bussl_dat_i[SLAVE_NA]),
.wbs_sel_i (bussl_sel_i[SLAVE_NA]),
.wbs_stb_i (bussl_stb_i[SLAVE_NA]),
.wbs_we_i (bussl_we_i[SLAVE_NA]),
.wbs_cab_i (bussl_cab_i[SLAVE_NA]),
.wbs_cti_i (bussl_cti_i[SLAVE_NA]),
.wbs_bte_i (bussl_bte_i[SLAVE_NA]));
md5_top md5_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_MD5]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_MD5]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_MD5]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_MD5]), // Templated
.wb_we_i (bussl_we_i[SLAVE_MD5]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_MD5]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_MD5]), // Templated
.wb_err_o (bussl_err_o[SLAVE_MD5])); // Templated
aes_top_128 aes_top_128_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_AES128]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_AES128]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_AES128]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_AES128]), // Templated
.wb_we_i (bussl_we_i[SLAVE_AES128]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_AES128]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_AES128]), // Templated
.wb_err_o (bussl_err_o[SLAVE_AES128])); // Templated
rsa_top rsa_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_RSA]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_RSA]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_RSA]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_RSA]), // Templated
.wb_we_i (bussl_we_i[SLAVE_RSA]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_RSA]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_RSA]), // Templated
.wb_err_o (bussl_err_o[SLAVE_RSA])); // Templated
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the compute tile for distributed memory systems.
*
*
* The assignment of the 32 bit IRQ vector connected to core 0 is as follows:
* - Bit [1:0]: N/A
* - Bit 2: UART
* - Bit 3: NA - message passing
* - Bit 4: NA - DMA
* - Bit [31:5]: N/A
*
* The address ranges of the bus slaves are as follows:
* - Slave 0 - DM: 0x00000000-0x7fffffff
* - Slave 1 - PGAS: not used
* - Slave 2 - NA: 0xe0000000-0xefffffff
* - Slave 3 - BOOT: 0xf0000000-0xffffffff
* - Slave 4 - UART: 0x90000000-0x9000000f
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module compute_tile_dm_dsp_top
import dii_package::dii_flit;
import opensocdebug::mor1kx_trace_exec;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
parameter ID = 'x,
parameter COREBASE = 'x,
parameter DEBUG_BASEID = 'x,
parameter MEM_FILE = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH
)
(
input dii_flit [1:0] debug_ring_in,
output [1:0] debug_ring_in_ready,
output dii_flit [1:0] debug_ring_out,
input [1:0] debug_ring_out_ready,
output [31:0] wb_ext_adr_i,
output wb_ext_cyc_i,
output [31:0] wb_ext_dat_i,
output [3:0] wb_ext_sel_i,
output wb_ext_stb_i,
output wb_ext_we_i,
output wb_ext_cab_i,
output [2:0] wb_ext_cti_i,
output [1:0] wb_ext_bte_i,
input wb_ext_ack_o,
input wb_ext_rty_o,
input wb_ext_err_o,
input [31:0] wb_ext_dat_o,
input clk,
input rst_cpu, rst_sys, rst_dbg,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
import optimsoc_functions::*;
localparam NR_MASTERS = 0;
localparam NR_SLAVES = 5;
localparam SLAVE_DM = 0;
localparam SLAVE_PGAS = 1;
localparam SLAVE_NA = 2;
localparam SLAVE_DFT = 3;
logic wb_mem_clk_i;
logic wb_mem_rst_i;
logic [31:0] wb_mem_adr_i;
logic wb_mem_cyc_i;
logic [31:0] wb_mem_dat_i;
logic [3:0] wb_mem_sel_i;
logic wb_mem_stb_i;
logic wb_mem_we_i;
logic wb_mem_cab_i;
logic [2:0] wb_mem_cti_i;
logic [1:0] wb_mem_bte_i;
logic wb_mem_ack_o;
logic wb_mem_rty_o;
logic wb_mem_err_o;
logic [31:0] wb_mem_dat_o;
// create DI ring segment with routers
localparam DEBUG_MODS_PER_TILE_NONZERO = (CONFIG.DEBUG_MODS_PER_TILE == 0) ? 1 : CONFIG.DEBUG_MODS_PER_TILE;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in_ready;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out_ready;
generate
if (CONFIG.USE_DEBUG == 1) begin : gen_debug_ring
genvar i;
logic [CONFIG.DEBUG_MODS_PER_TILE-1:0][15:0] id_map;
for (i = 0; i < CONFIG.DEBUG_MODS_PER_TILE; i = i+1) begin
assign id_map[i][15:0] = 16'(DEBUG_BASEID+i);
end
debug_ring_expand
#(.BUFFER_SIZE(CONFIG.DEBUG_ROUTER_BUFFER_SIZE),
.PORTS(CONFIG.DEBUG_MODS_PER_TILE))
u_debug_ring_segment
(.clk (clk),
.rst (rst_dbg),
.id_map (id_map),
.dii_in (dii_in),
.dii_in_ready (dii_in_ready),
.dii_out (dii_out),
.dii_out_ready (dii_out_ready),
.ext_in (debug_ring_in),
.ext_in_ready (debug_ring_in_ready),
.ext_out (debug_ring_out),
.ext_out_ready (debug_ring_out_ready));
end // if (USE_DEBUG)
endgenerate
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
wire [31:0] pic_ints_i [0:CONFIG.CORES_PER_TILE-1];
assign pic_ints_i[0][31:5] = 27'h0;
assign pic_ints_i[0][1:0] = 2'b00;
genvar c, m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
#(.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(CONFIG.ENABLE_DM),
.S0_RANGE_WIDTH(CONFIG.DM_RANGE_WIDTH),.S0_RANGE_MATCH(CONFIG.DM_RANGE_MATCH),
.S1_ENABLE(CONFIG.ENABLE_PGAS),
.S1_RANGE_WIDTH(CONFIG.PGAS_RANGE_WIDTH),.S1_RANGE_MATCH(CONFIG.PGAS_RANGE_MATCH),
.S2_RANGE_WIDTH(4),.S2_RANGE_MATCH(4'he),
.S3_ENABLE(CONFIG.ENABLE_BOOTROM),
.S3_RANGE_WIDTH(4),.S3_RANGE_MATCH(4'hf)
//.S4_ENABLE(CONFIG.DEBUG_DEM_UART),
//.S4_RANGE_WIDTH(28),.S4_RANGE_MATCH(28'h9000000)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
networkadapter_ct
#(.CONFIG(CONFIG),
.TILEID(ID),
.COREBASE(COREBASE))
u_na(
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
.cdc_conf (cdc_conf[2:0]),
.cdc_enable (cdc_enable),
`endif
`endif
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[SLAVE_NA]),
.wbs_rty_o (bussl_rty_o[SLAVE_NA]),
.wbs_err_o (bussl_err_o[SLAVE_NA]),
.wbs_dat_o (bussl_dat_o[SLAVE_NA]),
.irq (pic_ints_i[0][4:3]),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[SLAVE_NA]),
.wbs_cyc_i (bussl_cyc_i[SLAVE_NA]),
.wbs_dat_i (bussl_dat_i[SLAVE_NA]),
.wbs_sel_i (bussl_sel_i[SLAVE_NA]),
.wbs_stb_i (bussl_stb_i[SLAVE_NA]),
.wbs_we_i (bussl_we_i[SLAVE_NA]),
.wbs_cab_i (bussl_cab_i[SLAVE_NA]),
.wbs_cti_i (bussl_cti_i[SLAVE_NA]),
.wbs_bte_i (bussl_bte_i[SLAVE_NA]));
dft_top_top dft_top_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_DFT]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_DFT]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_DFT]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_DFT]), // Templated
.wb_we_i (bussl_we_i[SLAVE_DFT]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_DFT]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_DFT]), // Templated
.wb_err_o (bussl_err_o[SLAVE_DFT])); // Templated
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the compute tile for distributed memory systems.
*
*
* The assignment of the 32 bit IRQ vector connected to core 0 is as follows:
* - Bit [1:0]: N/A
* - Bit 2: UART
* - Bit 3: NA - message passing
* - Bit 4: NA - DMA
* - Bit [31:5]: N/A
*
* The address ranges of the bus slaves are as follows:
* - Slave 0 - DM: 0x00000000-0x7fffffff
* - Slave 1 - PGAS: not used
* - Slave 2 - NA: 0xe0000000-0xefffffff
* - Slave 3 - BOOT: 0xf0000000-0xffffffff
* - Slave 4 - UART: 0x90000000-0x9000000f
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module dspsubsys2
import dii_package::dii_flit;
import opensocdebug::mor1kx_trace_exec;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
parameter ID = 'x,
parameter COREBASE = 'x,
parameter DEBUG_BASEID = 'x,
parameter MEM_FILE = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH
)
(
input dii_flit [1:0] debug_ring_in,
output [1:0] debug_ring_in_ready,
output dii_flit [1:0] debug_ring_out,
input [1:0] debug_ring_out_ready,
output [31:0] wb_ext_adr_i,
output wb_ext_cyc_i,
output [31:0] wb_ext_dat_i,
output [3:0] wb_ext_sel_i,
output wb_ext_stb_i,
output wb_ext_we_i,
output wb_ext_cab_i,
output [2:0] wb_ext_cti_i,
output [1:0] wb_ext_bte_i,
input wb_ext_ack_o,
input wb_ext_rty_o,
input wb_ext_err_o,
input [31:0] wb_ext_dat_o,
input clk,
input rst_cpu, rst_sys, rst_dbg,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
import optimsoc_functions::*;
localparam NR_MASTERS = 0;
localparam NR_SLAVES = 5;
localparam SLAVE_DM = 0;
localparam SLAVE_IIR = 1;
localparam SLAVE_NA = 2;
localparam SLAVE_FIR = 3;
logic wb_mem_clk_i;
logic wb_mem_rst_i;
logic [31:0] wb_mem_adr_i;
logic wb_mem_cyc_i;
logic [31:0] wb_mem_dat_i;
logic [3:0] wb_mem_sel_i;
logic wb_mem_stb_i;
logic wb_mem_we_i;
logic wb_mem_cab_i;
logic [2:0] wb_mem_cti_i;
logic [1:0] wb_mem_bte_i;
logic wb_mem_ack_o;
logic wb_mem_rty_o;
logic wb_mem_err_o;
logic [31:0] wb_mem_dat_o;
// create DI ring segment with routers
localparam DEBUG_MODS_PER_TILE_NONZERO = (CONFIG.DEBUG_MODS_PER_TILE == 0) ? 1 : CONFIG.DEBUG_MODS_PER_TILE;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in_ready;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out_ready;
generate
if (CONFIG.USE_DEBUG == 1) begin : gen_debug_ring
genvar i;
logic [CONFIG.DEBUG_MODS_PER_TILE-1:0][15:0] id_map;
for (i = 0; i < CONFIG.DEBUG_MODS_PER_TILE; i = i+1) begin
assign id_map[i][15:0] = 16'(DEBUG_BASEID+i);
end
debug_ring_expand
#(.BUFFER_SIZE(CONFIG.DEBUG_ROUTER_BUFFER_SIZE),
.PORTS(CONFIG.DEBUG_MODS_PER_TILE))
u_debug_ring_segment
(.clk (clk),
.rst (rst_dbg),
.id_map (id_map),
.dii_in (dii_in),
.dii_in_ready (dii_in_ready),
.dii_out (dii_out),
.dii_out_ready (dii_out_ready),
.ext_in (debug_ring_in),
.ext_in_ready (debug_ring_in_ready),
.ext_out (debug_ring_out),
.ext_out_ready (debug_ring_out_ready));
end // if (USE_DEBUG)
endgenerate
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
wire [31:0] pic_ints_i [0:CONFIG.CORES_PER_TILE-1];
assign pic_ints_i[0][31:5] = 27'h0;
assign pic_ints_i[0][1:0] = 2'b00;
genvar c, m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
#(.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(CONFIG.ENABLE_DM),
.S0_RANGE_WIDTH(CONFIG.DM_RANGE_WIDTH),.S0_RANGE_MATCH(CONFIG.DM_RANGE_MATCH),
.S1_ENABLE(CONFIG.ENABLE_PGAS),
.S1_RANGE_WIDTH(CONFIG.PGAS_RANGE_WIDTH),.S1_RANGE_MATCH(CONFIG.PGAS_RANGE_MATCH),
.S2_RANGE_WIDTH(4),.S2_RANGE_MATCH(4'he),
.S3_ENABLE(CONFIG.ENABLE_BOOTROM),
.S3_RANGE_WIDTH(4),.S3_RANGE_MATCH(4'hf)
//.S4_ENABLE(CONFIG.DEBUG_DEM_UART),
//.S4_RANGE_WIDTH(28),.S4_RANGE_MATCH(28'h9000000)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
networkadapter_ct
#(.CONFIG(CONFIG),
.TILEID(ID),
.COREBASE(COREBASE))
u_na(
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
.cdc_conf (cdc_conf[2:0]),
.cdc_enable (cdc_enable),
`endif
`endif
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[SLAVE_NA]),
.wbs_rty_o (bussl_rty_o[SLAVE_NA]),
.wbs_err_o (bussl_err_o[SLAVE_NA]),
.wbs_dat_o (bussl_dat_o[SLAVE_NA]),
.irq (pic_ints_i[0][4:3]),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[SLAVE_NA]),
.wbs_cyc_i (bussl_cyc_i[SLAVE_NA]),
.wbs_dat_i (bussl_dat_i[SLAVE_NA]),
.wbs_sel_i (bussl_sel_i[SLAVE_NA]),
.wbs_stb_i (bussl_stb_i[SLAVE_NA]),
.wbs_we_i (bussl_we_i[SLAVE_NA]),
.wbs_cab_i (bussl_cab_i[SLAVE_NA]),
.wbs_cti_i (bussl_cti_i[SLAVE_NA]),
.wbs_bte_i (bussl_bte_i[SLAVE_NA]));
fir_top fir_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_FIR]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_FIR]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_FIR]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_FIR]), // Templated
.wb_we_i (bussl_we_i[SLAVE_FIR]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_FIR]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_FIR]), // Templated
.wb_err_o (bussl_err_o[SLAVE_FIR])); // Templated
iir_top iir_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_IIR]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_IIR]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_IIR]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_IIR]), // Templated
.wb_we_i (bussl_we_i[SLAVE_IIR]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_IIR]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_IIR]), // Templated
.wb_err_o (bussl_err_o[SLAVE_IIR])); // Templated
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the compute tile for distributed memory systems.
*
*
* The assignment of the 32 bit IRQ vector connected to core 0 is as follows:
* - Bit [1:0]: N/A
* - Bit 2: UART
* - Bit 3: NA - message passing
* - Bit 4: NA - DMA
* - Bit [31:5]: N/A
*
* The address ranges of the bus slaves are as follows:
* - Slave 0 - DM: 0x00000000-0x7fffffff
* - Slave 1 - PGAS: not used
* - Slave 2 - NA: 0xe0000000-0xefffffff
* - Slave 3 - BOOT: 0xf0000000-0xffffffff
* - Slave 4 - UART: 0x90000000-0x9000000f
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module dspsubsys1
import dii_package::dii_flit;
import opensocdebug::mor1kx_trace_exec;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
parameter ID = 'x,
parameter COREBASE = 'x,
parameter DEBUG_BASEID = 'x,
parameter MEM_FILE = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH
)
(
input dii_flit [1:0] debug_ring_in,
output [1:0] debug_ring_in_ready,
output dii_flit [1:0] debug_ring_out,
input [1:0] debug_ring_out_ready,
output [31:0] wb_ext_adr_i,
output wb_ext_cyc_i,
output [31:0] wb_ext_dat_i,
output [3:0] wb_ext_sel_i,
output wb_ext_stb_i,
output wb_ext_we_i,
output wb_ext_cab_i,
output [2:0] wb_ext_cti_i,
output [1:0] wb_ext_bte_i,
input wb_ext_ack_o,
input wb_ext_rty_o,
input wb_ext_err_o,
input [31:0] wb_ext_dat_o,
input clk,
input rst_cpu, rst_sys, rst_dbg,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
import optimsoc_functions::*;
localparam NR_MASTERS = 0;
localparam NR_SLAVES = 4;
localparam SLAVE_DM = 0;
localparam SLAVE_IDFT = 1;
localparam SLAVE_NA = 2;
localparam SLAVE_DFT = 3;
logic wb_mem_clk_i;
logic wb_mem_rst_i;
logic [31:0] wb_mem_adr_i;
logic wb_mem_cyc_i;
logic [31:0] wb_mem_dat_i;
logic [3:0] wb_mem_sel_i;
logic wb_mem_stb_i;
logic wb_mem_we_i;
logic wb_mem_cab_i;
logic [2:0] wb_mem_cti_i;
logic [1:0] wb_mem_bte_i;
logic wb_mem_ack_o;
logic wb_mem_rty_o;
logic wb_mem_err_o;
logic [31:0] wb_mem_dat_o;
// create DI ring segment with routers
localparam DEBUG_MODS_PER_TILE_NONZERO = (CONFIG.DEBUG_MODS_PER_TILE == 0) ? 1 : CONFIG.DEBUG_MODS_PER_TILE;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in_ready;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out_ready;
generate
if (CONFIG.USE_DEBUG == 1) begin : gen_debug_ring
genvar i;
logic [CONFIG.DEBUG_MODS_PER_TILE-1:0][15:0] id_map;
for (i = 0; i < CONFIG.DEBUG_MODS_PER_TILE; i = i+1) begin
assign id_map[i][15:0] = 16'(DEBUG_BASEID+i);
end
debug_ring_expand
#(.BUFFER_SIZE(CONFIG.DEBUG_ROUTER_BUFFER_SIZE),
.PORTS(CONFIG.DEBUG_MODS_PER_TILE))
u_debug_ring_segment
(.clk (clk),
.rst (rst_dbg),
.id_map (id_map),
.dii_in (dii_in),
.dii_in_ready (dii_in_ready),
.dii_out (dii_out),
.dii_out_ready (dii_out_ready),
.ext_in (debug_ring_in),
.ext_in_ready (debug_ring_in_ready),
.ext_out (debug_ring_out),
.ext_out_ready (debug_ring_out_ready));
end // if (USE_DEBUG)
endgenerate
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
wire [31:0] pic_ints_i [0:CONFIG.CORES_PER_TILE-1];
assign pic_ints_i[0][31:5] = 27'h0;
assign pic_ints_i[0][1:0] = 2'b00;
genvar c, m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
#(.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(CONFIG.ENABLE_DM),
.S0_RANGE_WIDTH(CONFIG.DM_RANGE_WIDTH),.S0_RANGE_MATCH(CONFIG.DM_RANGE_MATCH),
.S1_ENABLE(CONFIG.ENABLE_PGAS),
.S1_RANGE_WIDTH(CONFIG.PGAS_RANGE_WIDTH),.S1_RANGE_MATCH(CONFIG.PGAS_RANGE_MATCH),
.S2_RANGE_WIDTH(4),.S2_RANGE_MATCH(4'he),
.S3_ENABLE(CONFIG.ENABLE_BOOTROM),
.S3_RANGE_WIDTH(4),.S3_RANGE_MATCH(4'hf)
//.S4_ENABLE(CONFIG.DEBUG_DEM_UART),
//.S4_RANGE_WIDTH(28),.S4_RANGE_MATCH(28'h9000000)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
networkadapter_ct
#(.CONFIG(CONFIG),
.TILEID(ID),
.COREBASE(COREBASE))
u_na(
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
.cdc_conf (cdc_conf[2:0]),
.cdc_enable (cdc_enable),
`endif
`endif
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[SLAVE_NA]),
.wbs_rty_o (bussl_rty_o[SLAVE_NA]),
.wbs_err_o (bussl_err_o[SLAVE_NA]),
.wbs_dat_o (bussl_dat_o[SLAVE_NA]),
.irq (pic_ints_i[0][4:3]),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[SLAVE_NA]),
.wbs_cyc_i (bussl_cyc_i[SLAVE_NA]),
.wbs_dat_i (bussl_dat_i[SLAVE_NA]),
.wbs_sel_i (bussl_sel_i[SLAVE_NA]),
.wbs_stb_i (bussl_stb_i[SLAVE_NA]),
.wbs_we_i (bussl_we_i[SLAVE_NA]),
.wbs_cab_i (bussl_cab_i[SLAVE_NA]),
.wbs_cti_i (bussl_cti_i[SLAVE_NA]),
.wbs_bte_i (bussl_bte_i[SLAVE_NA]));
dft_top_top dft_top_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_DFT]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_DFT]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_DFT]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_DFT]), // Templated
.wb_we_i (bussl_we_i[SLAVE_DFT]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_DFT]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_DFT]), // Templated
.wb_err_o (bussl_err_o[SLAVE_DFT])); // Templated
idft_top_top idft_top_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_IDFT]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_IDFT]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_IDFT]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_IDFT]), // Templated
.wb_we_i (bussl_we_i[SLAVE_IDFT]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_IDFT]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_IDFT]), // Templated
.wb_err_o (bussl_err_o[SLAVE_IDFT])); // Templated
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the compute tile for distributed memory systems.
*
*
* The assignment of the 32 bit IRQ vector connected to core 0 is as follows:
* - Bit [1:0]: N/A
* - Bit 2: UART
* - Bit 3: NA - message passing
* - Bit 4: NA - DMA
* - Bit [31:5]: N/A
*
* The address ranges of the bus slaves are as follows:
* - Slave 0 - DM: 0x00000000-0x7fffffff
* - Slave 1 - PGAS: not used
* - Slave 2 - NA: 0xe0000000-0xefffffff
* - Slave 3 - BOOT: 0xf0000000-0xffffffff
* - Slave 4 - UART: 0x90000000-0x9000000f
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module compute_tile_dm_fir_top
import dii_package::dii_flit;
import opensocdebug::mor1kx_trace_exec;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
parameter ID = 'x,
parameter COREBASE = 'x,
parameter DEBUG_BASEID = 'x,
parameter MEM_FILE = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH
)
(
input dii_flit [1:0] debug_ring_in,
output [1:0] debug_ring_in_ready,
output dii_flit [1:0] debug_ring_out,
input [1:0] debug_ring_out_ready,
output [31:0] wb_ext_adr_i,
output wb_ext_cyc_i,
output [31:0] wb_ext_dat_i,
output [3:0] wb_ext_sel_i,
output wb_ext_stb_i,
output wb_ext_we_i,
output wb_ext_cab_i,
output [2:0] wb_ext_cti_i,
output [1:0] wb_ext_bte_i,
input wb_ext_ack_o,
input wb_ext_rty_o,
input wb_ext_err_o,
input [31:0] wb_ext_dat_o,
input clk,
input rst_cpu, rst_sys, rst_dbg,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
import optimsoc_functions::*;
localparam NR_MASTERS = 0;
localparam NR_SLAVES = 5;
localparam SLAVE_DM = 0;
localparam SLAVE_PGAS = 1;
localparam SLAVE_NA = 2;
localparam SLAVE_FIR = 3;
logic wb_mem_clk_i;
logic wb_mem_rst_i;
logic [31:0] wb_mem_adr_i;
logic wb_mem_cyc_i;
logic [31:0] wb_mem_dat_i;
logic [3:0] wb_mem_sel_i;
logic wb_mem_stb_i;
logic wb_mem_we_i;
logic wb_mem_cab_i;
logic [2:0] wb_mem_cti_i;
logic [1:0] wb_mem_bte_i;
logic wb_mem_ack_o;
logic wb_mem_rty_o;
logic wb_mem_err_o;
logic [31:0] wb_mem_dat_o;
// create DI ring segment with routers
localparam DEBUG_MODS_PER_TILE_NONZERO = (CONFIG.DEBUG_MODS_PER_TILE == 0) ? 1 : CONFIG.DEBUG_MODS_PER_TILE;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in_ready;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out_ready;
generate
if (CONFIG.USE_DEBUG == 1) begin : gen_debug_ring
genvar i;
logic [CONFIG.DEBUG_MODS_PER_TILE-1:0][15:0] id_map;
for (i = 0; i < CONFIG.DEBUG_MODS_PER_TILE; i = i+1) begin
assign id_map[i][15:0] = 16'(DEBUG_BASEID+i);
end
debug_ring_expand
#(.BUFFER_SIZE(CONFIG.DEBUG_ROUTER_BUFFER_SIZE),
.PORTS(CONFIG.DEBUG_MODS_PER_TILE))
u_debug_ring_segment
(.clk (clk),
.rst (rst_dbg),
.id_map (id_map),
.dii_in (dii_in),
.dii_in_ready (dii_in_ready),
.dii_out (dii_out),
.dii_out_ready (dii_out_ready),
.ext_in (debug_ring_in),
.ext_in_ready (debug_ring_in_ready),
.ext_out (debug_ring_out),
.ext_out_ready (debug_ring_out_ready));
end // if (USE_DEBUG)
endgenerate
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
wire [31:0] pic_ints_i [0:CONFIG.CORES_PER_TILE-1];
assign pic_ints_i[0][31:5] = 27'h0;
assign pic_ints_i[0][1:0] = 2'b00;
genvar c, m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
#(.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(CONFIG.ENABLE_DM),
.S0_RANGE_WIDTH(CONFIG.DM_RANGE_WIDTH),.S0_RANGE_MATCH(CONFIG.DM_RANGE_MATCH),
.S1_ENABLE(CONFIG.ENABLE_PGAS),
.S1_RANGE_WIDTH(CONFIG.PGAS_RANGE_WIDTH),.S1_RANGE_MATCH(CONFIG.PGAS_RANGE_MATCH),
.S2_RANGE_WIDTH(4),.S2_RANGE_MATCH(4'he),
.S3_ENABLE(CONFIG.ENABLE_BOOTROM),
.S3_RANGE_WIDTH(4),.S3_RANGE_MATCH(4'hf)
//.S4_ENABLE(CONFIG.DEBUG_DEM_UART),
//.S4_RANGE_WIDTH(28),.S4_RANGE_MATCH(28'h9000000)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
networkadapter_ct
#(.CONFIG(CONFIG),
.TILEID(ID),
.COREBASE(COREBASE))
u_na(
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
.cdc_conf (cdc_conf[2:0]),
.cdc_enable (cdc_enable),
`endif
`endif
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[SLAVE_NA]),
.wbs_rty_o (bussl_rty_o[SLAVE_NA]),
.wbs_err_o (bussl_err_o[SLAVE_NA]),
.wbs_dat_o (bussl_dat_o[SLAVE_NA]),
.irq (pic_ints_i[0][4:3]),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[SLAVE_NA]),
.wbs_cyc_i (bussl_cyc_i[SLAVE_NA]),
.wbs_dat_i (bussl_dat_i[SLAVE_NA]),
.wbs_sel_i (bussl_sel_i[SLAVE_NA]),
.wbs_stb_i (bussl_stb_i[SLAVE_NA]),
.wbs_we_i (bussl_we_i[SLAVE_NA]),
.wbs_cab_i (bussl_cab_i[SLAVE_NA]),
.wbs_cti_i (bussl_cti_i[SLAVE_NA]),
.wbs_bte_i (bussl_bte_i[SLAVE_NA]));
fir_top fir_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_FIR]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_FIR]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_FIR]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_FIR]), // Templated
.wb_we_i (bussl_we_i[SLAVE_FIR]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_FIR]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_FIR]), // Templated
.wb_err_o (bussl_err_o[SLAVE_FIR])); // Templated
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the compute tile for distributed memory systems.
*
*
* The assignment of the 32 bit IRQ vector connected to core 0 is as follows:
* - Bit [1:0]: N/A
* - Bit 2: UART
* - Bit 3: NA - message passing
* - Bit 4: NA - DMA
* - Bit [31:5]: N/A
*
* The address ranges of the bus slaves are as follows:
* - Slave 0 - DM: 0x00000000-0x7fffffff
* - Slave 1 - PGAS: not used
* - Slave 2 - NA: 0xe0000000-0xefffffff
* - Slave 3 - BOOT: 0xf0000000-0xffffffff
* - Slave 4 - UART: 0x90000000-0x9000000f
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module compute_tile_dm_idft_top_top
import dii_package::dii_flit;
import opensocdebug::mor1kx_trace_exec;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
parameter ID = 'x,
parameter COREBASE = 'x,
parameter DEBUG_BASEID = 'x,
parameter MEM_FILE = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH
)
(
input dii_flit [1:0] debug_ring_in,
output [1:0] debug_ring_in_ready,
output dii_flit [1:0] debug_ring_out,
input [1:0] debug_ring_out_ready,
output [31:0] wb_ext_adr_i,
output wb_ext_cyc_i,
output [31:0] wb_ext_dat_i,
output [3:0] wb_ext_sel_i,
output wb_ext_stb_i,
output wb_ext_we_i,
output wb_ext_cab_i,
output [2:0] wb_ext_cti_i,
output [1:0] wb_ext_bte_i,
input wb_ext_ack_o,
input wb_ext_rty_o,
input wb_ext_err_o,
input [31:0] wb_ext_dat_o,
input clk,
input rst_cpu, rst_sys, rst_dbg,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
import optimsoc_functions::*;
localparam NR_MASTERS = 0;
localparam NR_SLAVES = 5;
localparam SLAVE_DM = 0;
localparam SLAVE_PGAS = 1;
localparam SLAVE_NA = 2;
localparam SLAVE_IDFT = 3;
logic wb_mem_clk_i;
logic wb_mem_rst_i;
logic [31:0] wb_mem_adr_i;
logic wb_mem_cyc_i;
logic [31:0] wb_mem_dat_i;
logic [3:0] wb_mem_sel_i;
logic wb_mem_stb_i;
logic wb_mem_we_i;
logic wb_mem_cab_i;
logic [2:0] wb_mem_cti_i;
logic [1:0] wb_mem_bte_i;
logic wb_mem_ack_o;
logic wb_mem_rty_o;
logic wb_mem_err_o;
logic [31:0] wb_mem_dat_o;
// create DI ring segment with routers
localparam DEBUG_MODS_PER_TILE_NONZERO = (CONFIG.DEBUG_MODS_PER_TILE == 0) ? 1 : CONFIG.DEBUG_MODS_PER_TILE;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in_ready;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out_ready;
generate
if (CONFIG.USE_DEBUG == 1) begin : gen_debug_ring
genvar i;
logic [CONFIG.DEBUG_MODS_PER_TILE-1:0][15:0] id_map;
for (i = 0; i < CONFIG.DEBUG_MODS_PER_TILE; i = i+1) begin
assign id_map[i][15:0] = 16'(DEBUG_BASEID+i);
end
debug_ring_expand
#(.BUFFER_SIZE(CONFIG.DEBUG_ROUTER_BUFFER_SIZE),
.PORTS(CONFIG.DEBUG_MODS_PER_TILE))
u_debug_ring_segment
(.clk (clk),
.rst (rst_dbg),
.id_map (id_map),
.dii_in (dii_in),
.dii_in_ready (dii_in_ready),
.dii_out (dii_out),
.dii_out_ready (dii_out_ready),
.ext_in (debug_ring_in),
.ext_in_ready (debug_ring_in_ready),
.ext_out (debug_ring_out),
.ext_out_ready (debug_ring_out_ready));
end // if (USE_DEBUG)
endgenerate
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
wire [31:0] pic_ints_i [0:CONFIG.CORES_PER_TILE-1];
assign pic_ints_i[0][31:5] = 27'h0;
assign pic_ints_i[0][1:0] = 2'b00;
genvar c, m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
#(.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(CONFIG.ENABLE_DM),
.S0_RANGE_WIDTH(CONFIG.DM_RANGE_WIDTH),.S0_RANGE_MATCH(CONFIG.DM_RANGE_MATCH),
.S1_ENABLE(CONFIG.ENABLE_PGAS),
.S1_RANGE_WIDTH(CONFIG.PGAS_RANGE_WIDTH),.S1_RANGE_MATCH(CONFIG.PGAS_RANGE_MATCH),
.S2_RANGE_WIDTH(4),.S2_RANGE_MATCH(4'he),
.S3_ENABLE(CONFIG.ENABLE_BOOTROM),
.S3_RANGE_WIDTH(4),.S3_RANGE_MATCH(4'hf)
//.S4_ENABLE(CONFIG.DEBUG_DEM_UART),
//.S4_RANGE_WIDTH(28),.S4_RANGE_MATCH(28'h9000000)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
networkadapter_ct
#(.CONFIG(CONFIG),
.TILEID(ID),
.COREBASE(COREBASE))
u_na(
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
.cdc_conf (cdc_conf[2:0]),
.cdc_enable (cdc_enable),
`endif
`endif
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[SLAVE_NA]),
.wbs_rty_o (bussl_rty_o[SLAVE_NA]),
.wbs_err_o (bussl_err_o[SLAVE_NA]),
.wbs_dat_o (bussl_dat_o[SLAVE_NA]),
.irq (pic_ints_i[0][4:3]),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[SLAVE_NA]),
.wbs_cyc_i (bussl_cyc_i[SLAVE_NA]),
.wbs_dat_i (bussl_dat_i[SLAVE_NA]),
.wbs_sel_i (bussl_sel_i[SLAVE_NA]),
.wbs_stb_i (bussl_stb_i[SLAVE_NA]),
.wbs_we_i (bussl_we_i[SLAVE_NA]),
.wbs_cab_i (bussl_cab_i[SLAVE_NA]),
.wbs_cti_i (bussl_cti_i[SLAVE_NA]),
.wbs_bte_i (bussl_bte_i[SLAVE_NA]));
idft_top_top idft_top_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_IDFT]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_IDFT]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_IDFT]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_IDFT]), // Templated
.wb_we_i (bussl_we_i[SLAVE_IDFT]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_IDFT]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_IDFT]), // Templated
.wb_err_o (bussl_err_o[SLAVE_IDFT])); // Templated
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the compute tile for distributed memory systems.
*
*
* The assignment of the 32 bit IRQ vector connected to core 0 is as follows:
* - Bit [1:0]: N/A
* - Bit 2: UART
* - Bit 3: NA - message passing
* - Bit 4: NA - DMA
* - Bit [31:5]: N/A
*
* The address ranges of the bus slaves are as follows:
* - Slave 0 - DM: 0x00000000-0x7fffffff
* - Slave 1 - PGAS: not used
* - Slave 2 - NA: 0xe0000000-0xefffffff
* - Slave 3 - BOOT: 0xf0000000-0xffffffff
* - Slave 4 - UART: 0x90000000-0x9000000f
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module compute_tile_dm_md5_top
import dii_package::dii_flit;
import opensocdebug::mor1kx_trace_exec;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
parameter ID = 'x,
parameter COREBASE = 'x,
parameter DEBUG_BASEID = 'x,
parameter MEM_FILE = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH
)
(
input dii_flit [1:0] debug_ring_in,
output [1:0] debug_ring_in_ready,
output dii_flit [1:0] debug_ring_out,
input [1:0] debug_ring_out_ready,
output [31:0] wb_ext_adr_i,
output wb_ext_cyc_i,
output [31:0] wb_ext_dat_i,
output [3:0] wb_ext_sel_i,
output wb_ext_stb_i,
output wb_ext_we_i,
output wb_ext_cab_i,
output [2:0] wb_ext_cti_i,
output [1:0] wb_ext_bte_i,
input wb_ext_ack_o,
input wb_ext_rty_o,
input wb_ext_err_o,
input [31:0] wb_ext_dat_o,
input clk,
input rst_cpu, rst_sys, rst_dbg,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
import optimsoc_functions::*;
localparam NR_MASTERS = 0;
localparam NR_SLAVES = 5;
localparam SLAVE_DM = 0;
localparam SLAVE_PGAS = 1;
localparam SLAVE_NA = 2;
localparam SLAVE_MD5 = 3;
logic wb_mem_clk_i;
logic wb_mem_rst_i;
logic [31:0] wb_mem_adr_i;
logic wb_mem_cyc_i;
logic [31:0] wb_mem_dat_i;
logic [3:0] wb_mem_sel_i;
logic wb_mem_stb_i;
logic wb_mem_we_i;
logic wb_mem_cab_i;
logic [2:0] wb_mem_cti_i;
logic [1:0] wb_mem_bte_i;
logic wb_mem_ack_o;
logic wb_mem_rty_o;
logic wb_mem_err_o;
logic [31:0] wb_mem_dat_o;
// create DI ring segment with routers
localparam DEBUG_MODS_PER_TILE_NONZERO = (CONFIG.DEBUG_MODS_PER_TILE == 0) ? 1 : CONFIG.DEBUG_MODS_PER_TILE;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in_ready;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out_ready;
generate
if (CONFIG.USE_DEBUG == 1) begin : gen_debug_ring
genvar i;
logic [CONFIG.DEBUG_MODS_PER_TILE-1:0][15:0] id_map;
for (i = 0; i < CONFIG.DEBUG_MODS_PER_TILE; i = i+1) begin
assign id_map[i][15:0] = 16'(DEBUG_BASEID+i);
end
debug_ring_expand
#(.BUFFER_SIZE(CONFIG.DEBUG_ROUTER_BUFFER_SIZE),
.PORTS(CONFIG.DEBUG_MODS_PER_TILE))
u_debug_ring_segment
(.clk (clk),
.rst (rst_dbg),
.id_map (id_map),
.dii_in (dii_in),
.dii_in_ready (dii_in_ready),
.dii_out (dii_out),
.dii_out_ready (dii_out_ready),
.ext_in (debug_ring_in),
.ext_in_ready (debug_ring_in_ready),
.ext_out (debug_ring_out),
.ext_out_ready (debug_ring_out_ready));
end // if (USE_DEBUG)
endgenerate
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
wire [31:0] pic_ints_i [0:CONFIG.CORES_PER_TILE-1];
assign pic_ints_i[0][31:5] = 27'h0;
assign pic_ints_i[0][1:0] = 2'b00;
genvar c, m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
#(.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(CONFIG.ENABLE_DM),
.S0_RANGE_WIDTH(CONFIG.DM_RANGE_WIDTH),.S0_RANGE_MATCH(CONFIG.DM_RANGE_MATCH),
.S1_ENABLE(CONFIG.ENABLE_PGAS),
.S1_RANGE_WIDTH(CONFIG.PGAS_RANGE_WIDTH),.S1_RANGE_MATCH(CONFIG.PGAS_RANGE_MATCH),
.S2_RANGE_WIDTH(4),.S2_RANGE_MATCH(4'he),
.S3_ENABLE(CONFIG.ENABLE_BOOTROM),
.S3_RANGE_WIDTH(4),.S3_RANGE_MATCH(4'hf)
//.S4_ENABLE(CONFIG.DEBUG_DEM_UART),
//.S4_RANGE_WIDTH(28),.S4_RANGE_MATCH(28'h9000000)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
networkadapter_ct
#(.CONFIG(CONFIG),
.TILEID(ID),
.COREBASE(COREBASE))
u_na(
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
.cdc_conf (cdc_conf[2:0]),
.cdc_enable (cdc_enable),
`endif
`endif
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[SLAVE_NA]),
.wbs_rty_o (bussl_rty_o[SLAVE_NA]),
.wbs_err_o (bussl_err_o[SLAVE_NA]),
.wbs_dat_o (bussl_dat_o[SLAVE_NA]),
.irq (pic_ints_i[0][4:3]),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[SLAVE_NA]),
.wbs_cyc_i (bussl_cyc_i[SLAVE_NA]),
.wbs_dat_i (bussl_dat_i[SLAVE_NA]),
.wbs_sel_i (bussl_sel_i[SLAVE_NA]),
.wbs_stb_i (bussl_stb_i[SLAVE_NA]),
.wbs_we_i (bussl_we_i[SLAVE_NA]),
.wbs_cab_i (bussl_cab_i[SLAVE_NA]),
.wbs_cti_i (bussl_cti_i[SLAVE_NA]),
.wbs_bte_i (bussl_bte_i[SLAVE_NA]));
md5_top md5_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_MD5]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_MD5]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_MD5]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_MD5]), // Templated
.wb_we_i (bussl_we_i[SLAVE_MD5]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_MD5]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_MD5]), // Templated
.wb_err_o (bussl_err_o[SLAVE_MD5])); // Templated
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the compute tile for distributed memory systems.
*
*
* The assignment of the 32 bit IRQ vector connected to core 0 is as follows:
* - Bit [1:0]: N/A
* - Bit 2: UART
* - Bit 3: NA - message passing
* - Bit 4: NA - DMA
* - Bit [31:5]: N/A
*
* The address ranges of the bus slaves are as follows:
* - Slave 0 - DM: 0x00000000-0x7fffffff
* - Slave 1 - PGAS: not used
* - Slave 2 - NA: 0xe0000000-0xefffffff
* - Slave 3 - BOOT: 0xf0000000-0xffffffff
* - Slave 4 - UART: 0x90000000-0x9000000f
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module compute_tile_dm_ram_wb_01
import dii_package::dii_flit;
import opensocdebug::mor1kx_trace_exec;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
parameter ID = 'x,
parameter COREBASE = 'x,
parameter DEBUG_BASEID = 'x,
parameter MEM_FILE = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH
)
(
input dii_flit [1:0] debug_ring_in,
output [1:0] debug_ring_in_ready,
output dii_flit [1:0] debug_ring_out,
input [1:0] debug_ring_out_ready,
output [31:0] wb_ext_adr_i,
output wb_ext_cyc_i,
output [31:0] wb_ext_dat_i,
output [3:0] wb_ext_sel_i,
output wb_ext_stb_i,
output wb_ext_we_i,
output wb_ext_cab_i,
output [2:0] wb_ext_cti_i,
output [1:0] wb_ext_bte_i,
input wb_ext_ack_o,
input wb_ext_rty_o,
input wb_ext_err_o,
input [31:0] wb_ext_dat_o,
input clk,
input rst_cpu, rst_sys, rst_dbg,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
import optimsoc_functions::*;
localparam NR_MASTERS = 0;
localparam NR_SLAVES = 5;
localparam SLAVE_DM = 0;
localparam SLAVE_PGAS = 1;
localparam SLAVE_NA = 2;
localparam SLAVE_RAM_1 = 3;
logic wb_mem_clk_i;
logic wb_mem_rst_i;
logic [31:0] wb_mem_adr_i;
logic wb_mem_cyc_i;
logic [31:0] wb_mem_dat_i;
logic [3:0] wb_mem_sel_i;
logic wb_mem_stb_i;
logic wb_mem_we_i;
logic wb_mem_cab_i;
logic [2:0] wb_mem_cti_i;
logic [1:0] wb_mem_bte_i;
logic wb_mem_ack_o;
logic wb_mem_rty_o;
logic wb_mem_err_o;
logic [31:0] wb_mem_dat_o;
// create DI ring segment with routers
localparam DEBUG_MODS_PER_TILE_NONZERO = (CONFIG.DEBUG_MODS_PER_TILE == 0) ? 1 : CONFIG.DEBUG_MODS_PER_TILE;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in_ready;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out_ready;
generate
if (CONFIG.USE_DEBUG == 1) begin : gen_debug_ring
genvar i;
logic [CONFIG.DEBUG_MODS_PER_TILE-1:0][15:0] id_map;
for (i = 0; i < CONFIG.DEBUG_MODS_PER_TILE; i = i+1) begin
assign id_map[i][15:0] = 16'(DEBUG_BASEID+i);
end
debug_ring_expand
#(.BUFFER_SIZE(CONFIG.DEBUG_ROUTER_BUFFER_SIZE),
.PORTS(CONFIG.DEBUG_MODS_PER_TILE))
u_debug_ring_segment
(.clk (clk),
.rst (rst_dbg),
.id_map (id_map),
.dii_in (dii_in),
.dii_in_ready (dii_in_ready),
.dii_out (dii_out),
.dii_out_ready (dii_out_ready),
.ext_in (debug_ring_in),
.ext_in_ready (debug_ring_in_ready),
.ext_out (debug_ring_out),
.ext_out_ready (debug_ring_out_ready));
end // if (USE_DEBUG)
endgenerate
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
wire [31:0] pic_ints_i [0:CONFIG.CORES_PER_TILE-1];
assign pic_ints_i[0][31:5] = 27'h0;
assign pic_ints_i[0][1:0] = 2'b00;
genvar c, m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
#(.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(CONFIG.ENABLE_DM),
.S0_RANGE_WIDTH(CONFIG.DM_RANGE_WIDTH),.S0_RANGE_MATCH(CONFIG.DM_RANGE_MATCH),
.S1_ENABLE(CONFIG.ENABLE_PGAS),
.S1_RANGE_WIDTH(CONFIG.PGAS_RANGE_WIDTH),.S1_RANGE_MATCH(CONFIG.PGAS_RANGE_MATCH),
.S2_RANGE_WIDTH(4),.S2_RANGE_MATCH(4'he),
.S3_ENABLE(CONFIG.ENABLE_BOOTROM),
.S3_RANGE_WIDTH(4),.S3_RANGE_MATCH(4'hf)
//.S4_ENABLE(CONFIG.DEBUG_DEM_UART),
//.S4_RANGE_WIDTH(28),.S4_RANGE_MATCH(28'h9000000)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
networkadapter_ct
#(.CONFIG(CONFIG),
.TILEID(ID),
.COREBASE(COREBASE))
u_na(
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
.cdc_conf (cdc_conf[2:0]),
.cdc_enable (cdc_enable),
`endif
`endif
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[SLAVE_NA]),
.wbs_rty_o (bussl_rty_o[SLAVE_NA]),
.wbs_err_o (bussl_err_o[SLAVE_NA]),
.wbs_dat_o (bussl_dat_o[SLAVE_NA]),
.irq (pic_ints_i[0][4:3]),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[SLAVE_NA]),
.wbs_cyc_i (bussl_cyc_i[SLAVE_NA]),
.wbs_dat_i (bussl_dat_i[SLAVE_NA]),
.wbs_sel_i (bussl_sel_i[SLAVE_NA]),
.wbs_stb_i (bussl_stb_i[SLAVE_NA]),
.wbs_we_i (bussl_we_i[SLAVE_NA]),
.wbs_cab_i (bussl_cab_i[SLAVE_NA]),
.wbs_cti_i (bussl_cti_i[SLAVE_NA]),
.wbs_bte_i (bussl_bte_i[SLAVE_NA]));
ram_wb_01 ram_wb_01_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_RAM_1]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_RAM_1]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_RAM_1]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_RAM_1]), // Templated
.wb_we_i (bussl_we_i[SLAVE_RAM_1]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_RAM_1]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_RAM_1]), // Templated
.wb_err_o (bussl_err_o[SLAVE_RAM_1])); // Templated
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the compute tile for distributed memory systems.
*
*
* The assignment of the 32 bit IRQ vector connected to core 0 is as follows:
* - Bit [1:0]: N/A
* - Bit 2: UART
* - Bit 3: NA - message passing
* - Bit 4: NA - DMA
* - Bit [31:5]: N/A
*
* The address ranges of the bus slaves are as follows:
* - Slave 0 - DM: 0x00000000-0x7fffffff
* - Slave 1 - PGAS: not used
* - Slave 2 - NA: 0xe0000000-0xefffffff
* - Slave 3 - BOOT: 0xf0000000-0xffffffff
* - Slave 4 - UART: 0x90000000-0x9000000f
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module compute_tile_dm_ram_wb_02
import dii_package::dii_flit;
import opensocdebug::mor1kx_trace_exec;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
parameter ID = 'x,
parameter COREBASE = 'x,
parameter DEBUG_BASEID = 'x,
parameter MEM_FILE = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH
)
(
input dii_flit [1:0] debug_ring_in,
output [1:0] debug_ring_in_ready,
output dii_flit [1:0] debug_ring_out,
input [1:0] debug_ring_out_ready,
output [31:0] wb_ext_adr_i,
output wb_ext_cyc_i,
output [31:0] wb_ext_dat_i,
output [3:0] wb_ext_sel_i,
output wb_ext_stb_i,
output wb_ext_we_i,
output wb_ext_cab_i,
output [2:0] wb_ext_cti_i,
output [1:0] wb_ext_bte_i,
input wb_ext_ack_o,
input wb_ext_rty_o,
input wb_ext_err_o,
input [31:0] wb_ext_dat_o,
input clk,
input rst_cpu, rst_sys, rst_dbg,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
import optimsoc_functions::*;
localparam NR_MASTERS = 0;
localparam NR_SLAVES = 5;
localparam SLAVE_DM = 0;
localparam SLAVE_PGAS = 1;
localparam SLAVE_NA = 2;
localparam SLAVE_RAM_2 = 3;
logic wb_mem_clk_i;
logic wb_mem_rst_i;
logic [31:0] wb_mem_adr_i;
logic wb_mem_cyc_i;
logic [31:0] wb_mem_dat_i;
logic [3:0] wb_mem_sel_i;
logic wb_mem_stb_i;
logic wb_mem_we_i;
logic wb_mem_cab_i;
logic [2:0] wb_mem_cti_i;
logic [1:0] wb_mem_bte_i;
logic wb_mem_ack_o;
logic wb_mem_rty_o;
logic wb_mem_err_o;
logic [31:0] wb_mem_dat_o;
// create DI ring segment with routers
localparam DEBUG_MODS_PER_TILE_NONZERO = (CONFIG.DEBUG_MODS_PER_TILE == 0) ? 1 : CONFIG.DEBUG_MODS_PER_TILE;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in_ready;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out_ready;
generate
if (CONFIG.USE_DEBUG == 1) begin : gen_debug_ring
genvar i;
logic [CONFIG.DEBUG_MODS_PER_TILE-1:0][15:0] id_map;
for (i = 0; i < CONFIG.DEBUG_MODS_PER_TILE; i = i+1) begin
assign id_map[i][15:0] = 16'(DEBUG_BASEID+i);
end
debug_ring_expand
#(.BUFFER_SIZE(CONFIG.DEBUG_ROUTER_BUFFER_SIZE),
.PORTS(CONFIG.DEBUG_MODS_PER_TILE))
u_debug_ring_segment
(.clk (clk),
.rst (rst_dbg),
.id_map (id_map),
.dii_in (dii_in),
.dii_in_ready (dii_in_ready),
.dii_out (dii_out),
.dii_out_ready (dii_out_ready),
.ext_in (debug_ring_in),
.ext_in_ready (debug_ring_in_ready),
.ext_out (debug_ring_out),
.ext_out_ready (debug_ring_out_ready));
end // if (USE_DEBUG)
endgenerate
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
wire [31:0] pic_ints_i [0:CONFIG.CORES_PER_TILE-1];
assign pic_ints_i[0][31:5] = 27'h0;
assign pic_ints_i[0][1:0] = 2'b00;
genvar c, m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
#(.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(CONFIG.ENABLE_DM),
.S0_RANGE_WIDTH(CONFIG.DM_RANGE_WIDTH),.S0_RANGE_MATCH(CONFIG.DM_RANGE_MATCH),
.S1_ENABLE(CONFIG.ENABLE_PGAS),
.S1_RANGE_WIDTH(CONFIG.PGAS_RANGE_WIDTH),.S1_RANGE_MATCH(CONFIG.PGAS_RANGE_MATCH),
.S2_RANGE_WIDTH(4),.S2_RANGE_MATCH(4'he),
.S3_ENABLE(CONFIG.ENABLE_BOOTROM),
.S3_RANGE_WIDTH(4),.S3_RANGE_MATCH(4'hf)
//.S4_ENABLE(CONFIG.DEBUG_DEM_UART),
//.S4_RANGE_WIDTH(28),.S4_RANGE_MATCH(28'h9000000)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
networkadapter_ct
#(.CONFIG(CONFIG),
.TILEID(ID),
.COREBASE(COREBASE))
u_na(
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
.cdc_conf (cdc_conf[2:0]),
.cdc_enable (cdc_enable),
`endif
`endif
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[SLAVE_NA]),
.wbs_rty_o (bussl_rty_o[SLAVE_NA]),
.wbs_err_o (bussl_err_o[SLAVE_NA]),
.wbs_dat_o (bussl_dat_o[SLAVE_NA]),
.irq (pic_ints_i[0][4:3]),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[SLAVE_NA]),
.wbs_cyc_i (bussl_cyc_i[SLAVE_NA]),
.wbs_dat_i (bussl_dat_i[SLAVE_NA]),
.wbs_sel_i (bussl_sel_i[SLAVE_NA]),
.wbs_stb_i (bussl_stb_i[SLAVE_NA]),
.wbs_we_i (bussl_we_i[SLAVE_NA]),
.wbs_cab_i (bussl_cab_i[SLAVE_NA]),
.wbs_cti_i (bussl_cti_i[SLAVE_NA]),
.wbs_bte_i (bussl_bte_i[SLAVE_NA]));
ram_wb_02 ram_wb_02_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_RAM_2]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_RAM_2]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_RAM_2]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_RAM_2]), // Templated
.wb_we_i (bussl_we_i[SLAVE_RAM_2]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_RAM_2]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_RAM_2]), // Templated
.wb_err_o (bussl_err_o[SLAVE_RAM_2])); // Templated
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the compute tile for distributed memory systems.
*
*
* The assignment of the 32 bit IRQ vector connected to core 0 is as follows:
* - Bit [1:0]: N/A
* - Bit 2: UART
* - Bit 3: NA - message passing
* - Bit 4: NA - DMA
* - Bit [31:5]: N/A
*
* The address ranges of the bus slaves are as follows:
* - Slave 0 - DM: 0x00000000-0x7fffffff
* - Slave 1 - PGAS: not used
* - Slave 2 - NA: 0xe0000000-0xefffffff
* - Slave 3 - BOOT: 0xf0000000-0xffffffff
* - Slave 4 - UART: 0x90000000-0x9000000f
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module compute_tile_dm_sha256_top
import dii_package::dii_flit;
import opensocdebug::mor1kx_trace_exec;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
parameter ID = 'x,
parameter COREBASE = 'x,
parameter DEBUG_BASEID = 'x,
parameter MEM_FILE = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH
)
(
input dii_flit [1:0] debug_ring_in,
output [1:0] debug_ring_in_ready,
output dii_flit [1:0] debug_ring_out,
input [1:0] debug_ring_out_ready,
output [31:0] wb_ext_adr_i,
output wb_ext_cyc_i,
output [31:0] wb_ext_dat_i,
output [3:0] wb_ext_sel_i,
output wb_ext_stb_i,
output wb_ext_we_i,
output wb_ext_cab_i,
output [2:0] wb_ext_cti_i,
output [1:0] wb_ext_bte_i,
input wb_ext_ack_o,
input wb_ext_rty_o,
input wb_ext_err_o,
input [31:0] wb_ext_dat_o,
input clk,
input rst_cpu, rst_sys, rst_dbg,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
import optimsoc_functions::*;
localparam NR_MASTERS = 0;
localparam NR_SLAVES = 5;
localparam SLAVE_DM = 0;
localparam SLAVE_PGAS = 1;
localparam SLAVE_NA = 2;
localparam SLAVE_SHA256 = 3;
logic wb_mem_clk_i;
logic wb_mem_rst_i;
logic [31:0] wb_mem_adr_i;
logic wb_mem_cyc_i;
logic [31:0] wb_mem_dat_i;
logic [3:0] wb_mem_sel_i;
logic wb_mem_stb_i;
logic wb_mem_we_i;
logic wb_mem_cab_i;
logic [2:0] wb_mem_cti_i;
logic [1:0] wb_mem_bte_i;
logic wb_mem_ack_o;
logic wb_mem_rty_o;
logic wb_mem_err_o;
logic [31:0] wb_mem_dat_o;
// create DI ring segment with routers
localparam DEBUG_MODS_PER_TILE_NONZERO = (CONFIG.DEBUG_MODS_PER_TILE == 0) ? 1 : CONFIG.DEBUG_MODS_PER_TILE;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in_ready;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out_ready;
generate
if (CONFIG.USE_DEBUG == 1) begin : gen_debug_ring
genvar i;
logic [CONFIG.DEBUG_MODS_PER_TILE-1:0][15:0] id_map;
for (i = 0; i < CONFIG.DEBUG_MODS_PER_TILE; i = i+1) begin
assign id_map[i][15:0] = 16'(DEBUG_BASEID+i);
end
debug_ring_expand
#(.BUFFER_SIZE(CONFIG.DEBUG_ROUTER_BUFFER_SIZE),
.PORTS(CONFIG.DEBUG_MODS_PER_TILE))
u_debug_ring_segment
(.clk (clk),
.rst (rst_dbg),
.id_map (id_map),
.dii_in (dii_in),
.dii_in_ready (dii_in_ready),
.dii_out (dii_out),
.dii_out_ready (dii_out_ready),
.ext_in (debug_ring_in),
.ext_in_ready (debug_ring_in_ready),
.ext_out (debug_ring_out),
.ext_out_ready (debug_ring_out_ready));
end // if (USE_DEBUG)
endgenerate
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
wire [31:0] pic_ints_i [0:CONFIG.CORES_PER_TILE-1];
assign pic_ints_i[0][31:5] = 27'h0;
assign pic_ints_i[0][1:0] = 2'b00;
genvar c, m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
#(.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(CONFIG.ENABLE_DM),
.S0_RANGE_WIDTH(CONFIG.DM_RANGE_WIDTH),.S0_RANGE_MATCH(CONFIG.DM_RANGE_MATCH),
.S1_ENABLE(CONFIG.ENABLE_PGAS),
.S1_RANGE_WIDTH(CONFIG.PGAS_RANGE_WIDTH),.S1_RANGE_MATCH(CONFIG.PGAS_RANGE_MATCH),
.S2_RANGE_WIDTH(4),.S2_RANGE_MATCH(4'he),
.S3_ENABLE(CONFIG.ENABLE_BOOTROM),
.S3_RANGE_WIDTH(4),.S3_RANGE_MATCH(4'hf)
//.S4_ENABLE(CONFIG.DEBUG_DEM_UART),
//.S4_RANGE_WIDTH(28),.S4_RANGE_MATCH(28'h9000000)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
networkadapter_ct
#(.CONFIG(CONFIG),
.TILEID(ID),
.COREBASE(COREBASE))
u_na(
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
.cdc_conf (cdc_conf[2:0]),
.cdc_enable (cdc_enable),
`endif
`endif
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[SLAVE_NA]),
.wbs_rty_o (bussl_rty_o[SLAVE_NA]),
.wbs_err_o (bussl_err_o[SLAVE_NA]),
.wbs_dat_o (bussl_dat_o[SLAVE_NA]),
.irq (pic_ints_i[0][4:3]),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[SLAVE_NA]),
.wbs_cyc_i (bussl_cyc_i[SLAVE_NA]),
.wbs_dat_i (bussl_dat_i[SLAVE_NA]),
.wbs_sel_i (bussl_sel_i[SLAVE_NA]),
.wbs_stb_i (bussl_stb_i[SLAVE_NA]),
.wbs_we_i (bussl_we_i[SLAVE_NA]),
.wbs_cab_i (bussl_cab_i[SLAVE_NA]),
.wbs_cti_i (bussl_cti_i[SLAVE_NA]),
.wbs_bte_i (bussl_bte_i[SLAVE_NA]));
sha256_top sha256_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_SHA256]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_SHA256]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_SHA256]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_SHA256]), // Templated
.wb_we_i (bussl_we_i[SLAVE_SHA256]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_SHA256]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_SHA256]), // Templated
.wb_err_o (bussl_err_o[SLAVE_SHA256])); // Templated
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the compute tile for distributed memory systems.
*
*
* The assignment of the 32 bit IRQ vector connected to core 0 is as follows:
* - Bit [1:0]: N/A
* - Bit 2: UART
* - Bit 3: NA - message passing
* - Bit 4: NA - DMA
* - Bit [31:5]: N/A
*
* The address ranges of the bus slaves are as follows:
* - Slave 0 - DM: 0x00000000-0x7fffffff
* - Slave 1 - PGAS: not used
* - Slave 2 - NA: 0xe0000000-0xefffffff
* - Slave 3 - BOOT: 0xf0000000-0xffffffff
* - Slave 4 - UART: 0x90000000-0x9000000f
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module compute_tile_dm_con1_top
import dii_package::dii_flit;
import opensocdebug::mor1kx_trace_exec;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
parameter ID = 'x,
parameter COREBASE = 'x,
parameter DEBUG_BASEID = 'x,
parameter MEM_FILE = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH
)
(
input dii_flit [1:0] debug_ring_in,
output [1:0] debug_ring_in_ready,
output dii_flit [1:0] debug_ring_out,
input [1:0] debug_ring_out_ready,
output [31:0] wb_ext_adr_i,
output wb_ext_cyc_i,
output [31:0] wb_ext_dat_i,
output [3:0] wb_ext_sel_i,
output wb_ext_stb_i,
output wb_ext_we_i,
output wb_ext_cab_i,
output [2:0] wb_ext_cti_i,
output [1:0] wb_ext_bte_i,
input wb_ext_ack_o,
input wb_ext_rty_o,
input wb_ext_err_o,
input [31:0] wb_ext_dat_o,
input clk,
input rst_cpu, rst_sys, rst_dbg,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
import optimsoc_functions::*;
localparam NR_MASTERS = 0;
localparam NR_SLAVES = 5;
localparam SLAVE_DM = 0;
localparam SLAVE_PGAS = 1;
localparam SLAVE_NA = 2;
localparam SLAVE_UART = 3;
logic wb_mem_clk_i;
logic wb_mem_rst_i;
logic [31:0] wb_mem_adr_i;
logic wb_mem_cyc_i;
logic [31:0] wb_mem_dat_i;
logic [3:0] wb_mem_sel_i;
logic wb_mem_stb_i;
logic wb_mem_we_i;
logic wb_mem_cab_i;
logic [2:0] wb_mem_cti_i;
logic [1:0] wb_mem_bte_i;
logic wb_mem_ack_o;
logic wb_mem_rty_o;
logic wb_mem_err_o;
logic [31:0] wb_mem_dat_o;
// create DI ring segment with routers
localparam DEBUG_MODS_PER_TILE_NONZERO = (CONFIG.DEBUG_MODS_PER_TILE == 0) ? 1 : CONFIG.DEBUG_MODS_PER_TILE;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in_ready;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out_ready;
generate
if (CONFIG.USE_DEBUG == 1) begin : gen_debug_ring
genvar i;
logic [CONFIG.DEBUG_MODS_PER_TILE-1:0][15:0] id_map;
for (i = 0; i < CONFIG.DEBUG_MODS_PER_TILE; i = i+1) begin
assign id_map[i][15:0] = 16'(DEBUG_BASEID+i);
end
debug_ring_expand
#(.BUFFER_SIZE(CONFIG.DEBUG_ROUTER_BUFFER_SIZE),
.PORTS(CONFIG.DEBUG_MODS_PER_TILE))
u_debug_ring_segment
(.clk (clk),
.rst (rst_dbg),
.id_map (id_map),
.dii_in (dii_in),
.dii_in_ready (dii_in_ready),
.dii_out (dii_out),
.dii_out_ready (dii_out_ready),
.ext_in (debug_ring_in),
.ext_in_ready (debug_ring_in_ready),
.ext_out (debug_ring_out),
.ext_out_ready (debug_ring_out_ready));
end // if (USE_DEBUG)
endgenerate
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
wire [31:0] pic_ints_i [0:CONFIG.CORES_PER_TILE-1];
assign pic_ints_i[0][31:5] = 27'h0;
assign pic_ints_i[0][1:0] = 2'b00;
genvar c, m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
#(.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(CONFIG.ENABLE_DM),
.S0_RANGE_WIDTH(CONFIG.DM_RANGE_WIDTH),.S0_RANGE_MATCH(CONFIG.DM_RANGE_MATCH),
.S1_ENABLE(CONFIG.ENABLE_PGAS),
.S1_RANGE_WIDTH(CONFIG.PGAS_RANGE_WIDTH),.S1_RANGE_MATCH(CONFIG.PGAS_RANGE_MATCH),
.S2_RANGE_WIDTH(4),.S2_RANGE_MATCH(4'he),
.S3_ENABLE(CONFIG.ENABLE_BOOTROM),
.S3_RANGE_WIDTH(4),.S3_RANGE_MATCH(4'hf)
//.S4_ENABLE(CONFIG.DEBUG_DEM_UART),
//.S4_RANGE_WIDTH(28),.S4_RANGE_MATCH(28'h9000000)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
networkadapter_ct
#(.CONFIG(CONFIG),
.TILEID(ID),
.COREBASE(COREBASE))
u_na(
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
.cdc_conf (cdc_conf[2:0]),
.cdc_enable (cdc_enable),
`endif
`endif
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[SLAVE_NA]),
.wbs_rty_o (bussl_rty_o[SLAVE_NA]),
.wbs_err_o (bussl_err_o[SLAVE_NA]),
.wbs_dat_o (bussl_dat_o[SLAVE_NA]),
.irq (pic_ints_i[0][4:3]),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[SLAVE_NA]),
.wbs_cyc_i (bussl_cyc_i[SLAVE_NA]),
.wbs_dat_i (bussl_dat_i[SLAVE_NA]),
.wbs_sel_i (bussl_sel_i[SLAVE_NA]),
.wbs_stb_i (bussl_stb_i[SLAVE_NA]),
.wbs_we_i (bussl_we_i[SLAVE_NA]),
.wbs_cab_i (bussl_cab_i[SLAVE_NA]),
.wbs_cti_i (bussl_cti_i[SLAVE_NA]),
.wbs_bte_i (bussl_bte_i[SLAVE_NA]));
uart_top uart_top_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_UART]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_UART]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_UART]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_UART]), // Templated
.wb_we_i (bussl_we_i[SLAVE_UART]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_UART]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_UART]), // Templated
.wb_err_o (bussl_err_o[SLAVE_UART])); // Templated
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the compute tile for distributed memory systems.
*
*
* The assignment of the 32 bit IRQ vector connected to core 0 is as follows:
* - Bit [1:0]: N/A
* - Bit 2: UART
* - Bit 3: NA - message passing
* - Bit 4: NA - DMA
* - Bit [31:5]: N/A
*
* The address ranges of the bus slaves are as follows:
* - Slave 0 - DM: 0x00000000-0x7fffffff
* - Slave 1 - PGAS: not used
* - Slave 2 - NA: 0xe0000000-0xefffffff
* - Slave 3 - BOOT: 0xf0000000-0xffffffff
* - Slave 4 - UART: 0x90000000-0x9000000f
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module compute_tile_dm_rv32
import dii_package::dii_flit;
import opensocdebug::mor1kx_trace_exec;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
parameter ID = 'x,
parameter COREBASE = 'x,
parameter DEBUG_BASEID = 'x,
parameter MEM_FILE = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH
)
(
input dii_flit [1:0] debug_ring_in,
output [1:0] debug_ring_in_ready,
output dii_flit [1:0] debug_ring_out,
input [1:0] debug_ring_out_ready,
output [31:0] wb_ext_adr_i,
output wb_ext_cyc_i,
output [31:0] wb_ext_dat_i,
output [3:0] wb_ext_sel_i,
output wb_ext_stb_i,
output wb_ext_we_i,
output wb_ext_cab_i,
output [2:0] wb_ext_cti_i,
output [1:0] wb_ext_bte_i,
input wb_ext_ack_o,
input wb_ext_rty_o,
input wb_ext_err_o,
input [31:0] wb_ext_dat_o,
input clk,
input rst_cpu, rst_sys, rst_dbg,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
import optimsoc_functions::*;
localparam NR_MASTERS = 1;
localparam NR_SLAVES = 5;
localparam SLAVE_DM = 0;
localparam SLAVE_PGAS = 1;
localparam SLAVE_NA = 2;
localparam SLAVE_BOOT = 3;
//localparam SLAVE_UART = 4;
mor1kx_trace_exec [CONFIG.CORES_PER_TILE-1:0] trace;
logic wb_mem_clk_i;
logic wb_mem_rst_i;
logic [31:0] wb_mem_adr_i;
logic wb_mem_cyc_i;
logic [31:0] wb_mem_dat_i;
logic [3:0] wb_mem_sel_i;
logic wb_mem_stb_i;
logic wb_mem_we_i;
logic wb_mem_cab_i;
logic [2:0] wb_mem_cti_i;
logic [1:0] wb_mem_bte_i;
logic wb_mem_ack_o;
logic wb_mem_rty_o;
logic wb_mem_err_o;
logic [31:0] wb_mem_dat_o;
// create DI ring segment with routers
localparam DEBUG_MODS_PER_TILE_NONZERO = (CONFIG.DEBUG_MODS_PER_TILE == 0) ? 1 : CONFIG.DEBUG_MODS_PER_TILE;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in_ready;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out_ready;
generate
if (CONFIG.USE_DEBUG == 1) begin : gen_debug_ring
genvar i;
logic [CONFIG.DEBUG_MODS_PER_TILE-1:0][15:0] id_map;
for (i = 0; i < CONFIG.DEBUG_MODS_PER_TILE; i = i+1) begin
assign id_map[i][15:0] = 16'(DEBUG_BASEID+i);
end
debug_ring_expand
#(.BUFFER_SIZE(CONFIG.DEBUG_ROUTER_BUFFER_SIZE),
.PORTS(CONFIG.DEBUG_MODS_PER_TILE))
u_debug_ring_segment
(.clk (clk),
.rst (rst_dbg),
.id_map (id_map),
.dii_in (dii_in),
.dii_in_ready (dii_in_ready),
.dii_out (dii_out),
.dii_out_ready (dii_out_ready),
.ext_in (debug_ring_in),
.ext_in_ready (debug_ring_in_ready),
.ext_out (debug_ring_out),
.ext_out_ready (debug_ring_out_ready));
end // if (USE_DEBUG)
endgenerate
/* wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
*/
wire [31:0] busms_adr_o;
wire busms_cyc_o;
wire [31:0] busms_dat_o;
wire [3:0] busms_sel_o;
wire busms_stb_o;
wire busms_we_o;
wire busms_cab_o;
wire [2:0] busms_cti_o;
wire [1:0] busms_bte_o;
wire busms_ack_i;
wire busms_rty_i;
wire busms_err_i;
wire [31:0] busms_dat_i;
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
wire [31:0] pic_ints_i [0:CONFIG.CORES_PER_TILE-1];
assign pic_ints_i[0][31:5] = 27'h0;
assign pic_ints_i[0][1:0] = 2'b00;
genvar c, m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
generate
for (c = 1; c < CONFIG.CORES_PER_TILE; c = c + 1) begin
assign pic_ints_i[c] = 32'h0;
end
endgenerate
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
#(.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(CONFIG.ENABLE_DM),
.S0_RANGE_WIDTH(CONFIG.DM_RANGE_WIDTH),.S0_RANGE_MATCH(CONFIG.DM_RANGE_MATCH),
.S1_ENABLE(CONFIG.ENABLE_PGAS),
.S1_RANGE_WIDTH(CONFIG.PGAS_RANGE_WIDTH),.S1_RANGE_MATCH(CONFIG.PGAS_RANGE_MATCH),
.S2_RANGE_WIDTH(4),.S2_RANGE_MATCH(4'he),
.S3_ENABLE(CONFIG.ENABLE_BOOTROM),
.S3_RANGE_WIDTH(4),.S3_RANGE_MATCH(4'hf)
// .S4_ENABLE(CONFIG.DEBUG_DEM_UART),
// .S4_RANGE_WIDTH(28),.S4_RANGE_MATCH(28'h9000000)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
//MAM - WB adapter signals
logic mam_dm_stb_o;
logic mam_dm_cyc_o;
logic mam_dm_ack_i;
logic mam_dm_err_i;
logic mam_dm_rty_i;
logic mam_dm_we_o;
logic [31:0] mam_dm_addr_o;
logic [31:0] mam_dm_dat_o;
logic [31:0] mam_dm_dat_i;
logic [2:0] mam_dm_cti_o;
logic [1:0] mam_dm_bte_o;
logic [3:0] mam_dm_sel_o;
if (CONFIG.USE_DEBUG == 1) begin : gen_mam_dm_wb
//MAM
osd_mam_wb #(
.DATA_WIDTH(32),
.MAX_PKT_LEN(CONFIG.DEBUG_MAX_PKT_LEN),
.MEM_SIZE0(CONFIG.LMEM_SIZE),
.BASE_ADDR0(0))
u_mam_dm_wb(
.clk_i(clk),
.rst_i(rst_dbg),
.debug_in(dii_out[0]),
.debug_in_ready(dii_out_ready[0]),
.debug_out(dii_in[0]),
.debug_out_ready(dii_in_ready[0]),
.id (16'(DEBUG_BASEID)),
.stb_o(mam_dm_stb_o),
.cyc_o(mam_dm_cyc_o),
.ack_i(mam_dm_ack_i),
.we_o(mam_dm_we_o),
.addr_o(mam_dm_addr_o),
.dat_o(mam_dm_dat_o),
.dat_i(mam_dm_dat_i),
.cti_o(mam_dm_cti_o),
.bte_o(mam_dm_bte_o),
.sel_o(mam_dm_sel_o));
end //if (USE_DEBUG == 1)
if (CONFIG.ENABLE_DM) begin : gen_mam_wb_adapter
/* mam_wb_adapter AUTO_TEMPLATE(
.wb_in_clk_i (clk),
.wb_in_rst_i (rst_sys),
.wb_in_\(.*\) (bussl_\1[SLAVE_DM]),
.wb_out_\(.*\) (wb_mem_\1),
); */
mam_wb_adapter
#(.DW(32),
.AW(32))
u_mam_wb_adapter_dm
(
.wb_mam_adr_o (mam_dm_addr_o),
.wb_mam_cyc_o (mam_dm_cyc_o),
.wb_mam_dat_o (mam_dm_dat_o),
.wb_mam_sel_o (mam_dm_sel_o),
.wb_mam_stb_o (mam_dm_stb_o),
.wb_mam_we_o (mam_dm_we_o),
.wb_mam_cab_o (1'b0),
.wb_mam_cti_o (mam_dm_cti_o),
.wb_mam_bte_o (mam_dm_bte_o),
.wb_mam_ack_i (mam_dm_ack_i),
.wb_mam_rty_i (mam_dm_rty_i),
.wb_mam_err_i (mam_dm_err_i),
.wb_mam_dat_i (mam_dm_dat_i),
/*AUTOINST*/
// Outputs
.wb_in_ack_o (bussl_ack_o[SLAVE_DM]), // Templated
.wb_in_err_o (bussl_err_o[SLAVE_DM]), // Templated
.wb_in_rty_o (bussl_rty_o[SLAVE_DM]), // Templated
.wb_in_dat_o (bussl_dat_o[SLAVE_DM]), // Templated
.wb_out_adr_i (wb_mem_adr_i), // Templated
.wb_out_bte_i (wb_mem_bte_i), // Templated
.wb_out_cti_i (wb_mem_cti_i), // Templated
.wb_out_cyc_i (wb_mem_cyc_i), // Templated
.wb_out_dat_i (wb_mem_dat_i), // Templated
.wb_out_sel_i (wb_mem_sel_i), // Templated
.wb_out_stb_i (wb_mem_stb_i), // Templated
.wb_out_we_i (wb_mem_we_i), // Templated
.wb_out_clk_i (wb_mem_clk_i), // Templated
.wb_out_rst_i (wb_mem_rst_i), // Templated
// Inputs
.wb_in_adr_i (bussl_adr_i[SLAVE_DM]), // Templated
.wb_in_bte_i (bussl_bte_i[SLAVE_DM]), // Templated
.wb_in_cti_i (bussl_cti_i[SLAVE_DM]), // Templated
.wb_in_cyc_i (bussl_cyc_i[SLAVE_DM]), // Templated
.wb_in_dat_i (bussl_dat_i[SLAVE_DM]), // Templated
.wb_in_sel_i (bussl_sel_i[SLAVE_DM]), // Templated
.wb_in_stb_i (bussl_stb_i[SLAVE_DM]), // Templated
.wb_in_we_i (bussl_we_i[SLAVE_DM]), // Templated
.wb_in_clk_i (clk), // Templated
.wb_in_rst_i (rst_sys), // Templated
.wb_out_ack_o (wb_mem_ack_o), // Templated
.wb_out_err_o (wb_mem_err_o), // Templated
.wb_out_rty_o (wb_mem_rty_o), // Templated
.wb_out_dat_o (wb_mem_dat_o)); // Templated
end else begin // if (CONFIG.ENABLE_DM)
assign mam_dm_dat_i = 32'hx;
assign {mam_dm_ack_i, mam_dm_err_i, mam_dm_rty_i} = 3'b000;
assign bussl_dat_o[SLAVE_DM] = 32'hx;
assign bussl_ack_o[SLAVE_DM] = 1'b0;
assign bussl_err_o[SLAVE_DM] = 1'b0;
assign bussl_rty_o[SLAVE_DM] = 1'b0;
end
if (!CONFIG.ENABLE_PGAS) begin : gen_tieoff_pgas
assign bussl_dat_o[SLAVE_PGAS] = 32'h0;
assign bussl_ack_o[SLAVE_PGAS] = 1'b0;
assign bussl_err_o[SLAVE_PGAS] = 1'b0;
assign bussl_rty_o[SLAVE_PGAS] = 1'b0;
end
generate
if ((CONFIG.ENABLE_DM) &&
(CONFIG.LMEM_STYLE == PLAIN)) begin : gen_sram
/* wb_sram_sp AUTO_TEMPLATE(
.wb_\(.*\) (wb_mem_\1),
); */
wb_sram_sp
#(.DW(32),
.AW(clog2_width(CONFIG.LMEM_SIZE)),
.MEM_SIZE_BYTE(CONFIG.LMEM_SIZE),
.MEM_FILE(MEM_FILE),
.MEM_IMPL_TYPE("PLAIN")
)
u_ram(/*AUTOINST*/
// Outputs
.wb_ack_o (wb_mem_ack_o),
.wb_err_o (wb_mem_err_o),
.wb_rty_o (wb_mem_rty_o),
.wb_dat_o (wb_mem_dat_o),
// Inputs
.wb_adr_i (wb_mem_adr_i[clog2_width(CONFIG.LMEM_SIZE)-1:0]),
.wb_bte_i (wb_mem_bte_i),
.wb_cti_i (wb_mem_cti_i),
.wb_cyc_i (wb_mem_cyc_i),
.wb_dat_i (wb_mem_dat_i),
.wb_sel_i (wb_mem_sel_i),
.wb_stb_i (wb_mem_stb_i),
.wb_we_i (wb_mem_we_i),
.wb_clk_i (wb_mem_clk_i),
.wb_rst_i (wb_mem_rst_i));
end else begin // block: gen_sram
assign wb_ext_adr_i = wb_mem_adr_i;
assign wb_ext_bte_i = wb_mem_bte_i;
assign wb_ext_cti_i = wb_mem_cti_i;
assign wb_ext_cyc_i = wb_mem_cyc_i;
assign wb_ext_dat_i = wb_mem_dat_i;
assign wb_ext_sel_i = wb_mem_sel_i;
assign wb_ext_stb_i = wb_mem_stb_i;
assign wb_ext_we_i = wb_mem_we_i;
assign wb_mem_ack_o = wb_ext_ack_o;
assign wb_mem_rty_o = wb_ext_rty_o;
assign wb_mem_err_o = wb_ext_err_o;
assign wb_mem_dat_o = wb_ext_dat_o;
end // else: !if((CONFIG.ENABLE_DM) &&...
endgenerate
networkadapter_ct
#(.CONFIG(CONFIG),
.TILEID(ID),
.COREBASE(COREBASE))
u_na(
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
.cdc_conf (cdc_conf[2:0]),
.cdc_enable (cdc_enable),
`endif
`endif
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o),
.wbm_cyc_o (busms_cyc_o),
.wbm_dat_o (busms_dat_o),
.wbm_sel_o (busms_sel_o),
.wbm_stb_o (busms_stb_o),
.wbm_we_o (busms_we_o),
.wbm_cab_o (busms_cab_o),
.wbm_cti_o (busms_cti_o),
.wbm_bte_o (busms_bte_o),
.wbs_ack_o (bussl_ack_o[SLAVE_NA]),
.wbs_rty_o (bussl_rty_o[SLAVE_NA]),
.wbs_err_o (bussl_err_o[SLAVE_NA]),
.wbs_dat_o (bussl_dat_o[SLAVE_NA]),
.irq (pic_ints_i[0][4:3]),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i),
.wbm_rty_i (busms_rty_i),
.wbm_err_i (busms_err_i),
.wbm_dat_i (busms_dat_i),
.wbs_adr_i (bussl_adr_i[SLAVE_NA]),
.wbs_cyc_i (bussl_cyc_i[SLAVE_NA]),
.wbs_dat_i (bussl_dat_i[SLAVE_NA]),
.wbs_sel_i (bussl_sel_i[SLAVE_NA]),
.wbs_stb_i (bussl_stb_i[SLAVE_NA]),
.wbs_we_i (bussl_we_i[SLAVE_NA]),
.wbs_cab_i (bussl_cab_i[SLAVE_NA]),
.wbs_cti_i (bussl_cti_i[SLAVE_NA]),
.wbs_bte_i (bussl_bte_i[SLAVE_NA]));
// generate
// if (CONFIG.ENABLE_BOOTROM) begin : gen_bootrom
// /* bootrom AUTO_TEMPLATE(
// .clk(clk),
// .rst(rst_sys),
// .wb_\(.*\) (bussl_\1[SLAVE_BOOT]),
// ); */
// bootrom
// u_bootrom
// (/*AUTOINST*/
// // Outputs
// .wb_dat_o (bussl_dat_o[SLAVE_BOOT]), // Templated
// .wb_ack_o (bussl_ack_o[SLAVE_BOOT]), // Templated
// .wb_err_o (bussl_err_o[SLAVE_BOOT]), // Templated
// .wb_rty_o (bussl_rty_o[SLAVE_BOOT]), // Templated
// // Inputs
// .clk (clk), // Templated
// .rst (rst_sys), // Templated
// .wb_adr_i (bussl_adr_i[SLAVE_BOOT]), // Templated
// .wb_dat_i (bussl_dat_i[SLAVE_BOOT]), // Templated
// .wb_cyc_i (bussl_cyc_i[SLAVE_BOOT]), // Templated
// .wb_stb_i (bussl_stb_i[SLAVE_BOOT]), // Templated
// .wb_sel_i (bussl_sel_i[SLAVE_BOOT])); // Templated
// end else begin // if (CONFIG.ENABLE_BOOTROM)
// assign bussl_dat_o[SLAVE_BOOT] = 32'hx;
// assign bussl_ack_o[SLAVE_BOOT] = 1'b0;
// assign bussl_err_o[SLAVE_BOOT] = 1'b0;
// assign bussl_rty_o[SLAVE_BOOT] = 1'b0;
// end // else: !if(CONFIG.ENABLE_BOOTROM)
// endgenerate
picorv32_wb RV32
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wbm_adr_o (busms_adr_o), // Templated
.wbm_dat_i (busms_dat_i), // Templated
.wbm_cyc_o (busms_cyc_o), // Templated
.wbm_stb_o (busms_stb_o), // Templated
.wbm_we_o (busms_we_o), // Templated
.wbm_dat_o (busms_dat_o), // Templated
.wbm_ack_i (busms_ack_i), // Templated
.wbm_sel_o ()
//.wbm_err_o (busms_err_o)
); // Templated
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the compute tile for distributed memory systems.
*
*
* The assignment of the 32 bit IRQ vector connected to core 0 is as follows:
* - Bit [1:0]: N/A
* - Bit 2: UART
* - Bit 3: NA - message passing
* - Bit 4: NA - DMA
* - Bit [31:5]: N/A
*
* The address ranges of the bus slaves are as follows:
* - Slave 0 - DM: 0x00000000-0x7fffffff
* - Slave 1 - PGAS: not used
* - Slave 2 - NA: 0xe0000000-0xefffffff
* - Slave 3 - BOOT: 0xf0000000-0xffffffff
* - Slave 4 - UART: 0x90000000-0x9000000f
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module cpusubsys1
import dii_package::dii_flit;
import opensocdebug::mor1kx_trace_exec;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
parameter ID = 'x,
parameter COREBASE = 'x,
parameter DEBUG_BASEID = 'x,
parameter MEM_FILE = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH
)
(
input dii_flit [1:0] debug_ring_in,
output [1:0] debug_ring_in_ready,
output dii_flit [1:0] debug_ring_out,
input [1:0] debug_ring_out_ready,
output [31:0] wb_ext_adr_i,
output wb_ext_cyc_i,
output [31:0] wb_ext_dat_i,
output [3:0] wb_ext_sel_i,
output wb_ext_stb_i,
output wb_ext_we_i,
output wb_ext_cab_i,
output [2:0] wb_ext_cti_i,
output [1:0] wb_ext_bte_i,
input wb_ext_ack_o,
input wb_ext_rty_o,
input wb_ext_err_o,
input [31:0] wb_ext_dat_o,
input clk,
input rst_cpu, rst_sys, rst_dbg,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
import optimsoc_functions::*;
localparam NR_MASTERS = 2;
localparam NR_SLAVES = 3;
localparam SLAVE_NA = 0;
localparam SLAVE_DM = 1;
localparam SLAVE_PGAS = 2;
mor1kx_trace_exec [CONFIG.CORES_PER_TILE-1:0] trace;
logic wb_mem_clk_i;
logic wb_mem_rst_i;
logic [31:0] wb_mem_adr_i;
logic wb_mem_cyc_i;
logic [31:0] wb_mem_dat_i;
logic [3:0] wb_mem_sel_i;
logic wb_mem_stb_i;
logic wb_mem_we_i;
logic wb_mem_cab_i;
logic [2:0] wb_mem_cti_i;
logic [1:0] wb_mem_bte_i;
logic wb_mem_ack_o;
logic wb_mem_rty_o;
logic wb_mem_err_o;
logic [31:0] wb_mem_dat_o;
// create DI ring segment with routers
localparam DEBUG_MODS_PER_TILE_NONZERO = (CONFIG.DEBUG_MODS_PER_TILE == 0) ? 1 : CONFIG.DEBUG_MODS_PER_TILE;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in_ready;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out_ready;
generate
if (CONFIG.USE_DEBUG == 1) begin : gen_debug_ring
genvar i;
logic [CONFIG.DEBUG_MODS_PER_TILE-1:0][15:0] id_map;
for (i = 0; i < CONFIG.DEBUG_MODS_PER_TILE; i = i+1) begin
assign id_map[i][15:0] = 16'(DEBUG_BASEID+i);
end
debug_ring_expand
#(.BUFFER_SIZE(CONFIG.DEBUG_ROUTER_BUFFER_SIZE),
.PORTS(CONFIG.DEBUG_MODS_PER_TILE))
u_debug_ring_segment
(.clk (clk),
.rst (rst_dbg),
.id_map (id_map),
.dii_in (dii_in),
.dii_in_ready (dii_in_ready),
.dii_out (dii_out),
.dii_out_ready (dii_out_ready),
.ext_in (debug_ring_in),
.ext_in_ready (debug_ring_in_ready),
.ext_out (debug_ring_out),
.ext_out_ready (debug_ring_out_ready));
end // if (USE_DEBUG)
endgenerate
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
wire [31:0] pic_ints_i [0:CONFIG.CORES_PER_TILE-1];
assign pic_ints_i[0][31:5] = 27'h0;
assign pic_ints_i[0][1:0] = 2'b00;
genvar m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* generate
for (c = 1; c < CONFIG.CORES_PER_TILE; c = c + 1) begin
assign pic_ints_i[c] = 32'h0;
end
endgenerate*/
localparam c0 = 0;
picorv32_wb_ic
// #(.ID(c0),
// .NUMCORES(1)
// )
RV32IC
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wbm_adr_o (busms_adr_o[c0*2][31:0]), // Templated
.wbm_dat_i (busms_dat_i[c0*2+1][31:0]), // Templated
.wbm_cyc_o (busms_cyc_o[c0*2+1]), // Templated
.wbm_stb_o (busms_stb_o[c0*2+1]), // Templated
.wbm_we_o (busms_we_o[c0*2+1]), // Templated
.wbm_dat_o (busms_dat_o[c0*2+1][31:0]), // Templated
.wbm_ack_i (busms_ack_i[c0*2+1]), // Templated
.wbm_sel_o ()
//.wbm_err_o (busms_err_o)
); // Templated
assign busms_cab_o[c0*2] = 1'b0;
assign busms_cab_o[c0*2+1] = 1'b0;
/*if (CONFIG.USE_DEBUG == 1) begin : gen_ctm_stm
osd_stm_mor1kx
#(.MAX_PKT_LEN(CONFIG.DEBUG_MAX_PKT_LEN))
u_stm
(.clk (clk),
.rst (rst_dbg),
.id (16'(DEBUG_BASEID + 1 + c*CONFIG.DEBUG_MODS_PER_CORE)),
.debug_in (dii_out[1+c*CONFIG.DEBUG_MODS_PER_CORE]),
.debug_in_ready (dii_out_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE]),
.debug_out (dii_in[1+c*CONFIG.DEBUG_MODS_PER_CORE]),
.debug_out_ready (dii_in_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE]),
.trace_port (trace[c]));
osd_ctm_mor1kx
#(.MAX_PKT_LEN(CONFIG.DEBUG_MAX_PKT_LEN))
u_ctm
(.clk (clk),
.rst (rst_dbg),
.id (16'(DEBUG_BASEID + 1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1)),
.debug_in (dii_out[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.debug_in_ready (dii_out_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.debug_out (dii_in[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.debug_out_ready (dii_in_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.trace_port (trace[c]));
end*/
localparam c1 = 1;
picorv32_wb_i
// #(.ID(c1),
// .NUMCORES(1)
// )
RV32I
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wbm_adr_o (busms_adr_o[c1*2][31:0]), // Templated
.wbm_dat_i (busms_dat_i[c1*2+1][31:0]), // Templated
.wbm_cyc_o (busms_cyc_o[c1*2+1]), // Templated
.wbm_stb_o (busms_stb_o[c1*2+1]), // Templated
.wbm_we_o (busms_we_o[c1*2+1]), // Templated
.wbm_dat_o (busms_dat_o[c1*2+1][31:0]), // Templated
.wbm_ack_i (busms_ack_i[c1*2+1]), // Templated
.wbm_sel_o ()
//.wbm_err_o (busms_err_o)
); // Templated
assign busms_cab_o[c1*2] = 1'b0;
assign busms_cab_o[c1*2+1] = 1'b0;
/*if (CONFIG.USE_DEBUG == 1) begin : gen_ctm_stm
osd_stm_mor1kx
#(.MAX_PKT_LEN(CONFIG.DEBUG_MAX_PKT_LEN))
u_stm
(.clk (clk),
.rst (rst_dbg),
.id (16'(DEBUG_BASEID + 1 + c*CONFIG.DEBUG_MODS_PER_CORE)),
.debug_in (dii_out[1+c*CONFIG.DEBUG_MODS_PER_CORE]),
.debug_in_ready (dii_out_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE]),
.debug_out (dii_in[1+c*CONFIG.DEBUG_MODS_PER_CORE]),
.debug_out_ready (dii_in_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE]),
.trace_port (trace[c]));
osd_ctm_mor1kx
#(.MAX_PKT_LEN(CONFIG.DEBUG_MAX_PKT_LEN))
u_ctm
(.clk (clk),
.rst (rst_dbg),
.id (16'(DEBUG_BASEID + 1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1)),
.debug_in (dii_out[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.debug_in_ready (dii_out_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.debug_out (dii_in[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.debug_out_ready (dii_in_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.trace_port (trace[c]));
end*/
/* generate
if (CONFIG.USE_DEBUG != 0 && CONFIG.DEBUG_DEM_UART != 0) begin : gen_dem_uart
osd_dem_uart_wb
u_dem_uart(
.clk (clk),
.rst (rst_sys),
.id (16'(DEBUG_BASEID + CONFIG.DEBUG_MODS_PER_TILE - 1)),
.irq (pic_ints_i[0][2]),
.debug_in (dii_out[CONFIG.DEBUG_MODS_PER_TILE - 1]),
.debug_in_ready (dii_out_ready[CONFIG.DEBUG_MODS_PER_TILE - 1]),
.debug_out (dii_in[CONFIG.DEBUG_MODS_PER_TILE - 1]),
.debug_out_ready (dii_in_ready[CONFIG.DEBUG_MODS_PER_TILE - 1]),
.wb_adr_i (bussl_adr_i[SLAVE_UART][3:0]),
.wb_cyc_i (bussl_cyc_i[SLAVE_UART]),
.wb_dat_i (bussl_dat_i[SLAVE_UART]),
.wb_sel_i (bussl_sel_i[SLAVE_UART]),
.wb_stb_i (bussl_stb_i[SLAVE_UART]),
.wb_we_i (bussl_we_i[SLAVE_UART]),
.wb_cti_i (bussl_cti_i[SLAVE_UART]),
.wb_bte_i (bussl_bte_i[SLAVE_UART]),
.wb_ack_o (bussl_ack_o[SLAVE_UART]),
.wb_err_o (bussl_err_o[SLAVE_UART]),
.wb_rty_o (bussl_rty_o[SLAVE_UART]),
.wb_dat_o (bussl_dat_o[SLAVE_UART]));
end
endgenerate */
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
#(.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(CONFIG.ENABLE_DM),
.S0_RANGE_WIDTH(CONFIG.DM_RANGE_WIDTH),.S0_RANGE_MATCH(CONFIG.DM_RANGE_MATCH),
.S1_ENABLE(CONFIG.ENABLE_PGAS),
.S1_RANGE_WIDTH(CONFIG.PGAS_RANGE_WIDTH),.S1_RANGE_MATCH(CONFIG.PGAS_RANGE_MATCH),
.S2_RANGE_WIDTH(4),.S2_RANGE_MATCH(4'he),
.S3_ENABLE(CONFIG.ENABLE_BOOTROM),
.S3_RANGE_WIDTH(4),.S3_RANGE_MATCH(4'hf)
// .S4_ENABLE(CONFIG.DEBUG_DEM_UART),
// .S4_RANGE_WIDTH(28),.S4_RANGE_MATCH(28'h9000000)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
//MAM - WB adapter signals
logic mam_dm_stb_o;
logic mam_dm_cyc_o;
logic mam_dm_ack_i;
logic mam_dm_err_i;
logic mam_dm_rty_i;
logic mam_dm_we_o;
logic [31:0] mam_dm_addr_o;
logic [31:0] mam_dm_dat_o;
logic [31:0] mam_dm_dat_i;
logic [2:0] mam_dm_cti_o;
logic [1:0] mam_dm_bte_o;
logic [3:0] mam_dm_sel_o;
if (CONFIG.USE_DEBUG == 1) begin : gen_mam_dm_wb
//MAM
osd_mam_wb #(
.DATA_WIDTH(32),
.MAX_PKT_LEN(CONFIG.DEBUG_MAX_PKT_LEN),
.MEM_SIZE0(CONFIG.LMEM_SIZE),
.BASE_ADDR0(0))
u_mam_dm_wb(
.clk_i(clk),
.rst_i(rst_dbg),
.debug_in(dii_out[0]),
.debug_in_ready(dii_out_ready[0]),
.debug_out(dii_in[0]),
.debug_out_ready(dii_in_ready[0]),
.id (16'(DEBUG_BASEID)),
.stb_o(mam_dm_stb_o),
.cyc_o(mam_dm_cyc_o),
.ack_i(mam_dm_ack_i),
.we_o(mam_dm_we_o),
.addr_o(mam_dm_addr_o),
.dat_o(mam_dm_dat_o),
.dat_i(mam_dm_dat_i),
.cti_o(mam_dm_cti_o),
.bte_o(mam_dm_bte_o),
.sel_o(mam_dm_sel_o));
end //if (USE_DEBUG == 1)
if (CONFIG.ENABLE_DM) begin : gen_mam_wb_adapter
/* mam_wb_adapter AUTO_TEMPLATE(
.wb_in_clk_i (clk),
.wb_in_rst_i (rst_sys),
.wb_in_\(.*\) (bussl_\1[SLAVE_DM]),
.wb_out_\(.*\) (wb_mem_\1),
); */
mam_wb_adapter
#(.DW(32),
.AW(32))
u_mam_wb_adapter_dm
(
.wb_mam_adr_o (mam_dm_addr_o),
.wb_mam_cyc_o (mam_dm_cyc_o),
.wb_mam_dat_o (mam_dm_dat_o),
.wb_mam_sel_o (mam_dm_sel_o),
.wb_mam_stb_o (mam_dm_stb_o),
.wb_mam_we_o (mam_dm_we_o),
.wb_mam_cab_o (1'b0),
.wb_mam_cti_o (mam_dm_cti_o),
.wb_mam_bte_o (mam_dm_bte_o),
.wb_mam_ack_i (mam_dm_ack_i),
.wb_mam_rty_i (mam_dm_rty_i),
.wb_mam_err_i (mam_dm_err_i),
.wb_mam_dat_i (mam_dm_dat_i),
/*AUTOINST*/
// Outputs
.wb_in_ack_o (bussl_ack_o[SLAVE_DM]), // Templated
.wb_in_err_o (bussl_err_o[SLAVE_DM]), // Templated
.wb_in_rty_o (bussl_rty_o[SLAVE_DM]), // Templated
.wb_in_dat_o (bussl_dat_o[SLAVE_DM]), // Templated
.wb_out_adr_i (wb_mem_adr_i), // Templated
.wb_out_bte_i (wb_mem_bte_i), // Templated
.wb_out_cti_i (wb_mem_cti_i), // Templated
.wb_out_cyc_i (wb_mem_cyc_i), // Templated
.wb_out_dat_i (wb_mem_dat_i), // Templated
.wb_out_sel_i (wb_mem_sel_i), // Templated
.wb_out_stb_i (wb_mem_stb_i), // Templated
.wb_out_we_i (wb_mem_we_i), // Templated
.wb_out_clk_i (wb_mem_clk_i), // Templated
.wb_out_rst_i (wb_mem_rst_i), // Templated
// Inputs
.wb_in_adr_i (bussl_adr_i[SLAVE_DM]), // Templated
.wb_in_bte_i (bussl_bte_i[SLAVE_DM]), // Templated
.wb_in_cti_i (bussl_cti_i[SLAVE_DM]), // Templated
.wb_in_cyc_i (bussl_cyc_i[SLAVE_DM]), // Templated
.wb_in_dat_i (bussl_dat_i[SLAVE_DM]), // Templated
.wb_in_sel_i (bussl_sel_i[SLAVE_DM]), // Templated
.wb_in_stb_i (bussl_stb_i[SLAVE_DM]), // Templated
.wb_in_we_i (bussl_we_i[SLAVE_DM]), // Templated
.wb_in_clk_i (clk), // Templated
.wb_in_rst_i (rst_sys), // Templated
.wb_out_ack_o (wb_mem_ack_o), // Templated
.wb_out_err_o (wb_mem_err_o), // Templated
.wb_out_rty_o (wb_mem_rty_o), // Templated
.wb_out_dat_o (wb_mem_dat_o)); // Templated
end else begin // if (CONFIG.ENABLE_DM)
assign mam_dm_dat_i = 32'hx;
assign {mam_dm_ack_i, mam_dm_err_i, mam_dm_rty_i} = 3'b000;
assign bussl_dat_o[SLAVE_DM] = 32'hx;
assign bussl_ack_o[SLAVE_DM] = 1'b0;
assign bussl_err_o[SLAVE_DM] = 1'b0;
assign bussl_rty_o[SLAVE_DM] = 1'b0;
end
if (!CONFIG.ENABLE_PGAS) begin : gen_tieoff_pgas
assign bussl_dat_o[SLAVE_PGAS] = 32'h0;
assign bussl_ack_o[SLAVE_PGAS] = 1'b0;
assign bussl_err_o[SLAVE_PGAS] = 1'b0;
assign bussl_rty_o[SLAVE_PGAS] = 1'b0;
end
generate
if ((CONFIG.ENABLE_DM) &&
(CONFIG.LMEM_STYLE == PLAIN)) begin : gen_sram
/* wb_sram_sp AUTO_TEMPLATE(
.wb_\(.*\) (wb_mem_\1),
); */
wb_sram_sp
#(.DW(32),
.AW(clog2_width(CONFIG.LMEM_SIZE)),
.MEM_SIZE_BYTE(CONFIG.LMEM_SIZE),
.MEM_FILE(MEM_FILE),
.MEM_IMPL_TYPE("PLAIN")
)
u_ram(/*AUTOINST*/
// Outputs
.wb_ack_o (wb_mem_ack_o),
.wb_err_o (wb_mem_err_o),
.wb_rty_o (wb_mem_rty_o),
.wb_dat_o (wb_mem_dat_o),
// Inputs
.wb_adr_i (wb_mem_adr_i[clog2_width(CONFIG.LMEM_SIZE)-1:0]),
.wb_bte_i (wb_mem_bte_i),
.wb_cti_i (wb_mem_cti_i),
.wb_cyc_i (wb_mem_cyc_i),
.wb_dat_i (wb_mem_dat_i),
.wb_sel_i (wb_mem_sel_i),
.wb_stb_i (wb_mem_stb_i),
.wb_we_i (wb_mem_we_i),
.wb_clk_i (wb_mem_clk_i),
.wb_rst_i (wb_mem_rst_i));
end else begin // block: gen_sram
assign wb_ext_adr_i = wb_mem_adr_i;
assign wb_ext_bte_i = wb_mem_bte_i;
assign wb_ext_cti_i = wb_mem_cti_i;
assign wb_ext_cyc_i = wb_mem_cyc_i;
assign wb_ext_dat_i = wb_mem_dat_i;
assign wb_ext_sel_i = wb_mem_sel_i;
assign wb_ext_stb_i = wb_mem_stb_i;
assign wb_ext_we_i = wb_mem_we_i;
assign wb_mem_ack_o = wb_ext_ack_o;
assign wb_mem_rty_o = wb_ext_rty_o;
assign wb_mem_err_o = wb_ext_err_o;
assign wb_mem_dat_o = wb_ext_dat_o;
end // else: !if((CONFIG.ENABLE_DM) &&...
endgenerate
networkadapter_ct
#(.CONFIG(CONFIG),
.TILEID(ID),
.COREBASE(COREBASE))
u_na(
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
.cdc_conf (cdc_conf[2:0]),
.cdc_enable (cdc_enable),
`endif
`endif
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[SLAVE_NA]),
.wbs_rty_o (bussl_rty_o[SLAVE_NA]),
.wbs_err_o (bussl_err_o[SLAVE_NA]),
.wbs_dat_o (bussl_dat_o[SLAVE_NA]),
.irq (pic_ints_i[0][4:3]),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[SLAVE_NA]),
.wbs_cyc_i (bussl_cyc_i[SLAVE_NA]),
.wbs_dat_i (bussl_dat_i[SLAVE_NA]),
.wbs_sel_i (bussl_sel_i[SLAVE_NA]),
.wbs_stb_i (bussl_stb_i[SLAVE_NA]),
.wbs_we_i (bussl_we_i[SLAVE_NA]),
.wbs_cab_i (bussl_cab_i[SLAVE_NA]),
.wbs_cti_i (bussl_cti_i[SLAVE_NA]),
.wbs_bte_i (bussl_bte_i[SLAVE_NA]));
// generate
// if (CONFIG.ENABLE_BOOTROM) begin : gen_bootrom
// /* bootrom AUTO_TEMPLATE(
// .clk(clk),
// .rst(rst_sys),
// .wb_\(.*\) (bussl_\1[SLAVE_BOOT]),
// ); */
// bootrom
// u_bootrom
// (/*AUTOINST*/
// // Outputs
// .wb_dat_o (bussl_dat_o[SLAVE_BOOT]), // Templated
// .wb_ack_o (bussl_ack_o[SLAVE_BOOT]), // Templated
// .wb_err_o (bussl_err_o[SLAVE_BOOT]), // Templated
// .wb_rty_o (bussl_rty_o[SLAVE_BOOT]), // Templated
// // Inputs
// .clk (clk), // Templated
// .rst (rst_sys), // Templated
// .wb_adr_i (bussl_adr_i[SLAVE_BOOT]), // Templated
// .wb_dat_i (bussl_dat_i[SLAVE_BOOT]), // Templated
// .wb_cyc_i (bussl_cyc_i[SLAVE_BOOT]), // Templated
// .wb_stb_i (bussl_stb_i[SLAVE_BOOT]), // Templated
// .wb_sel_i (bussl_sel_i[SLAVE_BOOT])); // Templated
// end else begin // if (CONFIG.ENABLE_BOOTROM)
// assign bussl_dat_o[SLAVE_BOOT] = 32'hx;
// assign bussl_ack_o[SLAVE_BOOT] = 1'b0;
// assign bussl_err_o[SLAVE_BOOT] = 1'b0;
// assign bussl_rty_o[SLAVE_BOOT] = 1'b0;
// end // else: !if(CONFIG.ENABLE_BOOTROM)
// endgenerate
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the compute tile for distributed memory systems.
*
*
* The assignment of the 32 bit IRQ vector connected to core 0 is as follows:
* - Bit [1:0]: N/A
* - Bit 2: UART
* - Bit 3: NA - message passing
* - Bit 4: NA - DMA
* - Bit [31:5]: N/A
*
* The address ranges of the bus slaves are as follows:
* - Slave 0 - DM: 0x00000000-0x7fffffff
* - Slave 1 - PGAS: not used
* - Slave 2 - NA: 0xe0000000-0xefffffff
* - Slave 3 - BOOT: 0xf0000000-0xffffffff
* - Slave 4 - UART: 0x90000000-0x9000000f
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module cpusubsys2
import dii_package::dii_flit;
import opensocdebug::mor1kx_trace_exec;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
parameter ID = 'x,
parameter COREBASE = 'x,
parameter DEBUG_BASEID = 'x,
parameter MEM_FILE = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH
)
(
input dii_flit [1:0] debug_ring_in,
output [1:0] debug_ring_in_ready,
output dii_flit [1:0] debug_ring_out,
input [1:0] debug_ring_out_ready,
output [31:0] wb_ext_adr_i,
output wb_ext_cyc_i,
output [31:0] wb_ext_dat_i,
output [3:0] wb_ext_sel_i,
output wb_ext_stb_i,
output wb_ext_we_i,
output wb_ext_cab_i,
output [2:0] wb_ext_cti_i,
output [1:0] wb_ext_bte_i,
input wb_ext_ack_o,
input wb_ext_rty_o,
input wb_ext_err_o,
input [31:0] wb_ext_dat_o,
input clk,
input rst_cpu, rst_sys, rst_dbg,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
import optimsoc_functions::*;
localparam NR_MASTERS = 2;
localparam NR_SLAVES = 3;
localparam SLAVE_NA = 0;
localparam SLAVE_DM = 1;
localparam SLAVE_PGAS = 2;
mor1kx_trace_exec [CONFIG.CORES_PER_TILE-1:0] trace;
logic wb_mem_clk_i;
logic wb_mem_rst_i;
logic [31:0] wb_mem_adr_i;
logic wb_mem_cyc_i;
logic [31:0] wb_mem_dat_i;
logic [3:0] wb_mem_sel_i;
logic wb_mem_stb_i;
logic wb_mem_we_i;
logic wb_mem_cab_i;
logic [2:0] wb_mem_cti_i;
logic [1:0] wb_mem_bte_i;
logic wb_mem_ack_o;
logic wb_mem_rty_o;
logic wb_mem_err_o;
logic [31:0] wb_mem_dat_o;
// create DI ring segment with routers
localparam DEBUG_MODS_PER_TILE_NONZERO = (CONFIG.DEBUG_MODS_PER_TILE == 0) ? 1 : CONFIG.DEBUG_MODS_PER_TILE;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in_ready;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out_ready;
generate
if (CONFIG.USE_DEBUG == 1) begin : gen_debug_ring
genvar i;
logic [CONFIG.DEBUG_MODS_PER_TILE-1:0][15:0] id_map;
for (i = 0; i < CONFIG.DEBUG_MODS_PER_TILE; i = i+1) begin
assign id_map[i][15:0] = 16'(DEBUG_BASEID+i);
end
debug_ring_expand
#(.BUFFER_SIZE(CONFIG.DEBUG_ROUTER_BUFFER_SIZE),
.PORTS(CONFIG.DEBUG_MODS_PER_TILE))
u_debug_ring_segment
(.clk (clk),
.rst (rst_dbg),
.id_map (id_map),
.dii_in (dii_in),
.dii_in_ready (dii_in_ready),
.dii_out (dii_out),
.dii_out_ready (dii_out_ready),
.ext_in (debug_ring_in),
.ext_in_ready (debug_ring_in_ready),
.ext_out (debug_ring_out),
.ext_out_ready (debug_ring_out_ready));
end // if (USE_DEBUG)
endgenerate
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
wire [31:0] pic_ints_i [0:CONFIG.CORES_PER_TILE-1];
assign pic_ints_i[0][31:5] = 27'h0;
assign pic_ints_i[0][1:0] = 2'b00;
genvar c, m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* generate
for (c = 1; c < CONFIG.CORES_PER_TILE; c = c + 1) begin
assign pic_ints_i[c] = 32'h0;
end
endgenerate*/
localparam c3 = 3;
picorv32_wb_imc
// #(.ID(c3),
// .NUMCORES(1)
// )
RV32IMC
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wbm_adr_o (busms_adr_o[c3*2][31:0]), // Templated
.wbm_dat_i (busms_dat_i[c3*2+1][31:0]), // Templated
.wbm_cyc_o (busms_cyc_o[c3*2+1]), // Templated
.wbm_stb_o (busms_stb_o[c3*2+1]), // Templated
.wbm_we_o (busms_we_o[c3*2+1]), // Templated
.wbm_dat_o (busms_dat_o[c3*2+1][31:0]), // Templated
.wbm_ack_i (busms_ack_i[c3*2+1]), // Templated
.wbm_sel_o ()
//.wbm_err_o (busms_err_o)
); // Templated
assign busms_cab_o[c3*2] = 1'b0;
assign busms_cab_o[c3*2+1] = 1'b0;
/* if (CONFIG.USE_DEBUG == 1) begin : gen_ctm_stm
osd_stm_mor1kx
#(.MAX_PKT_LEN(CONFIG.DEBUG_MAX_PKT_LEN))
u_stm
(.clk (clk),
.rst (rst_dbg),
.id (16'(DEBUG_BASEID + 1 + c*CONFIG.DEBUG_MODS_PER_CORE)),
.debug_in (dii_out[1+c*CONFIG.DEBUG_MODS_PER_CORE]),
.debug_in_ready (dii_out_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE]),
.debug_out (dii_in[1+c*CONFIG.DEBUG_MODS_PER_CORE]),
.debug_out_ready (dii_in_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE]),
.trace_port (trace[c]));
osd_ctm_mor1kx
#(.MAX_PKT_LEN(CONFIG.DEBUG_MAX_PKT_LEN))
u_ctm
(.clk (clk),
.rst (rst_dbg),
.id (16'(DEBUG_BASEID + 1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1)),
.debug_in (dii_out[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.debug_in_ready (dii_out_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.debug_out (dii_in[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.debug_out_ready (dii_in_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.trace_port (trace[c]));
end*/
localparam c2 = 2;
picorv32_wb_im
// #(.ID(c2),
// .NUMCORES(1)
// )
RV32IM
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wbm_adr_o (busms_adr_o[c2*2][31:0]), // Templated
.wbm_dat_i (busms_dat_i[c2*2+1][31:0]), // Templated
.wbm_cyc_o (busms_cyc_o[c2*2+1]), // Templated
.wbm_stb_o (busms_stb_o[c2*2+1]), // Templated
.wbm_we_o (busms_we_o[c2*2+1]), // Templated
.wbm_dat_o (busms_dat_o[c2*2+1][31:0]), // Templated
.wbm_ack_i (busms_ack_i[c2*2+1]), // Templated
.wbm_sel_o ()
//.wbm_err_o (busms_err_o)
); // Templated
assign busms_cab_o[c2*2] = 1'b0;
assign busms_cab_o[c2*2+1] = 1'b0;
/* if (CONFIG.USE_DEBUG == 1) begin : gen_ctm_stm
osd_stm_mor1kx
#(.MAX_PKT_LEN(CONFIG.DEBUG_MAX_PKT_LEN))
u_stm
(.clk (clk),
.rst (rst_dbg),
.id (16'(DEBUG_BASEID + 1 + c*CONFIG.DEBUG_MODS_PER_CORE)),
.debug_in (dii_out[1+c*CONFIG.DEBUG_MODS_PER_CORE]),
.debug_in_ready (dii_out_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE]),
.debug_out (dii_in[1+c*CONFIG.DEBUG_MODS_PER_CORE]),
.debug_out_ready (dii_in_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE]),
.trace_port (trace[c]));
osd_ctm_mor1kx
#(.MAX_PKT_LEN(CONFIG.DEBUG_MAX_PKT_LEN))
u_ctm
(.clk (clk),
.rst (rst_dbg),
.id (16'(DEBUG_BASEID + 1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1)),
.debug_in (dii_out[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.debug_in_ready (dii_out_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.debug_out (dii_in[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.debug_out_ready (dii_in_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.trace_port (trace[c]));
end*/
/* generate
if (CONFIG.USE_DEBUG != 0 && CONFIG.DEBUG_DEM_UART != 0) begin : gen_dem_uart
osd_dem_uart_wb
u_dem_uart(
.clk (clk),
.rst (rst_sys),
.id (16'(DEBUG_BASEID + CONFIG.DEBUG_MODS_PER_TILE - 1)),
.irq (pic_ints_i[0][2]),
.debug_in (dii_out[CONFIG.DEBUG_MODS_PER_TILE - 1]),
.debug_in_ready (dii_out_ready[CONFIG.DEBUG_MODS_PER_TILE - 1]),
.debug_out (dii_in[CONFIG.DEBUG_MODS_PER_TILE - 1]),
.debug_out_ready (dii_in_ready[CONFIG.DEBUG_MODS_PER_TILE - 1]),
.wb_adr_i (bussl_adr_i[SLAVE_UART][3:0]),
.wb_cyc_i (bussl_cyc_i[SLAVE_UART]),
.wb_dat_i (bussl_dat_i[SLAVE_UART]),
.wb_sel_i (bussl_sel_i[SLAVE_UART]),
.wb_stb_i (bussl_stb_i[SLAVE_UART]),
.wb_we_i (bussl_we_i[SLAVE_UART]),
.wb_cti_i (bussl_cti_i[SLAVE_UART]),
.wb_bte_i (bussl_bte_i[SLAVE_UART]),
.wb_ack_o (bussl_ack_o[SLAVE_UART]),
.wb_err_o (bussl_err_o[SLAVE_UART]),
.wb_rty_o (bussl_rty_o[SLAVE_UART]),
.wb_dat_o (bussl_dat_o[SLAVE_UART]));
end
endgenerate */
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
#(.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(CONFIG.ENABLE_DM),
.S0_RANGE_WIDTH(CONFIG.DM_RANGE_WIDTH),.S0_RANGE_MATCH(CONFIG.DM_RANGE_MATCH),
.S1_ENABLE(CONFIG.ENABLE_PGAS),
.S1_RANGE_WIDTH(CONFIG.PGAS_RANGE_WIDTH),.S1_RANGE_MATCH(CONFIG.PGAS_RANGE_MATCH),
.S2_RANGE_WIDTH(4),.S2_RANGE_MATCH(4'he),
.S3_ENABLE(CONFIG.ENABLE_BOOTROM),
.S3_RANGE_WIDTH(4),.S3_RANGE_MATCH(4'hf)
// .S4_ENABLE(CONFIG.DEBUG_DEM_UART),
// .S4_RANGE_WIDTH(28),.S4_RANGE_MATCH(28'h9000000)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
//MAM - WB adapter signals
logic mam_dm_stb_o;
logic mam_dm_cyc_o;
logic mam_dm_ack_i;
logic mam_dm_err_i;
logic mam_dm_rty_i;
logic mam_dm_we_o;
logic [31:0] mam_dm_addr_o;
logic [31:0] mam_dm_dat_o;
logic [31:0] mam_dm_dat_i;
logic [2:0] mam_dm_cti_o;
logic [1:0] mam_dm_bte_o;
logic [3:0] mam_dm_sel_o;
if (CONFIG.USE_DEBUG == 1) begin : gen_mam_dm_wb
//MAM
osd_mam_wb #(
.DATA_WIDTH(32),
.MAX_PKT_LEN(CONFIG.DEBUG_MAX_PKT_LEN),
.MEM_SIZE0(CONFIG.LMEM_SIZE),
.BASE_ADDR0(0))
u_mam_dm_wb(
.clk_i(clk),
.rst_i(rst_dbg),
.debug_in(dii_out[0]),
.debug_in_ready(dii_out_ready[0]),
.debug_out(dii_in[0]),
.debug_out_ready(dii_in_ready[0]),
.id (16'(DEBUG_BASEID)),
.stb_o(mam_dm_stb_o),
.cyc_o(mam_dm_cyc_o),
.ack_i(mam_dm_ack_i),
.we_o(mam_dm_we_o),
.addr_o(mam_dm_addr_o),
.dat_o(mam_dm_dat_o),
.dat_i(mam_dm_dat_i),
.cti_o(mam_dm_cti_o),
.bte_o(mam_dm_bte_o),
.sel_o(mam_dm_sel_o));
end //if (USE_DEBUG == 1)
if (CONFIG.ENABLE_DM) begin : gen_mam_wb_adapter
/* mam_wb_adapter AUTO_TEMPLATE(
.wb_in_clk_i (clk),
.wb_in_rst_i (rst_sys),
.wb_in_\(.*\) (bussl_\1[SLAVE_DM]),
.wb_out_\(.*\) (wb_mem_\1),
); */
mam_wb_adapter
#(.DW(32),
.AW(32))
u_mam_wb_adapter_dm
(
.wb_mam_adr_o (mam_dm_addr_o),
.wb_mam_cyc_o (mam_dm_cyc_o),
.wb_mam_dat_o (mam_dm_dat_o),
.wb_mam_sel_o (mam_dm_sel_o),
.wb_mam_stb_o (mam_dm_stb_o),
.wb_mam_we_o (mam_dm_we_o),
.wb_mam_cab_o (1'b0),
.wb_mam_cti_o (mam_dm_cti_o),
.wb_mam_bte_o (mam_dm_bte_o),
.wb_mam_ack_i (mam_dm_ack_i),
.wb_mam_rty_i (mam_dm_rty_i),
.wb_mam_err_i (mam_dm_err_i),
.wb_mam_dat_i (mam_dm_dat_i),
/*AUTOINST*/
// Outputs
.wb_in_ack_o (bussl_ack_o[SLAVE_DM]), // Templated
.wb_in_err_o (bussl_err_o[SLAVE_DM]), // Templated
.wb_in_rty_o (bussl_rty_o[SLAVE_DM]), // Templated
.wb_in_dat_o (bussl_dat_o[SLAVE_DM]), // Templated
.wb_out_adr_i (wb_mem_adr_i), // Templated
.wb_out_bte_i (wb_mem_bte_i), // Templated
.wb_out_cti_i (wb_mem_cti_i), // Templated
.wb_out_cyc_i (wb_mem_cyc_i), // Templated
.wb_out_dat_i (wb_mem_dat_i), // Templated
.wb_out_sel_i (wb_mem_sel_i), // Templated
.wb_out_stb_i (wb_mem_stb_i), // Templated
.wb_out_we_i (wb_mem_we_i), // Templated
.wb_out_clk_i (wb_mem_clk_i), // Templated
.wb_out_rst_i (wb_mem_rst_i), // Templated
// Inputs
.wb_in_adr_i (bussl_adr_i[SLAVE_DM]), // Templated
.wb_in_bte_i (bussl_bte_i[SLAVE_DM]), // Templated
.wb_in_cti_i (bussl_cti_i[SLAVE_DM]), // Templated
.wb_in_cyc_i (bussl_cyc_i[SLAVE_DM]), // Templated
.wb_in_dat_i (bussl_dat_i[SLAVE_DM]), // Templated
.wb_in_sel_i (bussl_sel_i[SLAVE_DM]), // Templated
.wb_in_stb_i (bussl_stb_i[SLAVE_DM]), // Templated
.wb_in_we_i (bussl_we_i[SLAVE_DM]), // Templated
.wb_in_clk_i (clk), // Templated
.wb_in_rst_i (rst_sys), // Templated
.wb_out_ack_o (wb_mem_ack_o), // Templated
.wb_out_err_o (wb_mem_err_o), // Templated
.wb_out_rty_o (wb_mem_rty_o), // Templated
.wb_out_dat_o (wb_mem_dat_o)); // Templated
end else begin // if (CONFIG.ENABLE_DM)
assign mam_dm_dat_i = 32'hx;
assign {mam_dm_ack_i, mam_dm_err_i, mam_dm_rty_i} = 3'b000;
assign bussl_dat_o[SLAVE_DM] = 32'hx;
assign bussl_ack_o[SLAVE_DM] = 1'b0;
assign bussl_err_o[SLAVE_DM] = 1'b0;
assign bussl_rty_o[SLAVE_DM] = 1'b0;
end
if (!CONFIG.ENABLE_PGAS) begin : gen_tieoff_pgas
assign bussl_dat_o[SLAVE_PGAS] = 32'h0;
assign bussl_ack_o[SLAVE_PGAS] = 1'b0;
assign bussl_err_o[SLAVE_PGAS] = 1'b0;
assign bussl_rty_o[SLAVE_PGAS] = 1'b0;
end
generate
if ((CONFIG.ENABLE_DM) &&
(CONFIG.LMEM_STYLE == PLAIN)) begin : gen_sram
/* wb_sram_sp AUTO_TEMPLATE(
.wb_\(.*\) (wb_mem_\1),
); */
wb_sram_sp
#(.DW(32),
.AW(clog2_width(CONFIG.LMEM_SIZE)),
.MEM_SIZE_BYTE(CONFIG.LMEM_SIZE),
.MEM_FILE(MEM_FILE),
.MEM_IMPL_TYPE("PLAIN")
)
u_ram(/*AUTOINST*/
// Outputs
.wb_ack_o (wb_mem_ack_o),
.wb_err_o (wb_mem_err_o),
.wb_rty_o (wb_mem_rty_o),
.wb_dat_o (wb_mem_dat_o),
// Inputs
.wb_adr_i (wb_mem_adr_i[clog2_width(CONFIG.LMEM_SIZE)-1:0]),
.wb_bte_i (wb_mem_bte_i),
.wb_cti_i (wb_mem_cti_i),
.wb_cyc_i (wb_mem_cyc_i),
.wb_dat_i (wb_mem_dat_i),
.wb_sel_i (wb_mem_sel_i),
.wb_stb_i (wb_mem_stb_i),
.wb_we_i (wb_mem_we_i),
.wb_clk_i (wb_mem_clk_i),
.wb_rst_i (wb_mem_rst_i));
end else begin // block: gen_sram
assign wb_ext_adr_i = wb_mem_adr_i;
assign wb_ext_bte_i = wb_mem_bte_i;
assign wb_ext_cti_i = wb_mem_cti_i;
assign wb_ext_cyc_i = wb_mem_cyc_i;
assign wb_ext_dat_i = wb_mem_dat_i;
assign wb_ext_sel_i = wb_mem_sel_i;
assign wb_ext_stb_i = wb_mem_stb_i;
assign wb_ext_we_i = wb_mem_we_i;
assign wb_mem_ack_o = wb_ext_ack_o;
assign wb_mem_rty_o = wb_ext_rty_o;
assign wb_mem_err_o = wb_ext_err_o;
assign wb_mem_dat_o = wb_ext_dat_o;
end // else: !if((CONFIG.ENABLE_DM) &&...
endgenerate
networkadapter_ct
#(.CONFIG(CONFIG),
.TILEID(ID),
.COREBASE(COREBASE))
u_na(
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
.cdc_conf (cdc_conf[2:0]),
.cdc_enable (cdc_enable),
`endif
`endif
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[SLAVE_NA]),
.wbs_rty_o (bussl_rty_o[SLAVE_NA]),
.wbs_err_o (bussl_err_o[SLAVE_NA]),
.wbs_dat_o (bussl_dat_o[SLAVE_NA]),
.irq (pic_ints_i[0][4:3]),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[SLAVE_NA]),
.wbs_cyc_i (bussl_cyc_i[SLAVE_NA]),
.wbs_dat_i (bussl_dat_i[SLAVE_NA]),
.wbs_sel_i (bussl_sel_i[SLAVE_NA]),
.wbs_stb_i (bussl_stb_i[SLAVE_NA]),
.wbs_we_i (bussl_we_i[SLAVE_NA]),
.wbs_cab_i (bussl_cab_i[SLAVE_NA]),
.wbs_cti_i (bussl_cti_i[SLAVE_NA]),
.wbs_bte_i (bussl_bte_i[SLAVE_NA]));
// generate
// if (CONFIG.ENABLE_BOOTROM) begin : gen_bootrom
// /* bootrom AUTO_TEMPLATE(
// .clk(clk),
// .rst(rst_sys),
// .wb_\(.*\) (bussl_\1[SLAVE_BOOT]),
// ); */
// bootrom
// u_bootrom
// (/*AUTOINST*/
// // Outputs
// .wb_dat_o (bussl_dat_o[SLAVE_BOOT]), // Templated
// .wb_ack_o (bussl_ack_o[SLAVE_BOOT]), // Templated
// .wb_err_o (bussl_err_o[SLAVE_BOOT]), // Templated
// .wb_rty_o (bussl_rty_o[SLAVE_BOOT]), // Templated
// // Inputs
// .clk (clk), // Templated
// .rst (rst_sys), // Templated
// .wb_adr_i (bussl_adr_i[SLAVE_BOOT]), // Templated
// .wb_dat_i (bussl_dat_i[SLAVE_BOOT]), // Templated
// .wb_cyc_i (bussl_cyc_i[SLAVE_BOOT]), // Templated
// .wb_stb_i (bussl_stb_i[SLAVE_BOOT]), // Templated
// .wb_sel_i (bussl_sel_i[SLAVE_BOOT])); // Templated
// end else begin // if (CONFIG.ENABLE_BOOTROM)
// assign bussl_dat_o[SLAVE_BOOT] = 32'hx;
// assign bussl_ack_o[SLAVE_BOOT] = 1'b0;
// assign bussl_err_o[SLAVE_BOOT] = 1'b0;
// assign bussl_rty_o[SLAVE_BOOT] = 1'b0;
// end // else: !if(CONFIG.ENABLE_BOOTROM)
// endgenerate
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the compute tile for distributed memory systems.
*
*
* The assignment of the 32 bit IRQ vector connected to core 0 is as follows:
* - Bit [1:0]: N/A
* - Bit 2: UART
* - Bit 3: NA - message passing
* - Bit 4: NA - DMA
* - Bit [31:5]: N/A
*
* The address ranges of the bus slaves are as follows:
* - Slave 0 - DM: 0x00000000-0x7fffffff
* - Slave 1 - PGAS: not used
* - Slave 2 - NA: 0xe0000000-0xefffffff
* - Slave 3 - BOOT: 0xf0000000-0xffffffff
* - Slave 4 - UART: 0x90000000-0x9000000f
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module cpusubsys1
import dii_package::dii_flit;
import opensocdebug::mor1kx_trace_exec;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
parameter ID = 'x,
parameter COREBASE = 'x,
parameter DEBUG_BASEID = 'x,
parameter MEM_FILE = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH
)
(
input dii_flit [1:0] debug_ring_in,
output [1:0] debug_ring_in_ready,
output dii_flit [1:0] debug_ring_out,
input [1:0] debug_ring_out_ready,
output [31:0] wb_ext_adr_i,
output wb_ext_cyc_i,
output [31:0] wb_ext_dat_i,
output [3:0] wb_ext_sel_i,
output wb_ext_stb_i,
output wb_ext_we_i,
output wb_ext_cab_i,
output [2:0] wb_ext_cti_i,
output [1:0] wb_ext_bte_i,
input wb_ext_ack_o,
input wb_ext_rty_o,
input wb_ext_err_o,
input [31:0] wb_ext_dat_o,
input clk,
input rst_cpu, rst_sys, rst_dbg,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
import optimsoc_functions::*;
localparam NR_MASTERS = 2;
localparam NR_SLAVES = 3;
localparam SLAVE_NA = 0;
localparam SLAVE_DM = 1;
localparam SLAVE_PGAS = 2;
mor1kx_trace_exec [CONFIG.CORES_PER_TILE-1:0] trace;
logic wb_mem_clk_i;
logic wb_mem_rst_i;
logic [31:0] wb_mem_adr_i;
logic wb_mem_cyc_i;
logic [31:0] wb_mem_dat_i;
logic [3:0] wb_mem_sel_i;
logic wb_mem_stb_i;
logic wb_mem_we_i;
logic wb_mem_cab_i;
logic [2:0] wb_mem_cti_i;
logic [1:0] wb_mem_bte_i;
logic wb_mem_ack_o;
logic wb_mem_rty_o;
logic wb_mem_err_o;
logic [31:0] wb_mem_dat_o;
// create DI ring segment with routers
localparam DEBUG_MODS_PER_TILE_NONZERO = (CONFIG.DEBUG_MODS_PER_TILE == 0) ? 1 : CONFIG.DEBUG_MODS_PER_TILE;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in_ready;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out_ready;
generate
if (CONFIG.USE_DEBUG == 1) begin : gen_debug_ring
genvar i;
logic [CONFIG.DEBUG_MODS_PER_TILE-1:0][15:0] id_map;
for (i = 0; i < CONFIG.DEBUG_MODS_PER_TILE; i = i+1) begin
assign id_map[i][15:0] = 16'(DEBUG_BASEID+i);
end
debug_ring_expand
#(.BUFFER_SIZE(CONFIG.DEBUG_ROUTER_BUFFER_SIZE),
.PORTS(CONFIG.DEBUG_MODS_PER_TILE))
u_debug_ring_segment
(.clk (clk),
.rst (rst_dbg),
.id_map (id_map),
.dii_in (dii_in),
.dii_in_ready (dii_in_ready),
.dii_out (dii_out),
.dii_out_ready (dii_out_ready),
.ext_in (debug_ring_in),
.ext_in_ready (debug_ring_in_ready),
.ext_out (debug_ring_out),
.ext_out_ready (debug_ring_out_ready));
end // if (USE_DEBUG)
endgenerate
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
wire [31:0] pic_ints_i [0:CONFIG.CORES_PER_TILE-1];
assign pic_ints_i[0][31:5] = 27'h0;
assign pic_ints_i[0][1:0] = 2'b00;
genvar m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* generate
for (c = 1; c < CONFIG.CORES_PER_TILE; c = c + 1) begin
assign pic_ints_i[c] = 32'h0;
end
endgenerate*/
localparam c0 = 0;
picorv32_wb_ic
// #(.ID(c0),
// .NUMCORES(1)
// )
RV32IC
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wbm_adr_o (busms_adr_o[c0*2][31:0]), // Templated
.wbm_dat_i (busms_dat_i[c0*2+1][31:0]), // Templated
.wbm_cyc_o (busms_cyc_o[c0*2+1]), // Templated
.wbm_stb_o (busms_stb_o[c0*2+1]), // Templated
.wbm_we_o (busms_we_o[c0*2+1]), // Templated
.wbm_dat_o (busms_dat_o[c0*2+1][31:0]), // Templated
.wbm_ack_i (busms_ack_i[c0*2+1]), // Templated
.wbm_sel_o ()
//.wbm_err_o (busms_err_o)
); // Templated
assign busms_cab_o[c0*2] = 1'b0;
assign busms_cab_o[c0*2+1] = 1'b0;
/*if (CONFIG.USE_DEBUG == 1) begin : gen_ctm_stm
osd_stm_mor1kx
#(.MAX_PKT_LEN(CONFIG.DEBUG_MAX_PKT_LEN))
u_stm
(.clk (clk),
.rst (rst_dbg),
.id (16'(DEBUG_BASEID + 1 + c*CONFIG.DEBUG_MODS_PER_CORE)),
.debug_in (dii_out[1+c*CONFIG.DEBUG_MODS_PER_CORE]),
.debug_in_ready (dii_out_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE]),
.debug_out (dii_in[1+c*CONFIG.DEBUG_MODS_PER_CORE]),
.debug_out_ready (dii_in_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE]),
.trace_port (trace[c]));
osd_ctm_mor1kx
#(.MAX_PKT_LEN(CONFIG.DEBUG_MAX_PKT_LEN))
u_ctm
(.clk (clk),
.rst (rst_dbg),
.id (16'(DEBUG_BASEID + 1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1)),
.debug_in (dii_out[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.debug_in_ready (dii_out_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.debug_out (dii_in[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.debug_out_ready (dii_in_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.trace_port (trace[c]));
end*/
localparam c1 = 1;
picorv32_wb_i
// #(.ID(c1),
// .NUMCORES(1)
// )
RV32I
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wbm_adr_o (busms_adr_o[c1*2][31:0]), // Templated
.wbm_dat_i (busms_dat_i[c1*2+1][31:0]), // Templated
.wbm_cyc_o (busms_cyc_o[c1*2+1]), // Templated
.wbm_stb_o (busms_stb_o[c1*2+1]), // Templated
.wbm_we_o (busms_we_o[c1*2+1]), // Templated
.wbm_dat_o (busms_dat_o[c1*2+1][31:0]), // Templated
.wbm_ack_i (busms_ack_i[c1*2+1]), // Templated
.wbm_sel_o ()
//.wbm_err_o (busms_err_o)
); // Templated
assign busms_cab_o[c1*2] = 1'b0;
assign busms_cab_o[c1*2+1] = 1'b0;
/*if (CONFIG.USE_DEBUG == 1) begin : gen_ctm_stm
osd_stm_mor1kx
#(.MAX_PKT_LEN(CONFIG.DEBUG_MAX_PKT_LEN))
u_stm
(.clk (clk),
.rst (rst_dbg),
.id (16'(DEBUG_BASEID + 1 + c*CONFIG.DEBUG_MODS_PER_CORE)),
.debug_in (dii_out[1+c*CONFIG.DEBUG_MODS_PER_CORE]),
.debug_in_ready (dii_out_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE]),
.debug_out (dii_in[1+c*CONFIG.DEBUG_MODS_PER_CORE]),
.debug_out_ready (dii_in_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE]),
.trace_port (trace[c]));
osd_ctm_mor1kx
#(.MAX_PKT_LEN(CONFIG.DEBUG_MAX_PKT_LEN))
u_ctm
(.clk (clk),
.rst (rst_dbg),
.id (16'(DEBUG_BASEID + 1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1)),
.debug_in (dii_out[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.debug_in_ready (dii_out_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.debug_out (dii_in[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.debug_out_ready (dii_in_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.trace_port (trace[c]));
end*/
/* generate
if (CONFIG.USE_DEBUG != 0 && CONFIG.DEBUG_DEM_UART != 0) begin : gen_dem_uart
osd_dem_uart_wb
u_dem_uart(
.clk (clk),
.rst (rst_sys),
.id (16'(DEBUG_BASEID + CONFIG.DEBUG_MODS_PER_TILE - 1)),
.irq (pic_ints_i[0][2]),
.debug_in (dii_out[CONFIG.DEBUG_MODS_PER_TILE - 1]),
.debug_in_ready (dii_out_ready[CONFIG.DEBUG_MODS_PER_TILE - 1]),
.debug_out (dii_in[CONFIG.DEBUG_MODS_PER_TILE - 1]),
.debug_out_ready (dii_in_ready[CONFIG.DEBUG_MODS_PER_TILE - 1]),
.wb_adr_i (bussl_adr_i[SLAVE_UART][3:0]),
.wb_cyc_i (bussl_cyc_i[SLAVE_UART]),
.wb_dat_i (bussl_dat_i[SLAVE_UART]),
.wb_sel_i (bussl_sel_i[SLAVE_UART]),
.wb_stb_i (bussl_stb_i[SLAVE_UART]),
.wb_we_i (bussl_we_i[SLAVE_UART]),
.wb_cti_i (bussl_cti_i[SLAVE_UART]),
.wb_bte_i (bussl_bte_i[SLAVE_UART]),
.wb_ack_o (bussl_ack_o[SLAVE_UART]),
.wb_err_o (bussl_err_o[SLAVE_UART]),
.wb_rty_o (bussl_rty_o[SLAVE_UART]),
.wb_dat_o (bussl_dat_o[SLAVE_UART]));
end
endgenerate */
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
#(.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(CONFIG.ENABLE_DM),
.S0_RANGE_WIDTH(CONFIG.DM_RANGE_WIDTH),.S0_RANGE_MATCH(CONFIG.DM_RANGE_MATCH),
.S1_ENABLE(CONFIG.ENABLE_PGAS),
.S1_RANGE_WIDTH(CONFIG.PGAS_RANGE_WIDTH),.S1_RANGE_MATCH(CONFIG.PGAS_RANGE_MATCH),
.S2_RANGE_WIDTH(4),.S2_RANGE_MATCH(4'he),
.S3_ENABLE(CONFIG.ENABLE_BOOTROM),
.S3_RANGE_WIDTH(4),.S3_RANGE_MATCH(4'hf)
// .S4_ENABLE(CONFIG.DEBUG_DEM_UART),
// .S4_RANGE_WIDTH(28),.S4_RANGE_MATCH(28'h9000000)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
//MAM - WB adapter signals
logic mam_dm_stb_o;
logic mam_dm_cyc_o;
logic mam_dm_ack_i;
logic mam_dm_err_i;
logic mam_dm_rty_i;
logic mam_dm_we_o;
logic [31:0] mam_dm_addr_o;
logic [31:0] mam_dm_dat_o;
logic [31:0] mam_dm_dat_i;
logic [2:0] mam_dm_cti_o;
logic [1:0] mam_dm_bte_o;
logic [3:0] mam_dm_sel_o;
if (CONFIG.USE_DEBUG == 1) begin : gen_mam_dm_wb
//MAM
osd_mam_wb #(
.DATA_WIDTH(32),
.MAX_PKT_LEN(CONFIG.DEBUG_MAX_PKT_LEN),
.MEM_SIZE0(CONFIG.LMEM_SIZE),
.BASE_ADDR0(0))
u_mam_dm_wb(
.clk_i(clk),
.rst_i(rst_dbg),
.debug_in(dii_out[0]),
.debug_in_ready(dii_out_ready[0]),
.debug_out(dii_in[0]),
.debug_out_ready(dii_in_ready[0]),
.id (16'(DEBUG_BASEID)),
.stb_o(mam_dm_stb_o),
.cyc_o(mam_dm_cyc_o),
.ack_i(mam_dm_ack_i),
.we_o(mam_dm_we_o),
.addr_o(mam_dm_addr_o),
.dat_o(mam_dm_dat_o),
.dat_i(mam_dm_dat_i),
.cti_o(mam_dm_cti_o),
.bte_o(mam_dm_bte_o),
.sel_o(mam_dm_sel_o));
end //if (USE_DEBUG == 1)
if (CONFIG.ENABLE_DM) begin : gen_mam_wb_adapter
/* mam_wb_adapter AUTO_TEMPLATE(
.wb_in_clk_i (clk),
.wb_in_rst_i (rst_sys),
.wb_in_\(.*\) (bussl_\1[SLAVE_DM]),
.wb_out_\(.*\) (wb_mem_\1),
); */
mam_wb_adapter
#(.DW(32),
.AW(32))
u_mam_wb_adapter_dm
(
.wb_mam_adr_o (mam_dm_addr_o),
.wb_mam_cyc_o (mam_dm_cyc_o),
.wb_mam_dat_o (mam_dm_dat_o),
.wb_mam_sel_o (mam_dm_sel_o),
.wb_mam_stb_o (mam_dm_stb_o),
.wb_mam_we_o (mam_dm_we_o),
.wb_mam_cab_o (1'b0),
.wb_mam_cti_o (mam_dm_cti_o),
.wb_mam_bte_o (mam_dm_bte_o),
.wb_mam_ack_i (mam_dm_ack_i),
.wb_mam_rty_i (mam_dm_rty_i),
.wb_mam_err_i (mam_dm_err_i),
.wb_mam_dat_i (mam_dm_dat_i),
/*AUTOINST*/
// Outputs
.wb_in_ack_o (bussl_ack_o[SLAVE_DM]), // Templated
.wb_in_err_o (bussl_err_o[SLAVE_DM]), // Templated
.wb_in_rty_o (bussl_rty_o[SLAVE_DM]), // Templated
.wb_in_dat_o (bussl_dat_o[SLAVE_DM]), // Templated
.wb_out_adr_i (wb_mem_adr_i), // Templated
.wb_out_bte_i (wb_mem_bte_i), // Templated
.wb_out_cti_i (wb_mem_cti_i), // Templated
.wb_out_cyc_i (wb_mem_cyc_i), // Templated
.wb_out_dat_i (wb_mem_dat_i), // Templated
.wb_out_sel_i (wb_mem_sel_i), // Templated
.wb_out_stb_i (wb_mem_stb_i), // Templated
.wb_out_we_i (wb_mem_we_i), // Templated
.wb_out_clk_i (wb_mem_clk_i), // Templated
.wb_out_rst_i (wb_mem_rst_i), // Templated
// Inputs
.wb_in_adr_i (bussl_adr_i[SLAVE_DM]), // Templated
.wb_in_bte_i (bussl_bte_i[SLAVE_DM]), // Templated
.wb_in_cti_i (bussl_cti_i[SLAVE_DM]), // Templated
.wb_in_cyc_i (bussl_cyc_i[SLAVE_DM]), // Templated
.wb_in_dat_i (bussl_dat_i[SLAVE_DM]), // Templated
.wb_in_sel_i (bussl_sel_i[SLAVE_DM]), // Templated
.wb_in_stb_i (bussl_stb_i[SLAVE_DM]), // Templated
.wb_in_we_i (bussl_we_i[SLAVE_DM]), // Templated
.wb_in_clk_i (clk), // Templated
.wb_in_rst_i (rst_sys), // Templated
.wb_out_ack_o (wb_mem_ack_o), // Templated
.wb_out_err_o (wb_mem_err_o), // Templated
.wb_out_rty_o (wb_mem_rty_o), // Templated
.wb_out_dat_o (wb_mem_dat_o)); // Templated
end else begin // if (CONFIG.ENABLE_DM)
assign mam_dm_dat_i = 32'hx;
assign {mam_dm_ack_i, mam_dm_err_i, mam_dm_rty_i} = 3'b000;
assign bussl_dat_o[SLAVE_DM] = 32'hx;
assign bussl_ack_o[SLAVE_DM] = 1'b0;
assign bussl_err_o[SLAVE_DM] = 1'b0;
assign bussl_rty_o[SLAVE_DM] = 1'b0;
end
if (!CONFIG.ENABLE_PGAS) begin : gen_tieoff_pgas
assign bussl_dat_o[SLAVE_PGAS] = 32'h0;
assign bussl_ack_o[SLAVE_PGAS] = 1'b0;
assign bussl_err_o[SLAVE_PGAS] = 1'b0;
assign bussl_rty_o[SLAVE_PGAS] = 1'b0;
end
generate
if ((CONFIG.ENABLE_DM) &&
(CONFIG.LMEM_STYLE == PLAIN)) begin : gen_sram
/* wb_sram_sp AUTO_TEMPLATE(
.wb_\(.*\) (wb_mem_\1),
); */
wb_sram_sp
#(.DW(32),
.AW(clog2_width(CONFIG.LMEM_SIZE)),
.MEM_SIZE_BYTE(CONFIG.LMEM_SIZE),
.MEM_FILE(MEM_FILE),
.MEM_IMPL_TYPE("PLAIN")
)
u_ram(/*AUTOINST*/
// Outputs
.wb_ack_o (wb_mem_ack_o),
.wb_err_o (wb_mem_err_o),
.wb_rty_o (wb_mem_rty_o),
.wb_dat_o (wb_mem_dat_o),
// Inputs
.wb_adr_i (wb_mem_adr_i[clog2_width(CONFIG.LMEM_SIZE)-1:0]),
.wb_bte_i (wb_mem_bte_i),
.wb_cti_i (wb_mem_cti_i),
.wb_cyc_i (wb_mem_cyc_i),
.wb_dat_i (wb_mem_dat_i),
.wb_sel_i (wb_mem_sel_i),
.wb_stb_i (wb_mem_stb_i),
.wb_we_i (wb_mem_we_i),
.wb_clk_i (wb_mem_clk_i),
.wb_rst_i (wb_mem_rst_i));
end else begin // block: gen_sram
assign wb_ext_adr_i = wb_mem_adr_i;
assign wb_ext_bte_i = wb_mem_bte_i;
assign wb_ext_cti_i = wb_mem_cti_i;
assign wb_ext_cyc_i = wb_mem_cyc_i;
assign wb_ext_dat_i = wb_mem_dat_i;
assign wb_ext_sel_i = wb_mem_sel_i;
assign wb_ext_stb_i = wb_mem_stb_i;
assign wb_ext_we_i = wb_mem_we_i;
assign wb_mem_ack_o = wb_ext_ack_o;
assign wb_mem_rty_o = wb_ext_rty_o;
assign wb_mem_err_o = wb_ext_err_o;
assign wb_mem_dat_o = wb_ext_dat_o;
end // else: !if((CONFIG.ENABLE_DM) &&...
endgenerate
networkadapter_ct
#(.CONFIG(CONFIG),
.TILEID(ID),
.COREBASE(COREBASE))
u_na(
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
.cdc_conf (cdc_conf[2:0]),
.cdc_enable (cdc_enable),
`endif
`endif
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[SLAVE_NA]),
.wbs_rty_o (bussl_rty_o[SLAVE_NA]),
.wbs_err_o (bussl_err_o[SLAVE_NA]),
.wbs_dat_o (bussl_dat_o[SLAVE_NA]),
.irq (pic_ints_i[0][4:3]),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[SLAVE_NA]),
.wbs_cyc_i (bussl_cyc_i[SLAVE_NA]),
.wbs_dat_i (bussl_dat_i[SLAVE_NA]),
.wbs_sel_i (bussl_sel_i[SLAVE_NA]),
.wbs_stb_i (bussl_stb_i[SLAVE_NA]),
.wbs_we_i (bussl_we_i[SLAVE_NA]),
.wbs_cab_i (bussl_cab_i[SLAVE_NA]),
.wbs_cti_i (bussl_cti_i[SLAVE_NA]),
.wbs_bte_i (bussl_bte_i[SLAVE_NA]));
// generate
// if (CONFIG.ENABLE_BOOTROM) begin : gen_bootrom
// /* bootrom AUTO_TEMPLATE(
// .clk(clk),
// .rst(rst_sys),
// .wb_\(.*\) (bussl_\1[SLAVE_BOOT]),
// ); */
// bootrom
// u_bootrom
// (/*AUTOINST*/
// // Outputs
// .wb_dat_o (bussl_dat_o[SLAVE_BOOT]), // Templated
// .wb_ack_o (bussl_ack_o[SLAVE_BOOT]), // Templated
// .wb_err_o (bussl_err_o[SLAVE_BOOT]), // Templated
// .wb_rty_o (bussl_rty_o[SLAVE_BOOT]), // Templated
// // Inputs
// .clk (clk), // Templated
// .rst (rst_sys), // Templated
// .wb_adr_i (bussl_adr_i[SLAVE_BOOT]), // Templated
// .wb_dat_i (bussl_dat_i[SLAVE_BOOT]), // Templated
// .wb_cyc_i (bussl_cyc_i[SLAVE_BOOT]), // Templated
// .wb_stb_i (bussl_stb_i[SLAVE_BOOT]), // Templated
// .wb_sel_i (bussl_sel_i[SLAVE_BOOT])); // Templated
// end else begin // if (CONFIG.ENABLE_BOOTROM)
// assign bussl_dat_o[SLAVE_BOOT] = 32'hx;
// assign bussl_ack_o[SLAVE_BOOT] = 1'b0;
// assign bussl_err_o[SLAVE_BOOT] = 1'b0;
// assign bussl_rty_o[SLAVE_BOOT] = 1'b0;
// end // else: !if(CONFIG.ENABLE_BOOTROM)
// endgenerate
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the compute tile for distributed memory systems.
*
*
* The assignment of the 32 bit IRQ vector connected to core 0 is as follows:
* - Bit [1:0]: N/A
* - Bit 2: UART
* - Bit 3: NA - message passing
* - Bit 4: NA - DMA
* - Bit [31:5]: N/A
*
* The address ranges of the bus slaves are as follows:
* - Slave 0 - DM: 0x00000000-0x7fffffff
* - Slave 1 - PGAS: not used
* - Slave 2 - NA: 0xe0000000-0xefffffff
* - Slave 3 - BOOT: 0xf0000000-0xffffffff
* - Slave 4 - UART: 0x90000000-0x9000000f
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module cpusubsys2
import dii_package::dii_flit;
import opensocdebug::mor1kx_trace_exec;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
parameter ID = 'x,
parameter COREBASE = 'x,
parameter DEBUG_BASEID = 'x,
parameter MEM_FILE = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH
)
(
input dii_flit [1:0] debug_ring_in,
output [1:0] debug_ring_in_ready,
output dii_flit [1:0] debug_ring_out,
input [1:0] debug_ring_out_ready,
output [31:0] wb_ext_adr_i,
output wb_ext_cyc_i,
output [31:0] wb_ext_dat_i,
output [3:0] wb_ext_sel_i,
output wb_ext_stb_i,
output wb_ext_we_i,
output wb_ext_cab_i,
output [2:0] wb_ext_cti_i,
output [1:0] wb_ext_bte_i,
input wb_ext_ack_o,
input wb_ext_rty_o,
input wb_ext_err_o,
input [31:0] wb_ext_dat_o,
input clk,
input rst_cpu, rst_sys, rst_dbg,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
import optimsoc_functions::*;
localparam NR_MASTERS = 2;
localparam NR_SLAVES = 3;
localparam SLAVE_NA = 0;
localparam SLAVE_DM = 1;
localparam SLAVE_PGAS = 2;
mor1kx_trace_exec [CONFIG.CORES_PER_TILE-1:0] trace;
logic wb_mem_clk_i;
logic wb_mem_rst_i;
logic [31:0] wb_mem_adr_i;
logic wb_mem_cyc_i;
logic [31:0] wb_mem_dat_i;
logic [3:0] wb_mem_sel_i;
logic wb_mem_stb_i;
logic wb_mem_we_i;
logic wb_mem_cab_i;
logic [2:0] wb_mem_cti_i;
logic [1:0] wb_mem_bte_i;
logic wb_mem_ack_o;
logic wb_mem_rty_o;
logic wb_mem_err_o;
logic [31:0] wb_mem_dat_o;
// create DI ring segment with routers
localparam DEBUG_MODS_PER_TILE_NONZERO = (CONFIG.DEBUG_MODS_PER_TILE == 0) ? 1 : CONFIG.DEBUG_MODS_PER_TILE;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in_ready;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out_ready;
generate
if (CONFIG.USE_DEBUG == 1) begin : gen_debug_ring
genvar i;
logic [CONFIG.DEBUG_MODS_PER_TILE-1:0][15:0] id_map;
for (i = 0; i < CONFIG.DEBUG_MODS_PER_TILE; i = i+1) begin
assign id_map[i][15:0] = 16'(DEBUG_BASEID+i);
end
debug_ring_expand
#(.BUFFER_SIZE(CONFIG.DEBUG_ROUTER_BUFFER_SIZE),
.PORTS(CONFIG.DEBUG_MODS_PER_TILE))
u_debug_ring_segment
(.clk (clk),
.rst (rst_dbg),
.id_map (id_map),
.dii_in (dii_in),
.dii_in_ready (dii_in_ready),
.dii_out (dii_out),
.dii_out_ready (dii_out_ready),
.ext_in (debug_ring_in),
.ext_in_ready (debug_ring_in_ready),
.ext_out (debug_ring_out),
.ext_out_ready (debug_ring_out_ready));
end // if (USE_DEBUG)
endgenerate
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
wire [31:0] pic_ints_i [0:CONFIG.CORES_PER_TILE-1];
assign pic_ints_i[0][31:5] = 27'h0;
assign pic_ints_i[0][1:0] = 2'b00;
genvar c, m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* generate
for (c = 1; c < CONFIG.CORES_PER_TILE; c = c + 1) begin
assign pic_ints_i[c] = 32'h0;
end
endgenerate*/
localparam c3 = 3;
picorv32_wb_imc
// #(.ID(c3),
// .NUMCORES(1)
// )
RV32IMC
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wbm_adr_o (busms_adr_o[c3*2][31:0]), // Templated
.wbm_dat_i (busms_dat_i[c3*2+1][31:0]), // Templated
.wbm_cyc_o (busms_cyc_o[c3*2+1]), // Templated
.wbm_stb_o (busms_stb_o[c3*2+1]), // Templated
.wbm_we_o (busms_we_o[c3*2+1]), // Templated
.wbm_dat_o (busms_dat_o[c3*2+1][31:0]), // Templated
.wbm_ack_i (busms_ack_i[c3*2+1]), // Templated
.wbm_sel_o ()
//.wbm_err_o (busms_err_o)
); // Templated
assign busms_cab_o[c3*2] = 1'b0;
assign busms_cab_o[c3*2+1] = 1'b0;
/* if (CONFIG.USE_DEBUG == 1) begin : gen_ctm_stm
osd_stm_mor1kx
#(.MAX_PKT_LEN(CONFIG.DEBUG_MAX_PKT_LEN))
u_stm
(.clk (clk),
.rst (rst_dbg),
.id (16'(DEBUG_BASEID + 1 + c*CONFIG.DEBUG_MODS_PER_CORE)),
.debug_in (dii_out[1+c*CONFIG.DEBUG_MODS_PER_CORE]),
.debug_in_ready (dii_out_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE]),
.debug_out (dii_in[1+c*CONFIG.DEBUG_MODS_PER_CORE]),
.debug_out_ready (dii_in_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE]),
.trace_port (trace[c]));
osd_ctm_mor1kx
#(.MAX_PKT_LEN(CONFIG.DEBUG_MAX_PKT_LEN))
u_ctm
(.clk (clk),
.rst (rst_dbg),
.id (16'(DEBUG_BASEID + 1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1)),
.debug_in (dii_out[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.debug_in_ready (dii_out_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.debug_out (dii_in[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.debug_out_ready (dii_in_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.trace_port (trace[c]));
end*/
localparam c2 = 2;
picorv32_wb_im
// #(.ID(c2),
// .NUMCORES(1)
// )
RV32IM
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wbm_adr_o (busms_adr_o[c2*2][31:0]), // Templated
.wbm_dat_i (busms_dat_i[c2*2+1][31:0]), // Templated
.wbm_cyc_o (busms_cyc_o[c2*2+1]), // Templated
.wbm_stb_o (busms_stb_o[c2*2+1]), // Templated
.wbm_we_o (busms_we_o[c2*2+1]), // Templated
.wbm_dat_o (busms_dat_o[c2*2+1][31:0]), // Templated
.wbm_ack_i (busms_ack_i[c2*2+1]), // Templated
.wbm_sel_o ()
//.wbm_err_o (busms_err_o)
); // Templated
assign busms_cab_o[c2*2] = 1'b0;
assign busms_cab_o[c2*2+1] = 1'b0;
/* if (CONFIG.USE_DEBUG == 1) begin : gen_ctm_stm
osd_stm_mor1kx
#(.MAX_PKT_LEN(CONFIG.DEBUG_MAX_PKT_LEN))
u_stm
(.clk (clk),
.rst (rst_dbg),
.id (16'(DEBUG_BASEID + 1 + c*CONFIG.DEBUG_MODS_PER_CORE)),
.debug_in (dii_out[1+c*CONFIG.DEBUG_MODS_PER_CORE]),
.debug_in_ready (dii_out_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE]),
.debug_out (dii_in[1+c*CONFIG.DEBUG_MODS_PER_CORE]),
.debug_out_ready (dii_in_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE]),
.trace_port (trace[c]));
osd_ctm_mor1kx
#(.MAX_PKT_LEN(CONFIG.DEBUG_MAX_PKT_LEN))
u_ctm
(.clk (clk),
.rst (rst_dbg),
.id (16'(DEBUG_BASEID + 1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1)),
.debug_in (dii_out[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.debug_in_ready (dii_out_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.debug_out (dii_in[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.debug_out_ready (dii_in_ready[1 + c*CONFIG.DEBUG_MODS_PER_CORE + 1]),
.trace_port (trace[c]));
end*/
/* generate
if (CONFIG.USE_DEBUG != 0 && CONFIG.DEBUG_DEM_UART != 0) begin : gen_dem_uart
osd_dem_uart_wb
u_dem_uart(
.clk (clk),
.rst (rst_sys),
.id (16'(DEBUG_BASEID + CONFIG.DEBUG_MODS_PER_TILE - 1)),
.irq (pic_ints_i[0][2]),
.debug_in (dii_out[CONFIG.DEBUG_MODS_PER_TILE - 1]),
.debug_in_ready (dii_out_ready[CONFIG.DEBUG_MODS_PER_TILE - 1]),
.debug_out (dii_in[CONFIG.DEBUG_MODS_PER_TILE - 1]),
.debug_out_ready (dii_in_ready[CONFIG.DEBUG_MODS_PER_TILE - 1]),
.wb_adr_i (bussl_adr_i[SLAVE_UART][3:0]),
.wb_cyc_i (bussl_cyc_i[SLAVE_UART]),
.wb_dat_i (bussl_dat_i[SLAVE_UART]),
.wb_sel_i (bussl_sel_i[SLAVE_UART]),
.wb_stb_i (bussl_stb_i[SLAVE_UART]),
.wb_we_i (bussl_we_i[SLAVE_UART]),
.wb_cti_i (bussl_cti_i[SLAVE_UART]),
.wb_bte_i (bussl_bte_i[SLAVE_UART]),
.wb_ack_o (bussl_ack_o[SLAVE_UART]),
.wb_err_o (bussl_err_o[SLAVE_UART]),
.wb_rty_o (bussl_rty_o[SLAVE_UART]),
.wb_dat_o (bussl_dat_o[SLAVE_UART]));
end
endgenerate */
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
#(.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(CONFIG.ENABLE_DM),
.S0_RANGE_WIDTH(CONFIG.DM_RANGE_WIDTH),.S0_RANGE_MATCH(CONFIG.DM_RANGE_MATCH),
.S1_ENABLE(CONFIG.ENABLE_PGAS),
.S1_RANGE_WIDTH(CONFIG.PGAS_RANGE_WIDTH),.S1_RANGE_MATCH(CONFIG.PGAS_RANGE_MATCH),
.S2_RANGE_WIDTH(4),.S2_RANGE_MATCH(4'he),
.S3_ENABLE(CONFIG.ENABLE_BOOTROM),
.S3_RANGE_WIDTH(4),.S3_RANGE_MATCH(4'hf)
// .S4_ENABLE(CONFIG.DEBUG_DEM_UART),
// .S4_RANGE_WIDTH(28),.S4_RANGE_MATCH(28'h9000000)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
//MAM - WB adapter signals
logic mam_dm_stb_o;
logic mam_dm_cyc_o;
logic mam_dm_ack_i;
logic mam_dm_err_i;
logic mam_dm_rty_i;
logic mam_dm_we_o;
logic [31:0] mam_dm_addr_o;
logic [31:0] mam_dm_dat_o;
logic [31:0] mam_dm_dat_i;
logic [2:0] mam_dm_cti_o;
logic [1:0] mam_dm_bte_o;
logic [3:0] mam_dm_sel_o;
if (CONFIG.USE_DEBUG == 1) begin : gen_mam_dm_wb
//MAM
osd_mam_wb #(
.DATA_WIDTH(32),
.MAX_PKT_LEN(CONFIG.DEBUG_MAX_PKT_LEN),
.MEM_SIZE0(CONFIG.LMEM_SIZE),
.BASE_ADDR0(0))
u_mam_dm_wb(
.clk_i(clk),
.rst_i(rst_dbg),
.debug_in(dii_out[0]),
.debug_in_ready(dii_out_ready[0]),
.debug_out(dii_in[0]),
.debug_out_ready(dii_in_ready[0]),
.id (16'(DEBUG_BASEID)),
.stb_o(mam_dm_stb_o),
.cyc_o(mam_dm_cyc_o),
.ack_i(mam_dm_ack_i),
.we_o(mam_dm_we_o),
.addr_o(mam_dm_addr_o),
.dat_o(mam_dm_dat_o),
.dat_i(mam_dm_dat_i),
.cti_o(mam_dm_cti_o),
.bte_o(mam_dm_bte_o),
.sel_o(mam_dm_sel_o));
end //if (USE_DEBUG == 1)
if (CONFIG.ENABLE_DM) begin : gen_mam_wb_adapter
/* mam_wb_adapter AUTO_TEMPLATE(
.wb_in_clk_i (clk),
.wb_in_rst_i (rst_sys),
.wb_in_\(.*\) (bussl_\1[SLAVE_DM]),
.wb_out_\(.*\) (wb_mem_\1),
); */
mam_wb_adapter
#(.DW(32),
.AW(32))
u_mam_wb_adapter_dm
(
.wb_mam_adr_o (mam_dm_addr_o),
.wb_mam_cyc_o (mam_dm_cyc_o),
.wb_mam_dat_o (mam_dm_dat_o),
.wb_mam_sel_o (mam_dm_sel_o),
.wb_mam_stb_o (mam_dm_stb_o),
.wb_mam_we_o (mam_dm_we_o),
.wb_mam_cab_o (1'b0),
.wb_mam_cti_o (mam_dm_cti_o),
.wb_mam_bte_o (mam_dm_bte_o),
.wb_mam_ack_i (mam_dm_ack_i),
.wb_mam_rty_i (mam_dm_rty_i),
.wb_mam_err_i (mam_dm_err_i),
.wb_mam_dat_i (mam_dm_dat_i),
/*AUTOINST*/
// Outputs
.wb_in_ack_o (bussl_ack_o[SLAVE_DM]), // Templated
.wb_in_err_o (bussl_err_o[SLAVE_DM]), // Templated
.wb_in_rty_o (bussl_rty_o[SLAVE_DM]), // Templated
.wb_in_dat_o (bussl_dat_o[SLAVE_DM]), // Templated
.wb_out_adr_i (wb_mem_adr_i), // Templated
.wb_out_bte_i (wb_mem_bte_i), // Templated
.wb_out_cti_i (wb_mem_cti_i), // Templated
.wb_out_cyc_i (wb_mem_cyc_i), // Templated
.wb_out_dat_i (wb_mem_dat_i), // Templated
.wb_out_sel_i (wb_mem_sel_i), // Templated
.wb_out_stb_i (wb_mem_stb_i), // Templated
.wb_out_we_i (wb_mem_we_i), // Templated
.wb_out_clk_i (wb_mem_clk_i), // Templated
.wb_out_rst_i (wb_mem_rst_i), // Templated
// Inputs
.wb_in_adr_i (bussl_adr_i[SLAVE_DM]), // Templated
.wb_in_bte_i (bussl_bte_i[SLAVE_DM]), // Templated
.wb_in_cti_i (bussl_cti_i[SLAVE_DM]), // Templated
.wb_in_cyc_i (bussl_cyc_i[SLAVE_DM]), // Templated
.wb_in_dat_i (bussl_dat_i[SLAVE_DM]), // Templated
.wb_in_sel_i (bussl_sel_i[SLAVE_DM]), // Templated
.wb_in_stb_i (bussl_stb_i[SLAVE_DM]), // Templated
.wb_in_we_i (bussl_we_i[SLAVE_DM]), // Templated
.wb_in_clk_i (clk), // Templated
.wb_in_rst_i (rst_sys), // Templated
.wb_out_ack_o (wb_mem_ack_o), // Templated
.wb_out_err_o (wb_mem_err_o), // Templated
.wb_out_rty_o (wb_mem_rty_o), // Templated
.wb_out_dat_o (wb_mem_dat_o)); // Templated
end else begin // if (CONFIG.ENABLE_DM)
assign mam_dm_dat_i = 32'hx;
assign {mam_dm_ack_i, mam_dm_err_i, mam_dm_rty_i} = 3'b000;
assign bussl_dat_o[SLAVE_DM] = 32'hx;
assign bussl_ack_o[SLAVE_DM] = 1'b0;
assign bussl_err_o[SLAVE_DM] = 1'b0;
assign bussl_rty_o[SLAVE_DM] = 1'b0;
end
if (!CONFIG.ENABLE_PGAS) begin : gen_tieoff_pgas
assign bussl_dat_o[SLAVE_PGAS] = 32'h0;
assign bussl_ack_o[SLAVE_PGAS] = 1'b0;
assign bussl_err_o[SLAVE_PGAS] = 1'b0;
assign bussl_rty_o[SLAVE_PGAS] = 1'b0;
end
generate
if ((CONFIG.ENABLE_DM) &&
(CONFIG.LMEM_STYLE == PLAIN)) begin : gen_sram
/* wb_sram_sp AUTO_TEMPLATE(
.wb_\(.*\) (wb_mem_\1),
); */
wb_sram_sp
#(.DW(32),
.AW(clog2_width(CONFIG.LMEM_SIZE)),
.MEM_SIZE_BYTE(CONFIG.LMEM_SIZE),
.MEM_FILE(MEM_FILE),
.MEM_IMPL_TYPE("PLAIN")
)
u_ram(/*AUTOINST*/
// Outputs
.wb_ack_o (wb_mem_ack_o),
.wb_err_o (wb_mem_err_o),
.wb_rty_o (wb_mem_rty_o),
.wb_dat_o (wb_mem_dat_o),
// Inputs
.wb_adr_i (wb_mem_adr_i[clog2_width(CONFIG.LMEM_SIZE)-1:0]),
.wb_bte_i (wb_mem_bte_i),
.wb_cti_i (wb_mem_cti_i),
.wb_cyc_i (wb_mem_cyc_i),
.wb_dat_i (wb_mem_dat_i),
.wb_sel_i (wb_mem_sel_i),
.wb_stb_i (wb_mem_stb_i),
.wb_we_i (wb_mem_we_i),
.wb_clk_i (wb_mem_clk_i),
.wb_rst_i (wb_mem_rst_i));
end else begin // block: gen_sram
assign wb_ext_adr_i = wb_mem_adr_i;
assign wb_ext_bte_i = wb_mem_bte_i;
assign wb_ext_cti_i = wb_mem_cti_i;
assign wb_ext_cyc_i = wb_mem_cyc_i;
assign wb_ext_dat_i = wb_mem_dat_i;
assign wb_ext_sel_i = wb_mem_sel_i;
assign wb_ext_stb_i = wb_mem_stb_i;
assign wb_ext_we_i = wb_mem_we_i;
assign wb_mem_ack_o = wb_ext_ack_o;
assign wb_mem_rty_o = wb_ext_rty_o;
assign wb_mem_err_o = wb_ext_err_o;
assign wb_mem_dat_o = wb_ext_dat_o;
end // else: !if((CONFIG.ENABLE_DM) &&...
endgenerate
networkadapter_ct
#(.CONFIG(CONFIG),
.TILEID(ID),
.COREBASE(COREBASE))
u_na(
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
.cdc_conf (cdc_conf[2:0]),
.cdc_enable (cdc_enable),
`endif
`endif
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[SLAVE_NA]),
.wbs_rty_o (bussl_rty_o[SLAVE_NA]),
.wbs_err_o (bussl_err_o[SLAVE_NA]),
.wbs_dat_o (bussl_dat_o[SLAVE_NA]),
.irq (pic_ints_i[0][4:3]),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[SLAVE_NA]),
.wbs_cyc_i (bussl_cyc_i[SLAVE_NA]),
.wbs_dat_i (bussl_dat_i[SLAVE_NA]),
.wbs_sel_i (bussl_sel_i[SLAVE_NA]),
.wbs_stb_i (bussl_stb_i[SLAVE_NA]),
.wbs_we_i (bussl_we_i[SLAVE_NA]),
.wbs_cab_i (bussl_cab_i[SLAVE_NA]),
.wbs_cti_i (bussl_cti_i[SLAVE_NA]),
.wbs_bte_i (bussl_bte_i[SLAVE_NA]));
// generate
// if (CONFIG.ENABLE_BOOTROM) begin : gen_bootrom
// /* bootrom AUTO_TEMPLATE(
// .clk(clk),
// .rst(rst_sys),
// .wb_\(.*\) (bussl_\1[SLAVE_BOOT]),
// ); */
// bootrom
// u_bootrom
// (/*AUTOINST*/
// // Outputs
// .wb_dat_o (bussl_dat_o[SLAVE_BOOT]), // Templated
// .wb_ack_o (bussl_ack_o[SLAVE_BOOT]), // Templated
// .wb_err_o (bussl_err_o[SLAVE_BOOT]), // Templated
// .wb_rty_o (bussl_rty_o[SLAVE_BOOT]), // Templated
// // Inputs
// .clk (clk), // Templated
// .rst (rst_sys), // Templated
// .wb_adr_i (bussl_adr_i[SLAVE_BOOT]), // Templated
// .wb_dat_i (bussl_dat_i[SLAVE_BOOT]), // Templated
// .wb_cyc_i (bussl_cyc_i[SLAVE_BOOT]), // Templated
// .wb_stb_i (bussl_stb_i[SLAVE_BOOT]), // Templated
// .wb_sel_i (bussl_sel_i[SLAVE_BOOT])); // Templated
// end else begin // if (CONFIG.ENABLE_BOOTROM)
// assign bussl_dat_o[SLAVE_BOOT] = 32'hx;
// assign bussl_ack_o[SLAVE_BOOT] = 1'b0;
// assign bussl_err_o[SLAVE_BOOT] = 1'b0;
// assign bussl_rty_o[SLAVE_BOOT] = 1'b0;
// end // else: !if(CONFIG.ENABLE_BOOTROM)
// endgenerate
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the compute tile for distributed memory systems.
*
*
* The assignment of the 32 bit IRQ vector connected to core 0 is as follows:
* - Bit [1:0]: N/A
* - Bit 2: UART
* - Bit 3: NA - message passing
* - Bit 4: NA - DMA
* - Bit [31:5]: N/A
*
* The address ranges of the bus slaves are as follows:
* - Slave 0 - DM: 0x00000000-0x7fffffff
* - Slave 1 - PGAS: not used
* - Slave 2 - NA: 0xe0000000-0xefffffff
* - Slave 3 - BOOT: 0xf0000000-0xffffffff
* - Slave 4 - UART: 0x90000000-0x9000000f
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module memsubsys
import dii_package::dii_flit;
import opensocdebug::mor1kx_trace_exec;
import optimsoc_config::*;
#(
parameter config_t CONFIG = 'x,
parameter ID = 'x,
parameter COREBASE = 'x,
parameter DEBUG_BASEID = 'x,
parameter MEM_FILE = 'x,
localparam CHANNELS = CONFIG.NOC_CHANNELS,
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH
)
(
input dii_flit [1:0] debug_ring_in,
output [1:0] debug_ring_in_ready,
output dii_flit [1:0] debug_ring_out,
input [1:0] debug_ring_out_ready,
output [31:0] wb_ext_adr_i,
output wb_ext_cyc_i,
output [31:0] wb_ext_dat_i,
output [3:0] wb_ext_sel_i,
output wb_ext_stb_i,
output wb_ext_we_i,
output wb_ext_cab_i,
output [2:0] wb_ext_cti_i,
output [1:0] wb_ext_bte_i,
input wb_ext_ack_o,
input wb_ext_rty_o,
input wb_ext_err_o,
input [31:0] wb_ext_dat_o,
input clk,
input rst_cpu, rst_sys, rst_dbg,
input [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_in_flit,
input [CHANNELS-1:0] noc_in_last,
input [CHANNELS-1:0] noc_in_valid,
output [CHANNELS-1:0] noc_in_ready,
output [CHANNELS-1:0][FLIT_WIDTH-1:0] noc_out_flit,
output [CHANNELS-1:0] noc_out_last,
output [CHANNELS-1:0] noc_out_valid,
input [CHANNELS-1:0] noc_out_ready
);
import optimsoc_functions::*;
localparam NR_MASTERS = 0;
localparam NR_SLAVES = 4;
localparam SLAVE_DM = 0;
localparam SLAVE_RAM1 = 1;
localparam SLAVE_NA = 2;
localparam SLAVE_RAM2 = 3;
localparam SLAVE_RAM3 = 4;
logic wb_mem_clk_i;
logic wb_mem_rst_i;
logic [31:0] wb_mem_adr_i;
logic wb_mem_cyc_i;
logic [31:0] wb_mem_dat_i;
logic [3:0] wb_mem_sel_i;
logic wb_mem_stb_i;
logic wb_mem_we_i;
logic wb_mem_cab_i;
logic [2:0] wb_mem_cti_i;
logic [1:0] wb_mem_bte_i;
logic wb_mem_ack_o;
logic wb_mem_rty_o;
logic wb_mem_err_o;
logic [31:0] wb_mem_dat_o;
// create DI ring segment with routers
localparam DEBUG_MODS_PER_TILE_NONZERO = (CONFIG.DEBUG_MODS_PER_TILE == 0) ? 1 : CONFIG.DEBUG_MODS_PER_TILE;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_in_ready;
dii_flit [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out;
logic [DEBUG_MODS_PER_TILE_NONZERO-1:0] dii_out_ready;
generate
if (CONFIG.USE_DEBUG == 1) begin : gen_debug_ring
genvar i;
logic [CONFIG.DEBUG_MODS_PER_TILE-1:0][15:0] id_map;
for (i = 0; i < CONFIG.DEBUG_MODS_PER_TILE; i = i+1) begin
assign id_map[i][15:0] = 16'(DEBUG_BASEID+i);
end
debug_ring_expand
#(.BUFFER_SIZE(CONFIG.DEBUG_ROUTER_BUFFER_SIZE),
.PORTS(CONFIG.DEBUG_MODS_PER_TILE))
u_debug_ring_segment
(.clk (clk),
.rst (rst_dbg),
.id_map (id_map),
.dii_in (dii_in),
.dii_in_ready (dii_in_ready),
.dii_out (dii_out),
.dii_out_ready (dii_out_ready),
.ext_in (debug_ring_in),
.ext_in_ready (debug_ring_in_ready),
.ext_out (debug_ring_out),
.ext_out_ready (debug_ring_out_ready));
end // if (USE_DEBUG)
endgenerate
wire [31:0] busms_adr_o[0:NR_MASTERS-1];
wire busms_cyc_o[0:NR_MASTERS-1];
wire [31:0] busms_dat_o[0:NR_MASTERS-1];
wire [3:0] busms_sel_o[0:NR_MASTERS-1];
wire busms_stb_o[0:NR_MASTERS-1];
wire busms_we_o[0:NR_MASTERS-1];
wire busms_cab_o[0:NR_MASTERS-1];
wire [2:0] busms_cti_o[0:NR_MASTERS-1];
wire [1:0] busms_bte_o[0:NR_MASTERS-1];
wire busms_ack_i[0:NR_MASTERS-1];
wire busms_rty_i[0:NR_MASTERS-1];
wire busms_err_i[0:NR_MASTERS-1];
wire [31:0] busms_dat_i[0:NR_MASTERS-1];
wire [31:0] bussl_adr_i[0:NR_SLAVES-1];
wire bussl_cyc_i[0:NR_SLAVES-1];
wire [31:0] bussl_dat_i[0:NR_SLAVES-1];
wire [3:0] bussl_sel_i[0:NR_SLAVES-1];
wire bussl_stb_i[0:NR_SLAVES-1];
wire bussl_we_i[0:NR_SLAVES-1];
wire bussl_cab_i[0:NR_SLAVES-1];
wire [2:0] bussl_cti_i[0:NR_SLAVES-1];
wire [1:0] bussl_bte_i[0:NR_SLAVES-1];
wire bussl_ack_o[0:NR_SLAVES-1];
wire bussl_rty_o[0:NR_SLAVES-1];
wire bussl_err_o[0:NR_SLAVES-1];
wire [31:0] bussl_dat_o[0:NR_SLAVES-1];
wire snoop_enable;
wire [31:0] snoop_adr;
wire [31:0] pic_ints_i [0:CONFIG.CORES_PER_TILE-1];
assign pic_ints_i[0][31:5] = 27'h0;
assign pic_ints_i[0][1:0] = 2'b00;
genvar c, m, s;
wire [32*NR_MASTERS-1:0] busms_adr_o_flat;
wire [NR_MASTERS-1:0] busms_cyc_o_flat;
wire [32*NR_MASTERS-1:0] busms_dat_o_flat;
wire [4*NR_MASTERS-1:0] busms_sel_o_flat;
wire [NR_MASTERS-1:0] busms_stb_o_flat;
wire [NR_MASTERS-1:0] busms_we_o_flat;
wire [NR_MASTERS-1:0] busms_cab_o_flat;
wire [3*NR_MASTERS-1:0] busms_cti_o_flat;
wire [2*NR_MASTERS-1:0] busms_bte_o_flat;
wire [NR_MASTERS-1:0] busms_ack_i_flat;
wire [NR_MASTERS-1:0] busms_rty_i_flat;
wire [NR_MASTERS-1:0] busms_err_i_flat;
wire [32*NR_MASTERS-1:0] busms_dat_i_flat;
wire [32*NR_SLAVES-1:0] bussl_adr_i_flat;
wire [NR_SLAVES-1:0] bussl_cyc_i_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_i_flat;
wire [4*NR_SLAVES-1:0] bussl_sel_i_flat;
wire [NR_SLAVES-1:0] bussl_stb_i_flat;
wire [NR_SLAVES-1:0] bussl_we_i_flat;
wire [NR_SLAVES-1:0] bussl_cab_i_flat;
wire [3*NR_SLAVES-1:0] bussl_cti_i_flat;
wire [2*NR_SLAVES-1:0] bussl_bte_i_flat;
wire [NR_SLAVES-1:0] bussl_ack_o_flat;
wire [NR_SLAVES-1:0] bussl_rty_o_flat;
wire [NR_SLAVES-1:0] bussl_err_o_flat;
wire [32*NR_SLAVES-1:0] bussl_dat_o_flat;
generate
for (m = 0; m < NR_MASTERS; m = m + 1) begin : gen_busms_flat
assign busms_adr_o_flat[32*(m+1)-1:32*m] = busms_adr_o[m];
assign busms_cyc_o_flat[m] = busms_cyc_o[m];
assign busms_dat_o_flat[32*(m+1)-1:32*m] = busms_dat_o[m];
assign busms_sel_o_flat[4*(m+1)-1:4*m] = busms_sel_o[m];
assign busms_stb_o_flat[m] = busms_stb_o[m];
assign busms_we_o_flat[m] = busms_we_o[m];
assign busms_cab_o_flat[m] = busms_cab_o[m];
assign busms_cti_o_flat[3*(m+1)-1:3*m] = busms_cti_o[m];
assign busms_bte_o_flat[2*(m+1)-1:2*m] = busms_bte_o[m];
assign busms_ack_i[m] = busms_ack_i_flat[m];
assign busms_rty_i[m] = busms_rty_i_flat[m];
assign busms_err_i[m] = busms_err_i_flat[m];
assign busms_dat_i[m] = busms_dat_i_flat[32*(m+1)-1:32*m];
end
for (s = 0; s < NR_SLAVES; s = s + 1) begin : gen_bussl_flat
assign bussl_adr_i[s] = bussl_adr_i_flat[32*(s+1)-1:32*s];
assign bussl_cyc_i[s] = bussl_cyc_i_flat[s];
assign bussl_dat_i[s] = bussl_dat_i_flat[32*(s+1)-1:32*s];
assign bussl_sel_i[s] = bussl_sel_i_flat[4*(s+1)-1:4*s];
assign bussl_stb_i[s] = bussl_stb_i_flat[s];
assign bussl_we_i[s] = bussl_we_i_flat[s];
assign bussl_cab_i[s] = bussl_cab_i_flat[s];
assign bussl_cti_i[s] = bussl_cti_i_flat[3*(s+1)-1:3*s];
assign bussl_bte_i[s] = bussl_bte_i_flat[2*(s+1)-1:2*s];
assign bussl_ack_o_flat[s] = bussl_ack_o[s];
assign bussl_rty_o_flat[s] = bussl_rty_o[s];
assign bussl_err_o_flat[s] = bussl_err_o[s];
assign bussl_dat_o_flat[32*(s+1)-1:32*s] = bussl_dat_o[s];
end
endgenerate
/* wb_bus_b3 AUTO_TEMPLATE(
.clk_i (clk),
.rst_i (rst_sys),
.m_\(.*\)_o (busms_\1_i_flat),
.m_\(.*\)_i (busms_\1_o_flat),
.s_\(.*\)_o (bussl_\1_i_flat),
.s_\(.*\)_i (bussl_\1_o_flat),
.snoop_en_o (snoop_enable),
.snoop_adr_o (snoop_adr),
.bus_hold (1'b0),
.bus_hold_ack (),
); */
wb_bus_b3
#(.MASTERS(NR_MASTERS),.SLAVES(NR_SLAVES),
.S0_ENABLE(CONFIG.ENABLE_DM),
.S0_RANGE_WIDTH(CONFIG.DM_RANGE_WIDTH),.S0_RANGE_MATCH(CONFIG.DM_RANGE_MATCH),
.S1_ENABLE(CONFIG.ENABLE_PGAS),
.S1_RANGE_WIDTH(CONFIG.PGAS_RANGE_WIDTH),.S1_RANGE_MATCH(CONFIG.PGAS_RANGE_MATCH),
.S2_RANGE_WIDTH(4),.S2_RANGE_MATCH(4'he),
.S3_ENABLE(CONFIG.ENABLE_BOOTROM),
.S3_RANGE_WIDTH(4),.S3_RANGE_MATCH(4'hf)
//.S4_ENABLE(CONFIG.DEBUG_DEM_UART),
//.S4_RANGE_WIDTH(28),.S4_RANGE_MATCH(28'h9000000)
)
u_bus(/*AUTOINST*/
// Outputs
.m_dat_o (busms_dat_i_flat), // Templated
.m_ack_o (busms_ack_i_flat), // Templated
.m_err_o (busms_err_i_flat), // Templated
.m_rty_o (busms_rty_i_flat), // Templated
.s_adr_o (bussl_adr_i_flat), // Templated
.s_dat_o (bussl_dat_i_flat), // Templated
.s_cyc_o (bussl_cyc_i_flat), // Templated
.s_stb_o (bussl_stb_i_flat), // Templated
.s_sel_o (bussl_sel_i_flat), // Templated
.s_we_o (bussl_we_i_flat), // Templated
.s_cti_o (bussl_cti_i_flat), // Templated
.s_bte_o (bussl_bte_i_flat), // Templated
.snoop_adr_o (snoop_adr), // Templated
.snoop_en_o (snoop_enable), // Templated
.bus_hold_ack (), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (rst_sys), // Templated
.m_adr_i (busms_adr_o_flat), // Templated
.m_dat_i (busms_dat_o_flat), // Templated
.m_cyc_i (busms_cyc_o_flat), // Templated
.m_stb_i (busms_stb_o_flat), // Templated
.m_sel_i (busms_sel_o_flat), // Templated
.m_we_i (busms_we_o_flat), // Templated
.m_cti_i (busms_cti_o_flat), // Templated
.m_bte_i (busms_bte_o_flat), // Templated
.s_dat_i (bussl_dat_o_flat), // Templated
.s_ack_i (bussl_ack_o_flat), // Templated
.s_err_i (bussl_err_o_flat), // Templated
.s_rty_i (bussl_rty_o_flat), // Templated
.bus_hold (1'b0)); // Templated
// Unused leftover from an older Wishbone spec version
assign bussl_cab_i_flat = NR_SLAVES'(1'b0);
networkadapter_ct
#(.CONFIG(CONFIG),
.TILEID(ID),
.COREBASE(COREBASE))
u_na(
`ifdef OPTIMSOC_CLOCKDOMAINS
`ifdef OPTIMSOC_CDC_DYNAMIC
.cdc_conf (cdc_conf[2:0]),
.cdc_enable (cdc_enable),
`endif
`endif
// Outputs
.noc_in_ready (noc_in_ready),
.noc_out_flit (noc_out_flit),
.noc_out_last (noc_out_last),
.noc_out_valid (noc_out_valid),
.wbm_adr_o (busms_adr_o[NR_MASTERS-1]),
.wbm_cyc_o (busms_cyc_o[NR_MASTERS-1]),
.wbm_dat_o (busms_dat_o[NR_MASTERS-1]),
.wbm_sel_o (busms_sel_o[NR_MASTERS-1]),
.wbm_stb_o (busms_stb_o[NR_MASTERS-1]),
.wbm_we_o (busms_we_o[NR_MASTERS-1]),
.wbm_cab_o (busms_cab_o[NR_MASTERS-1]),
.wbm_cti_o (busms_cti_o[NR_MASTERS-1]),
.wbm_bte_o (busms_bte_o[NR_MASTERS-1]),
.wbs_ack_o (bussl_ack_o[SLAVE_NA]),
.wbs_rty_o (bussl_rty_o[SLAVE_NA]),
.wbs_err_o (bussl_err_o[SLAVE_NA]),
.wbs_dat_o (bussl_dat_o[SLAVE_NA]),
.irq (pic_ints_i[0][4:3]),
// Inputs
.clk (clk),
.rst (rst_sys),
.noc_in_flit (noc_in_flit),
.noc_in_last (noc_in_last),
.noc_in_valid (noc_in_valid),
.noc_out_ready (noc_out_ready),
.wbm_ack_i (busms_ack_i[NR_MASTERS-1]),
.wbm_rty_i (busms_rty_i[NR_MASTERS-1]),
.wbm_err_i (busms_err_i[NR_MASTERS-1]),
.wbm_dat_i (busms_dat_i[NR_MASTERS-1]),
.wbs_adr_i (bussl_adr_i[SLAVE_NA]),
.wbs_cyc_i (bussl_cyc_i[SLAVE_NA]),
.wbs_dat_i (bussl_dat_i[SLAVE_NA]),
.wbs_sel_i (bussl_sel_i[SLAVE_NA]),
.wbs_stb_i (bussl_stb_i[SLAVE_NA]),
.wbs_we_i (bussl_we_i[SLAVE_NA]),
.wbs_cab_i (bussl_cab_i[SLAVE_NA]),
.wbs_cti_i (bussl_cti_i[SLAVE_NA]),
.wbs_bte_i (bussl_bte_i[SLAVE_NA]));
ram_wb_01 ram_wb_01_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_RAM1]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_RAM1]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_RAM1]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_RAM1]), // Templated
.wb_we_i (bussl_we_i[SLAVE_RAM1]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_RAM1]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_RAM1]), // Templated
.wb_err_o (bussl_err_o[SLAVE_RAM1])); // Templated
ram_wb_02 ram_wb_02_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_RAM2]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_RAM2]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_RAM2]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_RAM2]), // Templated
.wb_we_i (bussl_we_i[SLAVE_RAM2]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_RAM2]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_RAM2]), // Templated
.wb_err_o (bussl_err_o[SLAVE_RAM2])); // Templated
ram_wb_03 ram_wb_03_inst
(
.wb_clk_i(clk),
.wb_rst_i(rst_sys),
.wb_adr_i (bussl_adr_i[SLAVE_RAM3]), // Templated
.wb_dat_i (bussl_dat_i[SLAVE_RAM3]), // Templated
.wb_cyc_i (bussl_cyc_i[SLAVE_RAM3]), // Templated
.wb_stb_i (bussl_stb_i[SLAVE_RAM3]), // Templated
.wb_we_i (bussl_we_i[SLAVE_RAM3]), // Templated
.wb_dat_o (bussl_dat_o[SLAVE_RAM3]), // Templated
.wb_ack_o (bussl_ack_o[SLAVE_RAM3]), // Templated
.wb_err_o (bussl_err_o[SLAVE_RAM3])); // Templated
endmodule
|
/* Copyright (c) 2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is a NoC router. It has a configurable number of input ports
* and output ports, that are not necessarily equal. It supports
* virtual channels, meaning that the flit signal between routers is
* shared logically.
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module noc_router
#(parameter FLIT_WIDTH = 32,
parameter VCHANNELS = 1,
parameter INPUTS = 'x,
parameter OUTPUTS = 'x,
parameter BUFFER_SIZE_IN = 4,
parameter BUFFER_SIZE_OUT = 4,
parameter DESTS = 'x,
parameter [OUTPUTS*DESTS-1:0] ROUTES = {DESTS*OUTPUTS{1'b0}}
)
(
input clk, rst,
output [OUTPUTS-1:0][FLIT_WIDTH-1:0] out_flit,
output [OUTPUTS-1:0] out_last,
output [OUTPUTS-1:0][VCHANNELS-1:0] out_valid,
input [OUTPUTS-1:0][VCHANNELS-1:0] out_ready,
input [INPUTS-1:0][FLIT_WIDTH-1:0] in_flit,
input [INPUTS-1:0] in_last,
input [INPUTS-1:0][VCHANNELS-1:0] in_valid,
output [INPUTS-1:0][VCHANNELS-1:0] in_ready
);
// The "switch" is just wiring (all logic is in input and
// output). All inputs generate their requests for the outputs and
// the output arbitrate between the input requests.
// The input valid signals are one (or zero) hot and hence share
// the flit signal.
wire [INPUTS-1:0][VCHANNELS-1:0][FLIT_WIDTH-1:0] switch_in_flit;
wire [INPUTS-1:0][VCHANNELS-1:0] switch_in_last;
wire [INPUTS-1:0][VCHANNELS-1:0][OUTPUTS-1:0] switch_in_valid;
wire [INPUTS-1:0][VCHANNELS-1:0][OUTPUTS-1:0] switch_in_ready;
// Outputs are fully wired to receive all input requests.
wire [OUTPUTS-1:0][VCHANNELS-1:0][INPUTS-1:0][FLIT_WIDTH-1:0] switch_out_flit;
wire [OUTPUTS-1:0][VCHANNELS-1:0][INPUTS-1:0] switch_out_last;
wire [OUTPUTS-1:0][VCHANNELS-1:0][INPUTS-1:0] switch_out_valid;
wire [OUTPUTS-1:0][VCHANNELS-1:0][INPUTS-1:0] switch_out_ready;
genvar i, v, o;
generate
for (i = 0; i < INPUTS; i++) begin : inputs
// The input stages
noc_router_input
#(.FLIT_WIDTH(FLIT_WIDTH), .VCHANNELS(VCHANNELS),
.DESTS(DESTS), .OUTPUTS(OUTPUTS), .ROUTES(ROUTES),
.BUFFER_DEPTH (BUFFER_SIZE_IN))
u_input
(.*,
.in_flit (in_flit[i]),
.in_last (in_last[i]),
.in_valid (in_valid[i]),
.in_ready (in_ready[i]),
.out_flit (switch_in_flit[i]),
.out_last (switch_in_last[i]),
.out_valid (switch_in_valid[i]),
.out_ready (switch_in_ready[i])
);
end // block: inputs
// The switching logic
for (o = 0; o < OUTPUTS; o++) begin
for (v = 0; v < VCHANNELS; v++) begin
for (i = 0; i < INPUTS; i++) begin
assign switch_out_flit[o][v][i] = switch_in_flit[i][v];
assign switch_out_last[o][v][i] = switch_in_last[i][v];
assign switch_out_valid[o][v][i] = switch_in_valid[i][v][o];
assign switch_in_ready[i][v][o] = switch_out_ready[o][v][i];
end
end
end
for (o = 0; o < OUTPUTS; o++) begin : outputs
// The output stages
noc_router_output
#(.FLIT_WIDTH(FLIT_WIDTH), .VCHANNELS(VCHANNELS),
.INPUTS(INPUTS), .BUFFER_DEPTH(BUFFER_SIZE_OUT))
u_output
(.*,
.in_flit (switch_out_flit[o]),
.in_last (switch_out_last[o]),
.in_valid (switch_out_valid[o]),
.in_ready (switch_out_ready[o]),
.out_flit (out_flit[o]),
.out_last (out_last[o]),
.out_valid (out_valid[o]),
.out_ready (out_ready[o]));
end
endgenerate
endmodule // noc_router
|
`include "dbg_config.vh"
module system_noc
(
input clk,
input rst_sys,
output[4 * 32 - 1:0] wb_ext_adr_i,
output[4 * 1 - 1:0] wb_ext_cyc_i,
output[4 * 32 - 1:0] wb_ext_dat_i,
output[4 * 4 - 1:0] wb_ext_sel_i,
output[4 * 1 - 1:0] wb_ext_stb_i,
output[4 * 1 - 1:0] wb_ext_we_i,
output[4 * 1 - 1:0] wb_ext_cab_i,
output[4 * 3 - 1:0] wb_ext_cti_i,
output[4 * 2 - 1:0] wb_ext_bte_i,
input[4 * 1 - 1:0] wb_ext_ack_o,
input[4 * 1 - 1:0] wb_ext_rty_o,
input[4 * 1 - 1:0] wb_ext_err_o,
input[4 * 32 - 1:0] wb_ext_dat_o
);
import dii_package::dii_flit;
import optimsoc_functions::*;
import opensocdebug::mor1kx_trace_exec;
import optimsoc_config::*;
parameter config_t CONFIG = 'x;
localparam FLIT_WIDTH = CONFIG.NOC_FLIT_WIDTH;
localparam CHANNELS = CONFIG.NOC_CHANNELS;
localparam VCHANNELS = 2;
logic rst_cpu;
dii_flit [1:0] debug_ring_in [0:3];
dii_flit [1:0] debug_ring_out [0:3];
logic [1:0] debug_ring_in_ready [0:3];
logic [1:0] debug_ring_out_ready [0:3];
/* debug_interface
#(
.SYSTEM_VENDOR_ID (2),
.SYSTEM_DEVICE_ID (2),
.NUM_MODULES (CONFIG.DEBUG_NUM_MODS),
.MAX_PKT_LEN(CONFIG.DEBUG_MAX_PKT_LEN),
.SUBNET_BITS(CONFIG.DEBUG_SUBNET_BITS),
.LOCAL_SUBNET(CONFIG.DEBUG_LOCAL_SUBNET),
.DEBUG_ROUTER_BUFFER_SIZE(CONFIG.DEBUG_ROUTER_BUFFER_SIZE)
)
u_debuginterface
(
.clk (clk),
.rst (rst),
.sys_rst (rst_sys),
.cpu_rst (rst_cpu),
//.glip_in (c_glip_in),
//.glip_out (c_glip_out),
.ring_out (debug_ring_in[0]),
.ring_out_ready (debug_ring_in_ready[0]),
.ring_in (debug_ring_out[2]),
.ring_in_ready (debug_ring_out_ready[2])
);
// We are routing the debug in a meander
assign debug_ring_in[1] = debug_ring_out[0];
assign debug_ring_out_ready[0] = debug_ring_in_ready[1];
assign debug_ring_in[3] = debug_ring_out[1];
assign debug_ring_out_ready[1] = debug_ring_in_ready[3];
assign debug_ring_in[2] = debug_ring_out[3];
assign debug_ring_out_ready[3] = debug_ring_in_ready[2];*/
wire [3:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_in_flit_R_1_EP;
wire [3:0][CHANNELS-1:0]noc_in_last_R_1_EP;
wire [3:0][CHANNELS-1:0]noc_in_valid_R_1_EP;
wire [3:0][CHANNELS-1:0]noc_out_ready_R_1_EP;
wire [3:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_out_flit_R_1_EP;
wire [3:0][CHANNELS-1:0]noc_out_last_R_1_EP;
wire [3:0][CHANNELS-1:0]noc_out_valid_R_1_EP;
wire [3:0][CHANNELS-1:0]noc_in_ready_R_1_EP;
cpusubsys1
#(.CONFIG(CONFIG),
.ID(1),
.COREBASE(1*CONFIG.CORES_PER_TILE),
.DEBUG_BASEID((CONFIG.DEBUG_LOCAL_SUBNET << (16 - CONFIG.DEBUG_SUBNET_BITS))+ 1 + (1*CONFIG.DEBUG_MODS_PER_TILE)))
cpusubsys1inst(
.clk (clk),
.rst_cpu (rst_cpu),
.rst_sys (rst_sys),
.noc_in_flit (noc_in_flit_R_1_EP[1]),
.noc_in_last (noc_in_last_R_1_EP[1]),
.noc_in_valid (noc_in_valid_R_1_EP[1]),
.noc_out_ready (noc_out_ready_R_1_EP[1]),
.noc_in_ready (noc_in_ready_R_1_EP[1]),
.noc_out_flit (noc_out_flit_R_1_EP[1]),
.noc_out_last (noc_out_last_R_1_EP[1]),
.noc_out_valid (noc_out_valid_R_1_EP[1]));
wire [FLIT_WIDTH-1:0]in_flit_R_1_3;
wire in_last_R_1_2;
wire [VCHANNELS-1:0]in_valid_R_1_3;
wire [VCHANNELS-1:0]out_ready_R_1_3;
wire [VCHANNELS-1:0]in_ready_R_1_3;
wire [FLIT_WIDTH-1:0]out_flit_R_1_3;
wire out_last_R_1_3;
wire [VCHANNELS-1:0]out_valid_R_1_3;
noc_router
#(.VCHANNELS (CHANNELS),
.INPUTS (5),
.OUTPUTS (5),
.DESTS (32))
noc_router_R_1_inst(
.clk (clk),
.rst (rst_sys),
.in_flit ({noc_out_flit_R_1_EP[1],in_flit_R_1_3}),
.in_last ({noc_out_last_R_1_EP[1],in_last_R_1_3}),
.in_valid ({noc_out_valid_R_1_EP[1],in_valid_R_1_3}),
.out_ready ({noc_in_ready_R_1_EP[1],out_ready_R_1_3}),
.out_flit ({noc_in_flit_R_1_EP[1],out_flit_R_1_3}),
.out_last ({noc_in_last_R_1_EP[1],out_last_R_1_3}),
.out_valid ({noc_in_valid_R_1_EP[1],out_valid_R_1_3}),
.in_ready ({noc_out_ready_R_1_EP[1],in_ready_R_1_3}));
wire [3:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_in_flit_R_2_EP;
wire [3:0][CHANNELS-1:0]noc_in_last_R_2_EP;
wire [3:0][CHANNELS-1:0]noc_in_valid_R_2_EP;
wire [3:0][CHANNELS-1:0]noc_out_ready_R_2_EP;
wire [3:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_out_flit_R_2_EP;
wire [3:0][CHANNELS-1:0]noc_out_last_R_2_EP;
wire [3:0][CHANNELS-1:0]noc_out_valid_R_2_EP;
wire [3:0][CHANNELS-1:0]noc_in_ready_R_2_EP;
cpusubsys2
#(.CONFIG(CONFIG),
.ID(2),
.COREBASE(1*CONFIG.CORES_PER_TILE),
.DEBUG_BASEID((CONFIG.DEBUG_LOCAL_SUBNET << (16 - CONFIG.DEBUG_SUBNET_BITS))+ 1 + (1*CONFIG.DEBUG_MODS_PER_TILE)))
cpusubsys2inst(
.clk (clk),
.rst_cpu (rst_cpu),
.rst_sys (rst_sys),
.noc_in_flit (noc_in_flit_R_2_EP[1]),
.noc_in_last (noc_in_last_R_2_EP[1]),
.noc_in_valid (noc_in_valid_R_2_EP[1]),
.noc_out_ready (noc_out_ready_R_2_EP[1]),
.noc_in_ready (noc_in_ready_R_2_EP[1]),
.noc_out_flit (noc_out_flit_R_2_EP[1]),
.noc_out_last (noc_out_last_R_2_EP[1]),
.noc_out_valid (noc_out_valid_R_2_EP[1]));
wire [FLIT_WIDTH-1:0]in_flit_R_2_3;
wire in_last_R_2_3;
wire [VCHANNELS-1:0]in_valid_R_2_3;
wire [VCHANNELS-1:0]out_ready_R_2_3;
wire [VCHANNELS-1:0]in_ready_R_2_3;
wire [FLIT_WIDTH-1:0]out_flit_R_2_3;
wire out_last_R_2_3;
wire [VCHANNELS-1:0]out_valid_R_2_3;
noc_router
#(.VCHANNELS (CHANNELS),
.INPUTS (5),
.OUTPUTS (5),
.DESTS (32))
noc_router_R_2_inst(
.clk (clk),
.rst (rst_sys),
.in_flit ({noc_out_flit_R_2_EP[1],in_flit_R_2_3}),
.in_last ({noc_out_last_R_2_EP[1],in_last_R_2_3}),
.in_valid ({noc_out_valid_R_2_EP[1],in_valid_R_2_3}),
.out_ready ({noc_in_ready_R_2_EP[1],out_ready_R_2_3}),
.out_flit ({noc_in_flit_R_2_EP[1],out_flit_R_2_3}),
.out_last ({noc_in_last_R_2_EP[1],out_last_R_2_3}),
.out_valid ({noc_in_valid_R_2_EP[1],out_valid_R_2_3}),
.in_ready ({noc_out_ready_R_2_EP[1],in_ready_R_2_3}));
wire [FLIT_WIDTH-1:0]in_flit_R_3_4;
wire in_last_R_3_4;
wire [VCHANNELS-1:0]in_valid_R_3_4;
wire [VCHANNELS-1:0]out_ready_R_3_4;
wire [VCHANNELS-1:0]in_ready_R_3_4;
wire [FLIT_WIDTH-1:0]out_flit_R_3_4;
wire out_last_R_3_4;
wire [VCHANNELS-1:0]out_valid_R_3_4;
noc_router
#(.VCHANNELS (CHANNELS),
.INPUTS (6),
.OUTPUTS (6),
.DESTS (32))
noc_router_R_3_inst(
.clk (clk),
.rst (rst_sys),
.in_flit ({out_flit_R_1_3,out_flit_R_2_3,in_flit_R_3_4}),
.in_last ({out_last_R_1_3,out_last_R_2_3,in_last_R_3_4}),
.in_valid ({out_valid_R_1_3,out_valid_R_2_3,in_valid_R_3_4}),
.out_ready ({in_ready_R_1_3,in_ready_R_2_3,out_ready_R_3_4}),
.out_flit ({in_flit_R_1_3,in_flit_R_2_3,out_flit_R_3_4}),
.out_last ({in_last_R_1_3,in_last_R_2_3,out_last_R_3_4}),
.out_valid ({in_valid_R_1_3,in_valid_R_2_3,out_valid_R_3_4}),
.in_ready ({out_ready_R_1_3,out_ready_R_2_3,in_ready_R_3_4}));
////////////////////////////////////////////////////////////////
wire [FLIT_WIDTH-1:0]in_flit_R_6_4;
wire in_last_R_6_4;
wire [VCHANNELS-1:0]in_valid_R_6_4;
wire [VCHANNELS-1:0]out_ready_R_6_4;
wire [VCHANNELS-1:0]in_ready_R_6_4;
wire [FLIT_WIDTH-1:0]out_flit_R_6_4;
wire out_last_R_6_4;
wire [VCHANNELS-1:0]out_valid_R_6_4;
wire [FLIT_WIDTH-1:0]in_flit_R_5_4;
wire in_last_R_5_4;
wire [VCHANNELS-1:0]in_valid_R_5_4;
wire [VCHANNELS-1:0]out_ready_R_5_4;
wire [VCHANNELS-1:0]in_ready_R_5_4;
wire [FLIT_WIDTH-1:0]out_flit_R_5_4;
wire out_last_R_5_4;
wire [VCHANNELS-1:0]out_valid_R_5_4;
noc_router
#(.VCHANNELS (CHANNELS),
.INPUTS (6),
.OUTPUTS (6),
.DESTS (32))
noc_router_R_4_inst(
.clk (clk),
.rst (rst_sys),
.in_flit ({out_flit_R_3_4,in_flit_R_7_4,out_flit_R_5_4}),
.in_last ({out_last_R_3_4,in_last_R_7_4,out_last_R_5_4}),
.in_valid ({out_valid_R_3_4,out_valid_R_7_4,out_valid_R_5_4}),
.out_ready ({in_ready_R_3_4,in_ready_R_7_4,in_ready_R_5_4}),
.out_flit ({in_flit_R_3_4,in_flit_R_7_4,in_flit_R_5_4}),
.out_last ({in_last_R_3_4,in_last_R_7_4,in_last_R_5_4}),
.out_valid ({in_valid_R_3_4,in_valid_R_7_4,in_valid_R_5_4}),
.in_ready ({out_ready_R_3_4,out_ready_R_7_4,out_ready_R_5_4}));
noc_router
#(.VCHANNELS (CHANNELS),
.INPUTS (6),
.OUTPUTS (6),
.DESTS (32))
noc_router_R_5_inst(
.clk (clk),
.rst (rst_sys),
.in_flit ({out_flit_R_6_5,in_flit_R_6_4,in_flit_R_5_4}),
.in_last ({out_last_R_6_5,in_last_R_6_4,in_last_R_5_4}),
.in_valid ({out_valid_R_6_5,out_valid_R_6_4,in_valid_R_5_4}),
.out_ready ({in_ready_R_6_5,in_ready_R_6_4,out_ready_R_5_4}),
.out_flit ({in_flit_R_6_5,in_flit_R_6_4,out_flit_R_5_4}),
.out_last ({in_last_R_6_5,in_last_R_6_4,out_last_R_5_4}),
.out_valid ({in_valid_R_6_5,in_valid_R_6_4,out_valid_R_5_4}),
.in_ready ({out_ready_R_6_5,out_ready_R_6_4,in_ready_R_5_4}));
noc_router
#(.VCHANNELS (CHANNELS),
.INPUTS (6),
.OUTPUTS (6),
.DESTS (32))
noc_router_R_6_inst(
.clk (clk),
.rst (rst_sys),
.in_flit ({noc_out_flit_R_6_EP[1],in_flit_R_6_5}),
.in_last ({noc_out_last_R_6_EP[1],in_last_R_6_5}),
.in_valid ({noc_out_valid_R_6_EP[1],in_valid_R_6_5}),
.out_ready ({noc_in_ready_R_6_EP[1],out_ready_R_6_5}),
.out_flit ({noc_in_flit_R_6_EP[1],out_flit_R_6_5}),
.out_last ({noc_in_last_R_6_EP[1],out_last_R_6_5}),
.out_valid ({noc_in_valid_R_6_EP[1],out_valid_R_6_5}),
.in_ready ({noc_out_ready_R_6_EP[1],in_ready_R_6_5}));
wire [3:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_in_flit_R_6_EP;
wire [3:0][CHANNELS-1:0]noc_in_last_R_6_EP;
wire [3:0][CHANNELS-1:0]noc_in_valid_R_6_EP;
wire [3:0][CHANNELS-1:0]noc_out_ready_R_6_EP;
wire [3:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_out_flit_R_6_EP;
wire [3:0][CHANNELS-1:0]noc_out_last_R_6_EP;
wire [3:0][CHANNELS-1:0]noc_out_valid_R_6_EP;
wire [3:0][CHANNELS-1:0]noc_in_ready_R_6_EP;
memsubsys
#(.CONFIG(CONFIG),
.ID(5),
.COREBASE(5*CONFIG.CORES_PER_TILE),
.DEBUG_BASEID((CONFIG.DEBUG_LOCAL_SUBNET << (16 - CONFIG.DEBUG_SUBNET_BITS))+ 1 + (5*CONFIG.DEBUG_MODS_PER_TILE)))
memsubsysinst(
.clk (clk),
.rst_cpu (rst_cpu),
.rst_sys (rst_sys),
.noc_in_flit (noc_in_flit_R_6_EP[1]),
.noc_in_last (noc_in_last_R_6_EP[1]),
.noc_in_valid (noc_in_valid_R_6_EP[1]),
.noc_out_ready (noc_out_ready_R_6_EP[1]),
.noc_in_ready (noc_in_ready_R_6_EP[1]),
.noc_out_flit (noc_out_flit_R_6_EP[1]),
.noc_out_last (noc_out_last_R_6_EP[1]),
.noc_out_valid (noc_out_valid_R_6_EP[1]));
noc_router
#(.VCHANNELS (CHANNELS),
.INPUTS (6),
.OUTPUTS (6),
.DESTS (32))
noc_router_R_7_inst(
.clk (clk),
.rst (rst_sys),
.in_flit ({out_flit_R_7_4,in_flit_R_7_8,out_flit_R_7_11}),
.in_last ({out_last_R_7_4,in_last_R_7_8,out_last_R_7_11}),
.in_valid ({out_valid_R_7_4,out_valid_R_7_8,out_valid_R_7_11}),
.out_ready ({in_ready_R_7_4,in_ready_R_7_8,in_ready_R_7_11}),
.out_flit ({in_flit_R_7_4,in_flit_R_7_8,in_flit_R_7_11}),
.out_last ({in_last_R_7_4,in_last_R_7_8,in_last_R_7_11}),
.out_valid ({in_valid_R_7_4,in_valid_R_7_8,in_valid_R_7_11}),
.in_ready ({out_ready_R_7_4,out_ready_R_7_8,out_ready_R_7_11}));
noc_router
#(.VCHANNELS (CHANNELS),
.INPUTS (6),
.OUTPUTS (6),
.DESTS (32))
noc_router_R_8_inst(
.clk (clk),
.rst (rst_sys),
.in_flit ({out_flit_R_9_8,out_flit_R_10_8,out_flit_R_7_8}),
.in_last ({out_last_R_9_8,out_last_R_10_8,out_last_R_7_8}),
.in_valid ({out_valid_R_9_8,out_valid_R_10_8,out_valid_R_7_8}),
.out_ready ({in_ready_R_9_8,in_ready_R_10_8,in_ready_R_7_8}),
.out_flit ({in_flit_R_9_8,in_flit_R_10_8,in_flit_R_7_8}),
.out_last ({in_last_R_9_8,in_last_R_10_8,in_last_R_7_8}),
.out_valid ({in_valid_R_9_8,in_valid_R_10_8,in_valid_R_7_8}),
.in_ready ({out_ready_R_9_8,out_ready_R_10_8,out_ready_R_7_8}));
noc_router
#(.VCHANNELS (CHANNELS),
.INPUTS (5),
.OUTPUTS (5),
.DESTS (32))
noc_router_R_9_inst(
.clk (clk),
.rst (rst_sys),
.in_flit ({noc_out_flit_R_9_EP[1],in_flit_R_9_8}),
.in_last ({noc_out_last_R_9_EP[1],in_last_R_9_8}),
.in_valid ({noc_out_valid_R_9_EP[1],in_valid_R_9_8}),
.out_ready ({noc_in_ready_R_9_EP[1],out_ready_R_9_8}),
.out_flit ({noc_in_flit_R_9_EP[1],out_flit_R_9_8}),
.out_last ({noc_in_last_R_9_EP[1],out_last_R_9_8}),
.out_valid ({noc_in_valid_R_9_EP[1],out_valid_R_9_8}),
.in_ready ({noc_out_ready_R_9_EP[1],in_ready_R_9_8}));
noc_router
#(.VCHANNELS (CHANNELS),
.INPUTS (5),
.OUTPUTS (5),
.DESTS (32))
noc_router_R_10_inst(
.clk (clk),
.rst (rst_sys),
.in_flit ({noc_out_flit_R_10_EP[1],in_flit_R_10_8}),
.in_last ({noc_out_last_R_10_EP[1],in_last_R_10_8}),
.in_valid ({noc_out_valid_R_10_EP[1],in_valid_R_10_8}),
.out_ready ({noc_in_ready_R_10_EP[1],out_ready_R_10_8}),
.out_flit ({noc_in_flit_R_10_EP[1],out_flit_R_10_8}),
.out_last ({noc_in_last_R_10_EP[1],out_last_R_10_8}),
.out_valid ({noc_in_valid_R_10_EP[1],out_valid_R_10_8}),
.in_ready ({noc_out_ready_R_10_EP[1],in_ready_R_10_8}));
wire [3:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_in_flit_R_9_EP;
wire [3:0][CHANNELS-1:0]noc_in_last_R_9_EP;
wire [3:0][CHANNELS-1:0]noc_in_valid_R_9_EP;
wire [3:0][CHANNELS-1:0]noc_out_ready_R_9_EP;
wire [3:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_out_flit_R_9_EP;
wire [3:0][CHANNELS-1:0]noc_out_last_R_9_EP;
wire [3:0][CHANNELS-1:0]noc_out_valid_R_9_EP;
wire [3:0][CHANNELS-1:0]noc_in_ready_R_9_EP;
wire [3:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_in_flit_R_10_EP;
wire [3:0][CHANNELS-1:0]noc_in_last_R_10_EP;
wire [3:0][CHANNELS-1:0]noc_in_valid_R_10_EP;
wire [3:0][CHANNELS-1:0]noc_out_ready_R_10_EP;
wire [3:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_out_flit_R_10_EP;
wire [3:0][CHANNELS-1:0]noc_out_last_R_10_EP;
wire [3:0][CHANNELS-1:0]noc_out_valid_R_10_EP;
wire [3:0][CHANNELS-1:0]noc_in_ready_R_10_EP;
dspsubsys1
#(.CONFIG(CONFIG),
.ID(2),
.COREBASE(2*CONFIG.CORES_PER_TILE),
.DEBUG_BASEID((CONFIG.DEBUG_LOCAL_SUBNET << (16 - CONFIG.DEBUG_SUBNET_BITS))+ 1 + (2*CONFIG.DEBUG_MODS_PER_TILE)))
dspsubsys1inst(
.clk (clk),
.rst_cpu (rst_cpu),
.rst_sys (rst_sys),
.noc_in_flit (noc_in_flit_R_9_EP[1]),
.noc_in_last (noc_in_last_R_9_EP[1]),
.noc_in_valid (noc_in_valid_R_9_EP[1]),
.noc_out_ready (noc_out_ready_R_9_EP[1]),
.noc_in_ready (noc_in_ready_R_9_EP[1]),
.noc_out_flit (noc_out_flit_R_9_EP[1]),
.noc_out_last (noc_out_last_R_9_EP[1]),
.noc_out_valid (noc_out_valid_R_9_EP[1]));
dspsubsys2
#(.CONFIG(CONFIG),
.ID(4),
.COREBASE(4*CONFIG.CORES_PER_TILE),
.DEBUG_BASEID((CONFIG.DEBUG_LOCAL_SUBNET << (16 - CONFIG.DEBUG_SUBNET_BITS))+ 1 + (4*CONFIG.DEBUG_MODS_PER_TILE)))
dspsubsys2inst(
.clk (clk),
.rst_cpu (rst_cpu),
.rst_sys (rst_sys),
.noc_in_flit (noc_in_flit_R_10_EP[1]),
.noc_in_last (noc_in_last_R_10_EP[1]),
.noc_in_valid (noc_in_valid_R_10_EP[1]),
.noc_out_ready (noc_out_ready_R_10_EP[1]),
.noc_in_ready (noc_in_ready_R_10_EP[1]),
.noc_out_flit (noc_out_flit_R_10_EP[1]),
.noc_out_last (noc_out_last_R_10_EP[1]),
.noc_out_valid (noc_out_valid_R_10_EP[1]));
//////////////////////////////////////////////////////////
wire [FLIT_WIDTH-1:0]in_flit_R_1_2;
wire in_last_R_1_2;
wire [VCHANNELS-1:0]in_valid_R_1_2;
wire [VCHANNELS-1:0]out_ready_R_1_2;
wire [VCHANNELS-1:0]in_ready_R_1_2;
wire [FLIT_WIDTH-1:0]out_flit_R_1_2;
wire out_last_R_1_2;
wire [VCHANNELS-1:0]out_valid_R_1_2;
wire [1:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_in_flit_R_2_EP;
wire [1:0][CHANNELS-1:0]noc_in_last_R_2_EP;
wire [1:0][CHANNELS-1:0]noc_in_valid_R_2_EP;
wire [1:0][CHANNELS-1:0]noc_out_ready_R_2_EP;
wire [1:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_out_flit_R_2_EP;
wire [1:0][CHANNELS-1:0]noc_out_last_R_2_EP;
wire [1:0][CHANNELS-1:0]noc_out_valid_R_2_EP;
wire [1:0][CHANNELS-1:0]noc_in_ready_R_2_EP;
wire [FLIT_WIDTH-1:0]in_flit_R_2_3;
wire in_last_R_2_3;
wire [VCHANNELS-1:0]in_valid_R_2_3;
wire [VCHANNELS-1:0]out_ready_R_2_3;
wire [VCHANNELS-1:0]in_ready_R_2_3;
wire [FLIT_WIDTH-1:0]out_flit_R_2_3;
wire out_last_R_2_3;
wire [VCHANNELS-1:0]out_valid_R_2_3;
wire [0:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_in_flit_R_13_EP;
wire [0:0][CHANNELS-1:0]noc_in_last_R_13_EP;
wire [0:0][CHANNELS-1:0]noc_in_valid_R_13_EP;
wire [0:0][CHANNELS-1:0]noc_out_ready_R_13_EP;
wire [0:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_out_flit_R_13_EP;
wire [0:0][CHANNELS-1:0]noc_out_last_R_13_EP;
wire [0:0][CHANNELS-1:0]noc_out_valid_R_13_EP;
wire [0:0][CHANNELS-1:0]noc_in_ready_R_13_EP;
wire [FLIT_WIDTH-1:0]in_flit_R_3_4;
wire in_last_R_3_4;
wire [VCHANNELS-1:0]in_valid_R_3_4;
wire [VCHANNELS-1:0]out_ready_R_3_4;
wire [VCHANNELS-1:0]in_ready_R_3_4;
wire [FLIT_WIDTH-1:0]out_flit_R_3_4;
wire out_last_R_3_4;
wire [VCHANNELS-1:0]out_valid_R_3_4;
wire [FLIT_WIDTH-1:0]in_flit_R_3_5;
wire in_last_R_3_5;
wire [VCHANNELS-1:0]in_valid_R_3_5;
wire [VCHANNELS-1:0]out_ready_R_3_5;
wire [VCHANNELS-1:0]in_ready_R_3_5;
wire [FLIT_WIDTH-1:0]out_flit_R_3_5;
wire out_last_R_3_5;
wire [VCHANNELS-1:0]out_valid_R_3_5;
//////////////////////////////////////////////////////////
noc_router
#(.VCHANNELS (CHANNELS),
.INPUTS (5),
.OUTPUTS (5),
.DESTS (32))
noc_router_R_11_inst(
.clk (clk),
.rst (rst_sys),
.in_flit ({out_flit_R_11_12,in_flit_R_7_11,out_flit_R_11_16}),
.in_last ({out_last_R_11_12,in_last_R_7_11,out_last_R_11_16}),
.in_valid ({out_valid_R_11_12,out_valid_R_7_11,out_valid_R_11_16}),
.out_ready ({in_ready_R_11_12,in_ready_R_7_11,in_ready_R_11_16}),
.out_flit ({in_flit_R_11_12,in_flit_R_7_11,in_flit_R_11_16}),
.out_last ({in_last_R_11_12,in_last_R_7_11,in_last_R_11_16}),
.out_valid ({in_valid_R_11_12,in_valid_R_7_11,in_valid_R_11_16}),
.in_ready ({out_ready_R_11_12,out_ready_R_7_11,out_ready_R_11_16}));
noc_router
#(.VCHANNELS (CHANNELS),
.INPUTS (5),
.OUTPUTS (5),
.DESTS (32))
noc_router_R_12_inst(
.clk (clk),
.rst (rst_sys),
.in_flit ({in_flit_R_11_12,in_flit_R_12_13}),
.in_last ({in_last_R_11_12,in_last_R_12_13}),
.in_valid ({in_valid_R_11_12,in_valid_R_12_13}),
.out_ready ({out_ready_R_11_12,out_ready_R_12_13}),
.out_flit ({out_flit_R_11_12,out_flit_R_12_13}),
.out_last ({out_last_R_11_12,out_last_R_12_13}),
.out_valid ({out_valid_R_11_12,out_valid_R_12_13}),
.in_ready ({in_ready_R_11_12,in_ready_R_12_13}));
noc_router
#(.VCHANNELS (CHANNELS),
.INPUTS (5),
.OUTPUTS (5),
.DESTS (32))
noc_router_R_13_inst(
.clk (clk),
.rst (rst_sys),
.in_flit ({in_flit_R_14_13,in_flit_R_15_13,out_flit_R_12_13}),
.in_last ({in_last_R_14_13,in_last_R_15_13,out_last_R_12_13}),
.in_valid ({in_valid_R_14_13,in_valid_R_15_13,out_valid_R_12_13}),
.out_ready ({out_ready_R_14_13,out_ready_R_15_13,in_ready_R_12_13}),
.out_flit ({out_flit_R_14_13,out_flit_R_15_13,in_flit_R_12_13}),
.out_last ({out_last_R_14_13,out_last_R_15_13,in_last_R_12_13}),
.out_valid ({out_valid_R_14_13,out_valid_R_15_13,in_valid_R_12_13}),
.in_ready ({in_ready_R_14_13,in_ready_R_15_13,out_ready_R_12_13}));
wire [3:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_in_flit_R_14_EP;
wire [3:0][CHANNELS-1:0]noc_in_last_R_14_EP;
wire [3:0][CHANNELS-1:0]noc_in_valid_R_14_EP;
wire [3:0][CHANNELS-1:0]noc_out_ready_R_14_EP;
wire [3:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_out_flit_R_14_EP;
wire [3:0][CHANNELS-1:0]noc_out_last_R_14_EP;
wire [3:0][CHANNELS-1:0]noc_out_valid_R_14_EP;
wire [3:0][CHANNELS-1:0]noc_in_ready_R_14_EP;
wire [3:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_in_flit_R_15_EP;
wire [3:0][CHANNELS-1:0]noc_in_last_R_15_EP;
wire [3:0][CHANNELS-1:0]noc_in_valid_R_15_EP;
wire [3:0][CHANNELS-1:0]noc_out_ready_R_15_EP;
wire [3:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_out_flit_R_15_EP;
wire [3:0][CHANNELS-1:0]noc_out_last_R_15_EP;
wire [3:0][CHANNELS-1:0]noc_out_valid_R_15_EP;
wire [3:0][CHANNELS-1:0]noc_in_ready_R_15_EP;
cryptosubsys1
#(.CONFIG(CONFIG),
.ID(8),
.COREBASE(8*CONFIG.CORES_PER_TILE),
.DEBUG_BASEID((CONFIG.DEBUG_LOCAL_SUBNET << (16 - CONFIG.DEBUG_SUBNET_BITS))+ 1 + (8*CONFIG.DEBUG_MODS_PER_TILE)))
cryptosubsys1inst(
.clk (clk),
.rst_cpu (rst_cpu),
.rst_sys (rst_sys),
.noc_in_flit (noc_in_flit_R_14_EP[1]),
.noc_in_last (noc_in_last_R_14_EP[1]),
.noc_in_valid (noc_in_valid_R_14_EP[1]),
.noc_out_ready (noc_out_ready_R_14_EP[1]),
.noc_in_ready (noc_in_ready_R_14_EP[1]),
.noc_out_flit (noc_out_flit_R_14_EP[1]),
.noc_out_last (noc_out_last_R_14_EP[1]),
.noc_out_valid (noc_out_valid_R_14_EP[1]));
noc_router
#(.VCHANNELS (CHANNELS),
.INPUTS (5),
.OUTPUTS (5),
.DESTS (32))
noc_router_R_14_inst(
.clk (clk),
.rst (rst_sys),
.in_flit ({noc_out_flit_R_14_EP[1],out_flit_R_14_13}),
.in_last ({noc_out_last_R_14_EP[1],out_last_R_14_13}),
.in_valid ({noc_out_valid_R_14_EP[1],out_valid_R_14_13}),
.out_ready ({noc_in_ready_R_14_EP[1],in_ready_R_14_13}),
.out_flit ({noc_in_flit_R_14_EP[1],in_flit_R_14_13}),
.out_last ({noc_in_last_R_14_EP[1],in_last_R_14_13}),
.out_valid ({noc_in_valid_R_14_EP[1],in_valid_R_14_13}),
.in_ready ({noc_out_ready_R_14_EP[1],out_ready_R_14_13}));
cryptosubsys2
#(.CONFIG(CONFIG),
.ID(9),
.COREBASE(9*CONFIG.CORES_PER_TILE),
.DEBUG_BASEID((CONFIG.DEBUG_LOCAL_SUBNET << (16 - CONFIG.DEBUG_SUBNET_BITS))+ 1 + (9*CONFIG.DEBUG_MODS_PER_TILE)))
cryptosubsys2inst(
.clk (clk),
.rst_cpu (rst_cpu),
.rst_sys (rst_sys),
.noc_in_flit (noc_in_flit_R_15_EP[1]),
.noc_in_last (noc_in_last_R_15_EP[1]),
.noc_in_valid (noc_in_valid_R_15_EP[1]),
.noc_out_ready (noc_out_ready_R_15_EP[1]),
.noc_in_ready (noc_in_ready_R_15_EP[1]),
.noc_out_flit (noc_out_flit_R_15_EP[1]),
.noc_out_last (noc_out_last_R_15_EP[1]),
.noc_out_valid (noc_out_valid_R_15_EP[1]));
noc_router
#(.VCHANNELS (CHANNELS),
.INPUTS (5),
.OUTPUTS (5),
.DESTS (32))
noc_router_R_15_inst(
.clk (clk),
.rst (rst_sys),
.in_flit ({noc_out_flit_R_15_EP[1],out_flit_R_15_13}),
.in_last ({noc_out_last_R_15_EP[1],out_last_R_15_13}),
.in_valid ({noc_out_valid_R_15_EP[1],out_valid_R_15_13}),
.out_ready ({noc_in_ready_R_15_EP[1],in_ready_R_15_13}),
.out_flit ({noc_in_flit_R_15_EP[1],in_flit_R_15_13}),
.out_last ({noc_in_last_R_15_EP[1],in_last_R_15_13}),
.out_valid ({noc_in_valid_R_15_EP[1],in_valid_R_15_13}),
.in_ready ({noc_out_ready_R_15_EP[1],out_ready_R_15_13}));
wire [4:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_in_flit_R_16_EP;
wire [4:0][CHANNELS-1:0]noc_in_last_R_16_EP;
wire [4:0][CHANNELS-1:0]noc_in_valid_R_16_EP;
wire [4:0][CHANNELS-1:0]noc_out_ready_R_16_EP;
wire [4:0][CHANNELS-1:0][FLIT_WIDTH-1:0]noc_out_flit_R_16_EP;
wire [4:0][CHANNELS-1:0]noc_out_last_R_16_EP;
wire [4:0][CHANNELS-1:0]noc_out_valid_R_16_EP;
wire [4:0][CHANNELS-1:0]noc_in_ready_R_16_EP;
wire [FLIT_WIDTH-1:0]in_flit_R_11_16;
wire in_last_R_11_16;
wire [VCHANNELS-1:0]in_valid_R_11_16;
wire [VCHANNELS-1:0]out_ready_R_11_16;
wire [VCHANNELS-1:0]in_ready_R_11_16;
wire [FLIT_WIDTH-1:0]out_flit_R_11_16;
wire out_last_R_11_16;
wire [VCHANNELS-1:0]out_valid_R_11_16;
wire [FLIT_WIDTH-1:0]in_flit_R_17_16;
wire in_last_R_17_16;
wire [VCHANNELS-1:0]in_valid_R_17_16;
wire [VCHANNELS-1:0]out_ready_R_17_16;
wire [VCHANNELS-1:0]in_ready_R_17_16;
wire [FLIT_WIDTH-1:0]out_flit_R_17_16;
wire out_last_R_17_16;
wire [VCHANNELS-1:0]out_valid_R_17_16;
noc_router
#(.VCHANNELS (CHANNELS),
.INPUTS (5),
.OUTPUTS (5),
.DESTS (32))
noc_router_R_16_inst(
.clk (clk),
.rst (rst_sys),
.in_flit ({noc_out_flit_R_16_EP[1],in_flit_R_11_16}),
.in_last ({noc_out_last_R_16_EP[1],in_last_R_11_16}),
.in_valid ({noc_out_valid_R_16_EP[1],in_valid_R_11_16}),
.out_ready ({noc_in_ready_R_16_EP[1],out_ready_R_11_16}),
.out_flit ({noc_in_flit_R_16_EP[1],out_flit_R_11_16}),
.out_last ({noc_in_last_R_16_EP[1],out_last_R_11_16}),
.out_valid ({noc_in_valid_R_16_EP[1],out_valid_R_11_16}),
.in_ready ({noc_out_ready_R_16_EP[1],in_ready_R_11_16}));
connsubsys1
#(.CONFIG(CONFIG),
.ID(11),
.COREBASE(11*CONFIG.CORES_PER_TILE),
.DEBUG_BASEID((CONFIG.DEBUG_LOCAL_SUBNET << (16 - CONFIG.DEBUG_SUBNET_BITS))+ 1 + (11*CONFIG.DEBUG_MODS_PER_TILE)))
connsubsys1inst(
.clk (clk),
.rst_cpu (rst_cpu),
.rst_sys (rst_sys),
.noc_in_flit (noc_in_flit_R_16_EP[1]),
.noc_in_last (noc_in_last_R_16_EP[1]),
.noc_in_valid (noc_in_valid_R_16_EP[1]),
.noc_out_ready (noc_out_ready_R_16_EP[1]),
.noc_in_ready (noc_in_ready_R_16_EP[1]),
.noc_out_flit (noc_out_flit_R_16_EP[1]),
.noc_out_last (noc_out_last_R_16_EP[1]),
.noc_out_valid (noc_out_valid_R_16_EP[1]));
endmodule
|
/* Copyright (c) 2012-2016 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================*/
module tb_system(
`ifdef verilator
input clk,
input rst_sys
`endif
);
import dii_package::dii_flit;
import opensocdebug::mor1kx_trace_exec;
import optimsoc_config::*;
import optimsoc_functions::*;
parameter USE_DEBUG = 0;
parameter ENABLE_VCHANNELS = 1*1;
parameter integer NUM_CORES = 1*1; // bug in verilator would give a warning
parameter integer LMEM_SIZE = 1024;
localparam base_config_t
BASE_CONFIG = '{ NUMTILES: 4,
NUMCTS: 4,
CTLIST: {{60{16'hx}}, 16'h0, 16'h1, 16'h2, 16'h3},
CORES_PER_TILE: NUM_CORES,
GMEM_SIZE: 0,
GMEM_TILE: 'x,
NOC_ENABLE_VCHANNELS: ENABLE_VCHANNELS,
LMEM_SIZE: LMEM_SIZE,
LMEM_STYLE: PLAIN,
ENABLE_BOOTROM: 0,
BOOTROM_SIZE: 0,
ENABLE_DM: 1,
DM_BASE: 32'h0,
DM_SIZE: LMEM_SIZE,
ENABLE_PGAS: 0,
PGAS_BASE: 0,
PGAS_SIZE: 0,
//CORE_ENABLE_FPU: 0,
//CORE_ENABLE_PERFCOUNTERS: 0,
NA_ENABLE_MPSIMPLE: 1,
NA_ENABLE_DMA: 1,
NA_DMA_GENIRQ: 1,
NA_DMA_ENTRIES: 4,
USE_DEBUG: 1'(USE_DEBUG),
DEBUG_STM: 1,
DEBUG_CTM: 1,
//DEBUG_DEM_UART: 0,
DEBUG_SUBNET_BITS: 6,
DEBUG_LOCAL_SUBNET: 0,
DEBUG_ROUTER_BUFFER_SIZE: 4,
DEBUG_MAX_PKT_LEN: 12
};
localparam config_t CONFIG = derive_config(BASE_CONFIG);
//logic rst_sys, rst_cpu;
logic cpu_stall;
assign cpu_stall = 0;
// In Verilator, we feed clk and rst from the C++ toplevel, in ModelSim & Co.
// these signals are generated inside this testbench.
`ifndef verilator
reg clk;
reg rst_sys;
`endif
// Reset signals
// In simulations with debug system, these signals can be triggered through
// the host software. In simulations without debug systems, we only rely on
// the global reset signal.
generate
if (CONFIG.USE_DEBUG == 0) begin : gen_use_debug_rst
assign rst_sys = rst;
assign rst_cpu = rst;
end
endgenerate
/* glip_channel c_glip_in(.*);
glip_channel c_glip_out(.*);
logic com_rst, logic_rst;
if (CONFIG.USE_DEBUG == 1) begin : gen_use_debug_glip
// TCP communication interface (simulation only)
glip_tcp_toplevel
u_glip
(
.*,
.clk_io (clk),
.clk_logic (clk),
.fifo_in (c_glip_in),
.fifo_out (c_glip_out)
);
end // if (CONFIG.USE_DEBUG == 1)
*/
// Monitor system behavior in simulation
genvar t;
genvar i;
wire [CONFIG.NUMCTS*CONFIG.CORES_PER_TILE-1:0] termination;
/* generate
for (t = 0; t < CONFIG.NUMCTS; t = t + 1) begin : gen_tracemon_ct
logic [31:0] trace_r3 [0:CONFIG.CORES_PER_TILE-1];
mor1kx_trace_exec [CONFIG.CORES_PER_TILE-1:0] trace;
assign trace = u_system.gen_ct[t].u_ct.trace;
for (i = 0; i < CONFIG.CORES_PER_TILE; i = i + 1) begin : gen_tracemon_core
r3_checker
u_r3_checker(
.clk(clk),
.valid(trace[i].valid),
.we (trace[i].wben),
.addr (trace[i].wbreg),
.data (trace[i].wbdata),
.r3 (trace_r3[i])
);
trace_monitor
#(
.STDOUT_FILENAME({"stdout.",index2string((t*CONFIG.CORES_PER_TILE)+i)}),
.TRACEFILE_FILENAME({"trace.",index2string((t*CONFIG.CORES_PER_TILE)+i)}),
.ENABLE_TRACE(0),
.ID((t*CONFIG.CORES_PER_TILE)+i),
.TERM_CROSS_NUM(CONFIG.NUMCTS*CONFIG.CORES_PER_TILE)
)
u_mon0(
.termination (termination[(t*CONFIG.CORES_PER_TILE)+i]),
.clk (clk),
.enable (trace[i].valid),
.wb_pc (trace[i].pc),
.wb_insn (trace[i].insn),
.r3 (trace_r3[i]),
.termination_all (termination)
);
end
end
endgenerate*/
system_noc
#(.CONFIG(CONFIG))
u_system
(.clk (clk),
.rst_sys (rst),
//.c_glip_in (c_glip_in),
//.c_glip_out (c_glip_out),
.wb_ext_ack_o (4'hx),
.wb_ext_err_o (4'hx),
.wb_ext_rty_o (4'hx),
.wb_ext_dat_o (128'hx),
.wb_ext_adr_i (),
.wb_ext_cyc_i (),
.wb_ext_dat_i (),
.wb_ext_sel_i (),
.wb_ext_stb_i (),
.wb_ext_we_i (),
.wb_ext_cab_i (),
.wb_ext_cti_i (),
.wb_ext_bte_i ()
);
// Generate testbench signals.
// In Verilator, these signals are generated in the C++ toplevel testbench
`ifndef verilator
initial begin
clk = 1'b1;
rst_sys = 1'b1;
#15;
rst_sys = 1'b0;
end
//always clk = #1.25 ~clk;
`endif
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../../src/rtl/*/verilog")
// verilog-auto-inst-param-value: t
// End:
|
//////////////////////////////////////////////////////////////////////
//// ////
//// raminfr.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// Inferrable Distributed RAM for FIFOs ////
//// ////
//// Known problems (limits): ////
//// None . ////
//// ////
//// To Do: ////
//// Nothing so far. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// ////
//// Created: 2002/07/22 ////
//// Last Updated: 2002/07/22 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
//Following is the Verilog code for a dual-port RAM with asynchronous read.
module raminfr
(clk, we, a, dpra, di, dpo);
parameter addr_width = 4;
parameter data_width = 8;
parameter depth = 16;
input clk;
input we;
input [addr_width-1:0] a;
input [addr_width-1:0] dpra;
input [data_width-1:0] di;
//output [data_width-1:0] spo;
output [data_width-1:0] dpo;
reg [data_width-1:0] ram [depth-1:0];
wire [data_width-1:0] dpo;
wire [data_width-1:0] di;
wire [addr_width-1:0] a;
wire [addr_width-1:0] dpra;
always @(posedge clk) begin
if (we)
ram[a] <= di;
end
// assign spo = ram[a];
assign dpo = ram[dpra];
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_defines.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// Defines of the Core ////
//// ////
//// Known problems (limits): ////
//// None ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) = ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.13 2003/06/11 16:37:47 gorban
// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
//
// Revision 1.12 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.10 2001/12/11 08:55:40 mohor
// Scratch register define added.
//
// Revision 1.9 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.8 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.7 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.6 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.5 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.4 2001/05/21 19:12:02 gorban
// Corrected some Linter messages.
//
// Revision 1.3 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:11+02 jacob
// Initial revision
//
//
// Uncomment this if you want your UART to have
// 16xBaudrate output port.
// If defined, the enable signal will be used to drive baudrate_o signal
// It's frequency is 16xbaudrate
// `define UART_HAS_BAUDRATE_OUTPUT
// Register addresses
`define UART_REG_RB 3'd0 // receiver buffer
`define UART_REG_TR 3'd0 // transmitter
`define UART_REG_IE 3'd1 // Interrupt enable
`define UART_REG_II 3'd2 // Interrupt identification
`define UART_REG_FC 3'd2 // FIFO control
`define UART_REG_LC 3'd3 // Line Control
`define UART_REG_MC 3'd4 // Modem control
`define UART_REG_LS 3'd5 // Line status
`define UART_REG_MS 3'd6 // Modem status
`define UART_REG_SR 3'd7 // Scratch register
`define UART_REG_DL1 3'd0 // Divisor latch bytes (1-2)
`define UART_REG_DL2 3'd1
// Interrupt Enable register bits
`define UART_IE_RDA 0 // Received Data available interrupt
`define UART_IE_THRE 1 // Transmitter Holding Register empty interrupt
`define UART_IE_RLS 2 // Receiver Line Status Interrupt
`define UART_IE_MS 3 // Modem Status Interrupt
// Interrupt Identification register bits
`define UART_II_IP 0 // Interrupt pending when 0
`define UART_II_II 3:1 // Interrupt identification
// Interrupt identification values for bits 3:1
`define UART_II_RLS 3'b011 // Receiver Line Status
`define UART_II_RDA 3'b010 // Receiver Data available
`define UART_II_TI 3'b110 // Timeout Indication
`define UART_II_THRE 3'b001 // Transmitter Holding Register empty
`define UART_II_MS 3'b000 // Modem Status
// FIFO Control Register bits
`define UART_FC_TL 1:0 // Trigger level
// FIFO trigger level values
`define UART_FC_1 2'b00
`define UART_FC_4 2'b01
`define UART_FC_8 2'b10
`define UART_FC_14 2'b11
// Line Control register bits
`define UART_LC_BITS 1:0 // bits in character
`define UART_LC_SB 2 // stop bits
`define UART_LC_PE 3 // parity enable
`define UART_LC_EP 4 // even parity
`define UART_LC_SP 5 // stick parity
`define UART_LC_BC 6 // Break control
`define UART_LC_DL 7 // Divisor Latch access bit
// Modem Control register bits
`define UART_MC_DTR 0
`define UART_MC_RTS 1
`define UART_MC_OUT1 2
`define UART_MC_OUT2 3
`define UART_MC_LB 4 // Loopback mode
// Line Status Register bits
`define UART_LS_DR 0 // Data ready
`define UART_LS_OE 1 // Overrun Error
`define UART_LS_PE 2 // Parity Error
`define UART_LS_FE 3 // Framing Error
`define UART_LS_BI 4 // Break interrupt
`define UART_LS_TFE 5 // Transmit FIFO is empty
`define UART_LS_TE 6 // Transmitter Empty indicator
`define UART_LS_EI 7 // Error indicator
// Modem Status Register bits
`define UART_MS_DCTS 0 // Delta signals
`define UART_MS_DDSR 1
`define UART_MS_TERI 2
`define UART_MS_DDCD 3
`define UART_MS_CCTS 4 // Complement signals
`define UART_MS_CDSR 5
`define UART_MS_CRI 6
`define UART_MS_CDCD 7
// FIFO parameter defines
`define UART_FIFO_WIDTH 8
`define UART_FIFO_DEPTH 16
`define UART_FIFO_POINTER_W 4
`define UART_FIFO_COUNTER_W 5
// receiver fifo has width 11 because it has break, parity and framing error bits
`define UART_FIFO_REC_WIDTH 11
`define VERBOSE_WB 0 // All activity on the WISHBONE is recorded
`define VERBOSE_LINE_STATUS 0 // Details about the lsr (line status register)
`define FAST_TEST 1 // 64/1024 packets are sent
// Define the prescaler (divisor) for the UART as the initialization code that is part
// of the or1k toolchain does not seem to be setting it at all
`define PRESCALER_PRESET_HARD
`define PRESCALER_LOW_PRESET 8'd27
`define PRESCALER_HIGH_PRESET 8'd0
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_receiver.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core receiver logic ////
//// ////
//// Known problems (limits): ////
//// None known ////
//// ////
//// To Do: ////
//// Thourough testing. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.29 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.28 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.27 2001/12/30 20:39:13 mohor
// More than one character was stored in case of break. End of the break
// was not detected correctly.
//
// Revision 1.26 2001/12/20 13:28:27 mohor
// Missing declaration of rf_push_q fixed.
//
// Revision 1.25 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.24 2001/12/19 08:03:34 mohor
// Warnings cleared.
//
// Revision 1.23 2001/12/19 07:33:54 mohor
// Synplicity was having troubles with the comment.
//
// Revision 1.22 2001/12/17 14:46:48 mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.21 2001/12/13 10:31:16 mohor
// timeout irq must be set regardless of the rda irq (rda irq does not reset the
// timeout counter).
//
// Revision 1.20 2001/12/10 19:52:05 gorban
// Igor fixed break condition bugs
//
// Revision 1.19 2001/12/06 14:51:04 gorban
// Bug in LSR[0] is fixed.
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
//
// Revision 1.18 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.17 2001/11/28 19:36:39 gorban
// Fixed: timeout and break didn't pay attention to current data format when counting time
//
// Revision 1.16 2001/11/27 22:17:09 gorban
// Fixed bug that prevented synthesis in uart_receiver.v
//
// Revision 1.15 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.14 2001/11/10 12:43:21 gorban
// Logic Synthesis bugs fixed. Some other minor changes
//
// Revision 1.13 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.12 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.11 2001/10/31 15:19:22 gorban
// Fixes to break and timeout conditions
//
// Revision 1.10 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.9 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.6 2001/06/23 11:21:48 gorban
// DL made 16-bit long. Fixed transmission/reception bugs.
//
// Revision 1.5 2001/06/02 14:28:14 gorban
// Fixed receiver and transmitter. Major bug fixed.
//
// Revision 1.4 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/27 17:37:49 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2 2001/05/21 19:12:02 gorban
// Corrected some Linter messages.
//
// Revision 1.1 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:11+02 jacob
// Initial revision
//
//
`include "uart_defines.v"
module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable,
counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
input clk;
input wb_rst_i;
input [7:0] lcr;
input rf_pop;
input srx_pad_i;
input enable;
input rx_reset;
input lsr_mask;
output [9:0] counter_t;
output [`UART_FIFO_COUNTER_W-1:0] rf_count;
output [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
output rf_overrun;
output rf_error_bit;
output [3:0] rstate;
output rf_push_pulse;
reg [3:0] rstate;
reg [3:0] rcounter16;
reg [2:0] rbit_counter;
reg [7:0] rshift; // receiver shift register
reg rparity; // received parity
reg rparity_error;
reg rframing_error; // framing error flag
reg rparity_xor;
reg [7:0] counter_b; // counts the 0 (low) signals
reg rf_push_q;
// RX FIFO signals
reg [`UART_FIFO_REC_WIDTH-1:0] rf_data_in;
wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
wire rf_push_pulse;
reg rf_push;
wire rf_pop;
wire rf_overrun;
wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
wire rf_error_bit; // an error (parity or framing) is inside the fifo
wire break_error = (counter_b == 0);
// RX FIFO instance
uart_rfifo #(`UART_FIFO_REC_WIDTH) fifo_rx(
.clk( clk ),
.wb_rst_i( wb_rst_i ),
.data_in( rf_data_in ),
.data_out( rf_data_out ),
.push( rf_push_pulse ),
.pop( rf_pop ),
.overrun( rf_overrun ),
.count( rf_count ),
.error_bit( rf_error_bit ),
.fifo_reset( rx_reset ),
.reset_status(lsr_mask)
);
wire rcounter16_eq_7 = (rcounter16 == 4'd7);
wire rcounter16_eq_0 = (rcounter16 == 4'd0);
wire [3:0] rcounter16_minus_1 = rcounter16 - 3'd1;
parameter sr_idle = 4'd0;
parameter sr_rec_start = 4'd1;
parameter sr_rec_bit = 4'd2;
parameter sr_rec_parity = 4'd3;
parameter sr_rec_stop = 4'd4;
parameter sr_check_parity = 4'd5;
parameter sr_rec_prepare = 4'd6;
parameter sr_end_bit = 4'd7;
parameter sr_ca_lc_parity = 4'd8;
parameter sr_wait1 = 4'd9;
parameter sr_push = 4'd10;
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
begin
rstate <= sr_idle;
rcounter16 <= 0;
rbit_counter <= 0;
rparity_xor <= 1'b0;
rframing_error <= 1'b0;
rparity_error <= 1'b0;
rparity <= 1'b0;
rshift <= 0;
rf_push <= 1'b0;
rf_data_in <= 0;
end
else
if (enable)
begin
case (rstate)
sr_idle : begin
rf_push <= 1'b0;
rf_data_in <= 0;
rcounter16 <= 4'b1110;
if (srx_pad_i==1'b0 & ~break_error) // detected a pulse (start bit?)
begin
rstate <= sr_rec_start;
end
end
sr_rec_start : begin
rf_push <= 1'b0;
if (rcounter16_eq_7) // check the pulse
if (srx_pad_i==1'b1) // no start bit
rstate <= sr_idle;
else // start bit detected
rstate <= sr_rec_prepare;
rcounter16 <= rcounter16_minus_1;
end
sr_rec_prepare:begin
case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word
2'b00 : rbit_counter <= 3'b100;
2'b01 : rbit_counter <= 3'b101;
2'b10 : rbit_counter <= 3'b110;
2'b11 : rbit_counter <= 3'b111;
endcase
if (rcounter16_eq_0)
begin
rstate <= sr_rec_bit;
rcounter16 <= 4'b1110;
rshift <= 0;
end
else
rstate <= sr_rec_prepare;
rcounter16 <= rcounter16_minus_1;
end
sr_rec_bit : begin
if (rcounter16_eq_0)
rstate <= sr_end_bit;
if (rcounter16_eq_7) // read the bit
case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word
2'b00 : rshift[4:0] <= {srx_pad_i, rshift[4:1]};
2'b01 : rshift[5:0] <= {srx_pad_i, rshift[5:1]};
2'b10 : rshift[6:0] <= {srx_pad_i, rshift[6:1]};
2'b11 : rshift[7:0] <= {srx_pad_i, rshift[7:1]};
endcase
rcounter16 <= rcounter16_minus_1;
end
sr_end_bit : begin
if (rbit_counter==3'b0) // no more bits in word
if (lcr[`UART_LC_PE]) // choose state based on parity
rstate <= sr_rec_parity;
else
begin
rstate <= sr_rec_stop;
rparity_error <= 1'b0; // no parity - no error :)
end
else // else we have more bits to read
begin
rstate <= sr_rec_bit;
rbit_counter <= rbit_counter - 3'd1;
end
rcounter16 <= 4'b1110;
end
sr_rec_parity: begin
if (rcounter16_eq_7) // read the parity
begin
rparity <= srx_pad_i;
rstate <= sr_ca_lc_parity;
end
rcounter16 <= rcounter16_minus_1;
end
sr_ca_lc_parity : begin // rcounter equals 6
rcounter16 <= rcounter16_minus_1;
rparity_xor <= ^{rshift,rparity}; // calculate parity on all incoming data
rstate <= sr_check_parity;
end
sr_check_parity: begin // rcounter equals 5
case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
2'b00: rparity_error <= rparity_xor == 0; // no error if parity 1
2'b01: rparity_error <= ~rparity; // parity should sticked to 1
2'b10: rparity_error <= rparity_xor == 1; // error if parity is odd
2'b11: rparity_error <= rparity; // parity should be sticked to 0
endcase
rcounter16 <= rcounter16_minus_1;
rstate <= sr_wait1;
end
sr_wait1 : if (rcounter16_eq_0)
begin
rstate <= sr_rec_stop;
rcounter16 <= 4'b1110;
end
else
rcounter16 <= rcounter16_minus_1;
sr_rec_stop : begin
if (rcounter16_eq_7) // read the parity
begin
rframing_error <= !srx_pad_i; // no framing error if input is 1 (stop bit)
rstate <= sr_push;
end
rcounter16 <= rcounter16_minus_1;
end
sr_push : begin
///////////////////////////////////////
// $display($time, ": received: %b", rf_data_in);
if(srx_pad_i | break_error)
begin
if(break_error)
rf_data_in <= {8'b0, 3'b100}; // break input (empty character) to receiver FIFO
else
rf_data_in <= {rshift, 1'b0, rparity_error, rframing_error};
rf_push <= 1'b1;
rstate <= sr_idle;
end
else if(~rframing_error) // There's always a framing before break_error -> wait for break or srx_pad_i
begin
rf_data_in <= {rshift, 1'b0, rparity_error, rframing_error};
rf_push <= 1'b1;
rcounter16 <= 4'b1110;
rstate <= sr_rec_start;
end
end
default : rstate <= sr_idle;
endcase
end // if (enable)
end // always of receiver
always @ (posedge clk or posedge wb_rst_i)
begin
if(wb_rst_i)
rf_push_q <= 0;
else
rf_push_q <= rf_push;
end
assign rf_push_pulse = rf_push & ~rf_push_q;
//
// Break condition detection.
// Works in conjuction with the receiver state machine
reg [9:0] toc_value; // value to be set to timeout counter
always @(lcr)
case (lcr[3:0])
4'b0000 : toc_value = 447; // 7 bits
4'b0100 : toc_value = 479; // 7.5 bits
4'b0001, 4'b1000 : toc_value = 511; // 8 bits
4'b1100 : toc_value = 543; // 8.5 bits
4'b0010, 4'b0101, 4'b1001 : toc_value = 575; // 9 bits
4'b0011, 4'b0110, 4'b1010, 4'b1101 : toc_value = 639; // 10 bits
4'b0111, 4'b1011, 4'b1110 : toc_value = 703; // 11 bits
4'b1111 : toc_value = 767; // 12 bits
endcase // case(lcr[3:0])
wire [7:0] brc_value; // value to be set to break counter
assign brc_value = toc_value[9:2]; // the same as timeout but 1 insead of 4 character times
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
counter_b <= 8'd159;
else
if (srx_pad_i)
counter_b <= brc_value; // character time length - 1
else
if(enable & counter_b != 8'b0) // only work on enable times break not reached.
counter_b <= counter_b - 8'd1; // decrement break counter
end // always of break condition detection
///
/// Timeout condition detection
reg [9:0] counter_t; // counts the timeout condition clocks
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
counter_t <= 10'd639; // 10 bits for the default 8N1
else
if(rf_push_pulse || rf_pop || rf_count == 0) // counter is reset when RX FIFO is empty, accessed or above trigger level
counter_t <= toc_value;
else
if (enable && counter_t != 10'b0) // we don't want to underflow
counter_t <= counter_t - 10'd1;
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_regs.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// Registers of the uart 16550 core ////
//// ////
//// Known problems (limits): ////
//// Inserts 1 wait state in all WISHBONE transfers ////
//// ////
//// To Do: ////
//// Nothing or verification. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: (See log for the revision history ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.41 2004/05/21 11:44:41 tadejm
// Added synchronizer flops for RX input.
//
// Revision 1.40 2003/06/11 16:37:47 gorban
// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
//
// Revision 1.39 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.38 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.37 2001/12/27 13:24:09 mohor
// lsr[7] was not showing overrun errors.
//
// Revision 1.36 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.35 2001/12/19 08:03:34 mohor
// Warnings cleared.
//
// Revision 1.34 2001/12/19 07:33:54 mohor
// Synplicity was having troubles with the comment.
//
// Revision 1.33 2001/12/17 10:14:43 mohor
// Things related to msr register changed. After THRE IRQ occurs, and one
// character is written to the transmit fifo, the detection of the THRE bit in the
// LSR is delayed for one character time.
//
// Revision 1.32 2001/12/14 13:19:24 mohor
// MSR register fixed.
//
// Revision 1.31 2001/12/14 10:06:58 mohor
// After reset modem status register MSR should be reset.
//
// Revision 1.30 2001/12/13 10:09:13 mohor
// thre irq should be cleared only when being source of interrupt.
//
// Revision 1.29 2001/12/12 09:05:46 mohor
// LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).
//
// Revision 1.28 2001/12/10 19:52:41 gorban
// Scratch register added
//
// Revision 1.27 2001/12/06 14:51:04 gorban
// Bug in LSR[0] is fixed.
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
//
// Revision 1.26 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.25 2001/11/28 19:36:39 gorban
// Fixed: timeout and break didn't pay attention to current data format when counting time
//
// Revision 1.24 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.23 2001/11/12 21:57:29 gorban
// fixed more typo bugs
//
// Revision 1.22 2001/11/12 15:02:28 mohor
// lsr1r error fixed.
//
// Revision 1.21 2001/11/12 14:57:27 mohor
// ti_int_pnd error fixed.
//
// Revision 1.20 2001/11/12 14:50:27 mohor
// ti_int_d error fixed.
//
// Revision 1.19 2001/11/10 12:43:21 gorban
// Logic Synthesis bugs fixed. Some other minor changes
//
// Revision 1.18 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.17 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.16 2001/11/02 09:55:16 mohor
// no message
//
// Revision 1.15 2001/10/31 15:19:22 gorban
// Fixes to break and timeout conditions
//
// Revision 1.14 2001/10/29 17:00:46 gorban
// fixed parity sending and tx_fifo resets over- and underrun
//
// Revision 1.13 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.12 2001/10/19 16:21:40 gorban
// Changes data_out to be synchronous again as it should have been.
//
// Revision 1.11 2001/10/18 20:35:45 gorban
// small fix
//
// Revision 1.10 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.9 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.10 2001/06/23 11:21:48 gorban
// DL made 16-bit long. Fixed transmission/reception bugs.
//
// Revision 1.9 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.8 2001/05/29 20:05:04 gorban
// Fixed some bugs and synthesis problems.
//
// Revision 1.7 2001/05/27 17:37:49 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.6 2001/05/21 19:12:02 gorban
// Corrected some Linter messages.
//
// Revision 1.5 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:11+02 jacob
// Initial revision
//
//
`include "uart_defines.v"
`define UART_DL1 7:0
`define UART_DL2 15:8
module uart_regs
#(parameter SIM = 0)
(clk,
wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_re_i,
// additional signals
modem_inputs,
stx_pad_o, srx_pad_i,
rts_pad_o, dtr_pad_o, int_o
`ifdef UART_HAS_BAUDRATE_OUTPUT
, baud_o
`endif
);
input clk;
input wb_rst_i;
input [2:0] wb_addr_i;
input [7:0] wb_dat_i;
output [7:0] wb_dat_o;
input wb_we_i;
input wb_re_i;
output stx_pad_o;
input srx_pad_i;
input [3:0] modem_inputs;
output rts_pad_o;
output dtr_pad_o;
output int_o;
`ifdef UART_HAS_BAUDRATE_OUTPUT
output baud_o;
`endif
wire [3:0] modem_inputs;
reg enable;
`ifdef UART_HAS_BAUDRATE_OUTPUT
assign baud_o = enable; // baud_o is actually the enable signal
`endif
wire stx_pad_o; // received from transmitter module
wire srx_pad_i;
wire srx_pad;
reg [7:0] wb_dat_o;
wire [2:0] wb_addr_i;
wire [7:0] wb_dat_i;
reg [3:0] ier;
reg [3:0] iir;
reg [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
reg [4:0] mcr;
reg [7:0] lcr;
reg [7:0] msr;
reg [15:0] dl; // 32-bit divisor latch
reg [7:0] scratch; // UART scratch register
reg start_dlc; // activate dlc on writing to UART_DL1
reg lsr_mask_d; // delay for lsr_mask condition
reg msi_reset; // reset MSR 4 lower bits indicator
//reg threi_clear; // THRE interrupt clear flag
reg [15:0] dlc; // 32-bit divisor latch counter
reg int_o;
reg [3:0] trigger_level; // trigger level of the receiver FIFO
reg rx_reset;
reg tx_reset;
wire dlab; // divisor latch access bit
wire cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i; // modem status bits
wire loopback; // loopback bit (MCR bit 4)
wire cts, dsr, ri, dcd; // effective signals
wire cts_c, dsr_c, ri_c, dcd_c; // Complement effective signals (considering loopback)
wire rts_pad_o, dtr_pad_o; // modem control outputs
// LSR bits wires and regs
wire [7:0] lsr;
wire lsr0, lsr1, lsr2, lsr3, lsr4, lsr5, lsr6, lsr7;
reg lsr0r, lsr1r, lsr2r, lsr3r, lsr4r, lsr5r, lsr6r, lsr7r;
wire lsr_mask; // lsr_mask
//
// ASSINGS
//
assign lsr[7:0] = { lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, lsr0r };
assign {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs;
assign {cts, dsr, ri, dcd} = ~{cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
assign {cts_c, dsr_c, ri_c, dcd_c} = loopback ? {mcr[`UART_MC_RTS],mcr[`UART_MC_DTR],mcr[`UART_MC_OUT1],mcr[`UART_MC_OUT2]}
: {cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
assign dlab = lcr[`UART_LC_DL];
assign loopback = mcr[4];
// assign modem outputs
assign rts_pad_o = mcr[`UART_MC_RTS];
assign dtr_pad_o = mcr[`UART_MC_DTR];
// Interrupt signals
wire rls_int; // receiver line status interrupt
wire rda_int; // receiver data available interrupt
wire ti_int; // timeout indicator interrupt
wire thre_int; // transmitter holding register empty interrupt
wire ms_int; // modem status interrupt
// FIFO signals
reg tf_push;
reg rf_pop;
wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
wire rf_error_bit; // an error (parity or framing) is inside the fifo
wire rf_overrun;
wire rf_push_pulse;
wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
wire [2:0] tstate;
wire [3:0] rstate;
wire [9:0] counter_t;
wire thre_set_en; // THRE status is delayed one character time when a character is written to fifo.
reg [7:0] block_cnt; // While counter counts, THRE status is blocked (delayed one character cycle)
reg [7:0] block_value; // One character length minus stop bit
// Transmitter Instance
wire serial_out;
uart_transmitter #(.SIM (SIM)) transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, serial_out, tstate, tf_count, tx_reset, lsr_mask);
// Synchronizing and sampling serial RX input
uart_sync_flops i_uart_sync_flops
(
.rst_i (wb_rst_i),
.clk_i (clk),
.stage1_rst_i (1'b0),
.stage1_clk_en_i (1'b1),
.async_dat_i (srx_pad_i),
.sync_dat_o (srx_pad)
);
defparam i_uart_sync_flops.width = 1;
defparam i_uart_sync_flops.init_value = 1'b1;
// handle loopback
wire serial_in = loopback ? serial_out : srx_pad;
assign stx_pad_o = loopback ? 1'b1 : serial_out;
// Receiver Instance
uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, serial_in, enable,
counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
// Asynchronous reading here because the outputs are sampled in uart_wb.v file
always @(dl or dlab or ier or iir or scratch
or lcr or lsr or msr or rf_data_out or wb_addr_i or wb_re_i) // asynchrounous reading
begin
case (wb_addr_i)
`UART_REG_RB : wb_dat_o = dlab ? dl[`UART_DL1] : rf_data_out[10:3];
`UART_REG_IE : wb_dat_o = dlab ? dl[`UART_DL2] : {4'd0,ier};
`UART_REG_II : wb_dat_o = {4'b1100,iir};
`UART_REG_LC : wb_dat_o = lcr;
`UART_REG_LS : wb_dat_o = lsr;
`UART_REG_MS : wb_dat_o = msr;
`UART_REG_SR : wb_dat_o = scratch;
default: wb_dat_o = 8'b0; // ??
endcase // case(wb_addr_i)
end // always @ (dl or dlab or ier or iir or scratch...
// rf_pop signal handling
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
rf_pop <= 0;
else
if (rf_pop) // restore the signal to 0 after one clock cycle
rf_pop <= 0;
else
if (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab)
rf_pop <= 1; // advance read pointer
end
wire lsr_mask_condition;
wire iir_read;
wire msr_read;
wire fifo_read;
wire fifo_write;
assign lsr_mask_condition = (wb_re_i && wb_addr_i == `UART_REG_LS && !dlab);
assign iir_read = (wb_re_i && wb_addr_i == `UART_REG_II && !dlab);
assign msr_read = (wb_re_i && wb_addr_i == `UART_REG_MS && !dlab);
assign fifo_read = (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab);
assign fifo_write = (wb_we_i && wb_addr_i == `UART_REG_TR && !dlab);
// lsr_mask_d delayed signal handling
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
lsr_mask_d <= 0;
else // reset bits in the Line Status Register
lsr_mask_d <= lsr_mask_condition;
end
// lsr_mask is rise detected
assign lsr_mask = lsr_mask_condition && ~lsr_mask_d;
// msi_reset signal handling
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
msi_reset <= 1;
else
if (msi_reset)
msi_reset <= 0;
else
if (msr_read)
msi_reset <= 1; // reset bits in Modem Status Register
end
//
// WRITES AND RESETS //
//
// Line Control Register
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
lcr <= 8'b00000011; // 8n1 setting
else
if (wb_we_i && wb_addr_i==`UART_REG_LC)
lcr <= wb_dat_i;
// Interrupt Enable Register or UART_DL2
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
begin
ier <= 4'b0000; // no interrupts after reset
`ifdef PRESCALER_PRESET_HARD
dl[`UART_DL2] <= `PRESCALER_HIGH_PRESET;
`else
dl[`UART_DL2] <= 8'b0;
`endif
end
else
if (wb_we_i && wb_addr_i==`UART_REG_IE)
if (dlab)
begin
dl[`UART_DL2] <=
`ifdef PRESCALER_PRESET_HARD
dl[`UART_DL2];
`else
wb_dat_i;
`endif
end
else
ier <= wb_dat_i[3:0]; // ier uses only 4 lsb
// FIFO Control Register and rx_reset, tx_reset signals
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) begin
fcr <= 2'b11;
rx_reset <= 0;
tx_reset <= 0;
end else
if (wb_we_i && wb_addr_i==`UART_REG_FC) begin
fcr <= wb_dat_i[7:6];
rx_reset <= wb_dat_i[1];
tx_reset <= wb_dat_i[2];
end else begin
rx_reset <= 0;
tx_reset <= 0;
end
// Modem Control Register
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
mcr <= 5'b0;
else
if (wb_we_i && wb_addr_i==`UART_REG_MC)
mcr <= wb_dat_i[4:0];
// Scratch register
// Line Control Register
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
scratch <= 0; // 8n1 setting
else
if (wb_we_i && wb_addr_i==`UART_REG_SR)
scratch <= wb_dat_i;
// TX_FIFO or UART_DL1
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
begin
`ifdef PRESCALER_PRESET_HARD
dl[`UART_DL1] <= `PRESCALER_LOW_PRESET;
`else
dl[`UART_DL1] <= 8'b0;
`endif
tf_push <= 1'b0;
start_dlc <= 1'b0;
end
else
if (wb_we_i && wb_addr_i==`UART_REG_TR)
if (dlab)
begin
`ifdef PRESCALER_PRESET_HARD
dl[`UART_DL1] <= dl[`UART_DL1];
`else
dl[`UART_DL1] <= wb_dat_i;
`endif
start_dlc <= 1'b1; // enable DL counter
tf_push <= 1'b0;
end
else
begin
tf_push <= 1'b1;
start_dlc <= 1'b0;
end // else: !if(dlab)
else
begin
start_dlc <= 1'b0;
tf_push <= 1'b0;
end // else: !if(dlab)
// Receiver FIFO trigger level selection logic (asynchronous mux)
always @(fcr)
case (fcr[`UART_FC_TL])
2'b00 : trigger_level = 1;
2'b01 : trigger_level = 4;
2'b10 : trigger_level = 8;
2'b11 : trigger_level = 14;
endcase // case(fcr[`UART_FC_TL])
//
// STATUS REGISTERS //
//
// Modem Status Register
reg [3:0] delayed_modem_signals;
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
begin
msr <= 0;
delayed_modem_signals[3:0] <= 0;
end
else begin
msr[`UART_MS_DDCD:`UART_MS_DCTS] <= msi_reset ? 4'b0 :
msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ delayed_modem_signals[3:0]);
msr[`UART_MS_CDCD:`UART_MS_CCTS] <= {dcd_c, ri_c, dsr_c, cts_c};
delayed_modem_signals[3:0] <= {dcd, ri, dsr, cts};
end
end
// Line Status Register
// activation conditions
assign lsr0 = (rf_count==0 && rf_push_pulse); // data in receiver fifo available set condition
assign lsr1 = rf_overrun; // Receiver overrun error
assign lsr2 = rf_data_out[1]; // parity error bit
assign lsr3 = rf_data_out[0]; // framing error bit
assign lsr4 = rf_data_out[2]; // break error in the character
assign lsr5 = (tf_count==5'b0 && thre_set_en); // transmitter fifo is empty
assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate == /*`S_IDLE */ 0)); // transmitter empty
assign lsr7 = rf_error_bit | rf_overrun;
// lsr bit0 (receiver data available)
reg lsr0_d;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr0_d <= 0;
else lsr0_d <= lsr0;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr0r <= 0;
else lsr0r <= (rf_count==1 && rf_pop && !rf_push_pulse || rx_reset) ? 1'b0 : // deassert condition
lsr0r || (lsr0 && ~lsr0_d); // set on rise of lsr0 and keep asserted until deasserted
// lsr bit 1 (receiver overrun)
reg lsr1_d; // delayed
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr1_d <= 0;
else lsr1_d <= lsr1;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr1r <= 0;
else lsr1r <= lsr_mask ? 1'b0 : lsr1r || (lsr1 && ~lsr1_d); // set on rise
// lsr bit 2 (parity error)
reg lsr2_d; // delayed
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr2_d <= 0;
else lsr2_d <= lsr2;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr2r <= 0;
else lsr2r <= lsr_mask ? 1'b0 : lsr2r || (lsr2 && ~lsr2_d); // set on rise
// lsr bit 3 (framing error)
reg lsr3_d; // delayed
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr3_d <= 0;
else lsr3_d <= lsr3;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr3r <= 0;
else lsr3r <= lsr_mask ? 1'b0 : lsr3r || (lsr3 && ~lsr3_d); // set on rise
// lsr bit 4 (break indicator)
reg lsr4_d; // delayed
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr4_d <= 0;
else lsr4_d <= lsr4;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr4r <= 0;
else lsr4r <= lsr_mask ? 1'b0 : lsr4r || (lsr4 && ~lsr4_d);
// lsr bit 5 (transmitter fifo is empty)
reg lsr5_d;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr5_d <= 1;
else lsr5_d <= lsr5;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr5r <= 1;
else lsr5r <= (fifo_write) ? 1'b0 : lsr5r || (lsr5 && ~lsr5_d);
// lsr bit 6 (transmitter empty indicator)
reg lsr6_d;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr6_d <= 1;
else lsr6_d <= lsr6;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr6r <= 1;
else lsr6r <= (fifo_write) ? 1'b0 : lsr6r || (lsr6 && ~lsr6_d);
// lsr bit 7 (error in fifo)
reg lsr7_d;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr7_d <= 0;
else lsr7_d <= lsr7;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr7r <= 0;
else lsr7r <= lsr_mask ? 1'b0 : lsr7r || (lsr7 && ~lsr7_d);
// Frequency divider
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
dlc <= 0;
else
if (start_dlc | ~ (|dlc))
dlc <= dl - 16'd1; // preset counter
else
dlc <= dlc - 16'd1; // decrement counter
end
// Enable signal generation logic
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
enable <= 1'b0;
else
if (|dl & ~(|dlc)) // dl>0 & dlc==0
enable <= 1'b1;
else
enable <= 1'b0;
end
// Delaying THRE status for one character cycle after a character is written to an empty fifo.
always @(lcr)
case (lcr[3:0])
4'b0000 : block_value = 95; // 6 bits
4'b0100 : block_value = 103; // 6.5 bits
4'b0001, 4'b1000 : block_value = 111; // 7 bits
4'b1100 : block_value = 119; // 7.5 bits
4'b0010, 4'b0101, 4'b1001 : block_value = 127; // 8 bits
4'b0011, 4'b0110, 4'b1010, 4'b1101 : block_value = 143; // 9 bits
4'b0111, 4'b1011, 4'b1110 : block_value = 159; // 10 bits
4'b1111 : block_value = 175; // 11 bits
endcase // case(lcr[3:0])
// Counting time of one character minus stop bit
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
block_cnt <= 8'd0;
else
if(lsr5r & fifo_write) // THRE bit set & write to fifo occured
block_cnt <= SIM ? 8'd1 : block_value;
else
if (enable & block_cnt != 8'b0) // only work on enable times
block_cnt <= block_cnt - 8'd1; // decrement break counter
end // always of break condition detection
// Generating THRE status enable signal
assign thre_set_en = ~(|block_cnt);
//
// INTERRUPT LOGIC
//
assign rls_int = ier[`UART_IE_RLS] && (lsr[`UART_LS_OE] || lsr[`UART_LS_PE] || lsr[`UART_LS_FE] || lsr[`UART_LS_BI]);
assign rda_int = ier[`UART_IE_RDA] && (rf_count >= {1'b0,trigger_level});
assign thre_int = ier[`UART_IE_THRE] && lsr[`UART_LS_TFE];
assign ms_int = ier[`UART_IE_MS] && (| msr[3:0]);
assign ti_int = ier[`UART_IE_RDA] && (counter_t == 10'b0) && (|rf_count);
reg rls_int_d;
reg thre_int_d;
reg ms_int_d;
reg ti_int_d;
reg rda_int_d;
// delay lines
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) rls_int_d <= 0;
else rls_int_d <= rls_int;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) rda_int_d <= 0;
else rda_int_d <= rda_int;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) thre_int_d <= 0;
else thre_int_d <= thre_int;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) ms_int_d <= 0;
else ms_int_d <= ms_int;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) ti_int_d <= 0;
else ti_int_d <= ti_int;
// rise detection signals
wire rls_int_rise;
wire thre_int_rise;
wire ms_int_rise;
wire ti_int_rise;
wire rda_int_rise;
assign rda_int_rise = rda_int & ~rda_int_d;
assign rls_int_rise = rls_int & ~rls_int_d;
assign thre_int_rise = thre_int & ~thre_int_d;
assign ms_int_rise = ms_int & ~ms_int_d;
assign ti_int_rise = ti_int & ~ti_int_d;
// interrupt pending flags
reg rls_int_pnd;
reg rda_int_pnd;
reg thre_int_pnd;
reg ms_int_pnd;
reg ti_int_pnd;
// interrupt pending flags assignments
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) rls_int_pnd <= 0;
else
rls_int_pnd <= lsr_mask ? 1'b0 : // reset condition
rls_int_rise ? 1'b1 : // latch condition
rls_int_pnd && ier[`UART_IE_RLS]; // default operation: remove if masked
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) rda_int_pnd <= 0;
else
rda_int_pnd <= ((rf_count == {1'b0,trigger_level}) && fifo_read) ? 1'b0 : // reset condition
rda_int_rise ? 1'b1 : // latch condition
rda_int_pnd && ier[`UART_IE_RDA]; // default operation: remove if masked
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) thre_int_pnd <= 0;
else
thre_int_pnd <= fifo_write || (iir_read & ~iir[`UART_II_IP] & iir[`UART_II_II] == `UART_II_THRE)? 1'b0 :
thre_int_rise ? 1'b1 :
thre_int_pnd && ier[`UART_IE_THRE];
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) ms_int_pnd <= 0;
else
ms_int_pnd <= msr_read ? 1'b0 :
ms_int_rise ? 1'b1 :
ms_int_pnd && ier[`UART_IE_MS];
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) ti_int_pnd <= 0;
else
ti_int_pnd <= fifo_read ? 1'b0 :
ti_int_rise ? 1'b1 :
ti_int_pnd && ier[`UART_IE_RDA];
// end of pending flags
// INT_O logic
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
int_o <= 1'b0;
else
int_o <=
rls_int_pnd ? ~lsr_mask :
rda_int_pnd ? 1'b1 :
ti_int_pnd ? ~fifo_read :
thre_int_pnd ? !(fifo_write & iir_read) :
ms_int_pnd ? ~msr_read :
1'd0; // if no interrupt are pending
end
// Interrupt Identification register
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
iir <= 1;
else
if (rls_int_pnd) // interrupt is pending
begin
iir[`UART_II_II] <= `UART_II_RLS; // set identification register to correct value
iir[`UART_II_IP] <= 1'b0; // and clear the IIR bit 0 (interrupt pending)
end else // the sequence of conditions determines priority of interrupt identification
if (rda_int)
begin
iir[`UART_II_II] <= `UART_II_RDA;
iir[`UART_II_IP] <= 1'b0;
end
else if (ti_int_pnd)
begin
iir[`UART_II_II] <= `UART_II_TI;
iir[`UART_II_IP] <= 1'b0;
end
else if (thre_int_pnd)
begin
iir[`UART_II_II] <= `UART_II_THRE;
iir[`UART_II_IP] <= 1'b0;
end
else if (ms_int_pnd)
begin
iir[`UART_II_II] <= `UART_II_MS;
iir[`UART_II_IP] <= 1'b0;
end else // no interrupt is pending
begin
iir[`UART_II_II] <= 0;
iir[`UART_II_IP] <= 1'b1;
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_rfifo.v (Modified from uart_fifo.v) ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core receiver FIFO ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2002/07/22 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2003/06/11 16:37:47 gorban
// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
//
// Revision 1.2 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.1 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.16 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.15 2001/12/18 09:01:07 mohor
// Bug that was entered in the last update fixed (rx state machine).
//
// Revision 1.14 2001/12/17 14:46:48 mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.13 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.12 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.11 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.10 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.9 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8 2001/08/24 08:48:10 mohor
// FIFO was not cleared after the data was read bug fixed.
//
// Revision 1.7 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.3 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/27 17:37:48 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:12+02 jacob
// Initial revision
//
//
`include "uart_defines.v"
module uart_rfifo (clk,
wb_rst_i, data_in, data_out,
// Control signals
push, // push strobe, active high
pop, // pop strobe, active high
// status signals
overrun,
count,
error_bit,
fifo_reset,
reset_status
);
// FIFO parameters
parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
input clk;
input wb_rst_i;
input push;
input pop;
input [fifo_width-1:0] data_in;
input fifo_reset;
input reset_status;
output [fifo_width-1:0] data_out;
output overrun;
output [fifo_counter_w-1:0] count;
output error_bit;
wire [fifo_width-1:0] data_out;
wire [7:0] data8_out;
// flags FIFO
reg [2:0] fifo[fifo_depth-1:0];
// FIFO pointers
reg [fifo_pointer_w-1:0] top;
reg [fifo_pointer_w-1:0] bottom;
reg [fifo_counter_w-1:0] count;
reg overrun;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 4'h1;
raminfr #(fifo_pointer_w,8,fifo_depth) rfifo
(.clk(clk),
.we(push),
.a(top),
.dpra(bottom),
.di(data_in[fifo_width-1:fifo_width-8]),
.dpo(data8_out)
);
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
begin
top <= 0;
bottom <= 0;
count <= 0;
fifo[0] <= 0;
fifo[1] <= 0;
fifo[2] <= 0;
fifo[3] <= 0;
fifo[4] <= 0;
fifo[5] <= 0;
fifo[6] <= 0;
fifo[7] <= 0;
fifo[8] <= 0;
fifo[9] <= 0;
fifo[10] <= 0;
fifo[11] <= 0;
fifo[12] <= 0;
fifo[13] <= 0;
fifo[14] <= 0;
fifo[15] <= 0;
end
else
if (fifo_reset) begin
top <= 0;
bottom <= 0;
count <= 0;
fifo[0] <= 0;
fifo[1] <= 0;
fifo[2] <= 0;
fifo[3] <= 0;
fifo[4] <= 0;
fifo[5] <= 0;
fifo[6] <= 0;
fifo[7] <= 0;
fifo[8] <= 0;
fifo[9] <= 0;
fifo[10] <= 0;
fifo[11] <= 0;
fifo[12] <= 0;
fifo[13] <= 0;
fifo[14] <= 0;
fifo[15] <= 0;
end
else
begin
case ({push, pop})
2'b10 : if (count<fifo_depth) // overrun condition
begin
top <= top_plus_1;
fifo[top] <= data_in[2:0];
count <= count + 5'd1;
end
2'b01 : if(count>0)
begin
fifo[bottom] <= 0;
bottom <= bottom + 4'd1;
count <= count - 5'd1;
end
2'b11 : begin
bottom <= bottom + 4'd1;
top <= top_plus_1;
fifo[top] <= data_in[2:0];
end
default: ;
endcase
end
end // always
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
overrun <= 1'b0;
else
if(fifo_reset | reset_status)
overrun <= 1'b0;
else
if(push & ~pop & (count==fifo_depth))
overrun <= 1'b1;
end // always
// please note though that data_out is only valid one clock after pop signal
assign data_out = {data8_out,fifo[bottom]};
// Additional logic for detection of error conditions (parity and framing) inside the FIFO
// for the Line Status Register bit 7
wire [2:0] word0 = fifo[0];
wire [2:0] word1 = fifo[1];
wire [2:0] word2 = fifo[2];
wire [2:0] word3 = fifo[3];
wire [2:0] word4 = fifo[4];
wire [2:0] word5 = fifo[5];
wire [2:0] word6 = fifo[6];
wire [2:0] word7 = fifo[7];
wire [2:0] word8 = fifo[8];
wire [2:0] word9 = fifo[9];
wire [2:0] word10 = fifo[10];
wire [2:0] word11 = fifo[11];
wire [2:0] word12 = fifo[12];
wire [2:0] word13 = fifo[13];
wire [2:0] word14 = fifo[14];
wire [2:0] word15 = fifo[15];
// a 1 is returned if any of the error bits in the fifo is 1
assign error_bit = |(word0[2:0] | word1[2:0] | word2[2:0] | word3[2:0] |
word4[2:0] | word5[2:0] | word6[2:0] | word7[2:0] |
word8[2:0] | word9[2:0] | word10[2:0] | word11[2:0] |
word12[2:0] | word13[2:0] | word14[2:0] | word15[2:0] );
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_sync_flops.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core receiver logic ////
//// ////
//// Known problems (limits): ////
//// None known ////
//// ////
//// To Do: ////
//// Thourough testing. ////
//// ////
//// Author(s): ////
//// - Andrej Erzen ([email protected]) ////
//// - Tadej Markovic ([email protected]) ////
//// ////
//// Created: 2004/05/20 ////
//// Last Updated: 2004/05/20 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
module uart_sync_flops
(
// internal signals
rst_i,
clk_i,
stage1_rst_i,
stage1_clk_en_i,
async_dat_i,
sync_dat_o
);
parameter width = 1;
parameter init_value = 1'b0;
input rst_i; // reset input
input clk_i; // clock input
input stage1_rst_i; // synchronous reset for stage 1 FF
input stage1_clk_en_i; // synchronous clock enable for stage 1 FF
input [width-1:0] async_dat_i; // asynchronous data input
output [width-1:0] sync_dat_o; // synchronous data output
//
// Interal signal declarations
//
reg [width-1:0] sync_dat_o;
reg [width-1:0] flop_0;
// first stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
flop_0 <= {width{init_value}};
else
flop_0 <= async_dat_i;
end
// second stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
sync_dat_o <= {width{init_value}};
else if (stage1_rst_i)
sync_dat_o <= {width{init_value}};
else if (stage1_clk_en_i)
sync_dat_o <= flop_0;
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_tfifo.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core transmitter FIFO ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2002/07/22 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.16 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.15 2001/12/18 09:01:07 mohor
// Bug that was entered in the last update fixed (rx state machine).
//
// Revision 1.14 2001/12/17 14:46:48 mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.13 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.12 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.11 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.10 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.9 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8 2001/08/24 08:48:10 mohor
// FIFO was not cleared after the data was read bug fixed.
//
// Revision 1.7 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.3 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/27 17:37:48 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:12+02 jacob
// Initial revision
//
//
`include "uart_defines.v"
module uart_tfifo (clk,
wb_rst_i, data_in, data_out,
// Control signals
push, // push strobe, active high
pop, // pop strobe, active high
// status signals
overrun,
count,
fifo_reset,
reset_status
);
// FIFO parameters
parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
input clk;
input wb_rst_i;
input push;
input pop;
input [fifo_width-1:0] data_in;
input fifo_reset;
input reset_status;
output [fifo_width-1:0] data_out;
output overrun;
output [fifo_counter_w-1:0] count;
wire [fifo_width-1:0] data_out;
// FIFO pointers
reg [fifo_pointer_w-1:0] top;
reg [fifo_pointer_w-1:0] bottom;
reg [fifo_counter_w-1:0] count;
reg overrun;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 4'd1;
raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo
(.clk(clk),
.we(push),
.a(top),
.dpra(bottom),
.di(data_in),
.dpo(data_out)
);
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
begin
top <= 0;
bottom <= 0;
count <= 0;
end
else
if (fifo_reset) begin
top <= 0;
bottom <= 0;
count <= 0;
end
else
begin
case ({push, pop})
2'b10 : if (count<fifo_depth) // overrun condition
begin
top <= top_plus_1;
count <= count + 5'd1;
end
2'b01 : if(count>0)
begin
bottom <= bottom + 4'd1;
count <= count - 5'd1;
end
2'b11 : begin
bottom <= bottom + 4'd1;
top <= top_plus_1;
end
default: ;
endcase
end
end // always
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
overrun <= 1'b0;
else
if(fifo_reset | reset_status)
overrun <= 1'b0;
else
if(push & (count==fifo_depth))
overrun <= 1'b1;
end // always
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_top.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core top level. ////
//// ////
//// Known problems (limits): ////
//// Note that transmitter and receiver instances are inside ////
//// the uart_regs.v file. ////
//// ////
//// To Do: ////
//// Nothing so far. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.18 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.17 2001/12/19 08:40:03 mohor
// Warnings fixed (unused signals removed).
//
// Revision 1.16 2001/12/06 14:51:04 gorban
// Bug in LSR[0] is fixed.
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
//
// Revision 1.15 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.14 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.13 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.12 2001/08/25 15:46:19 gorban
// Modified port names again
//
// Revision 1.11 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.10 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.4 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/21 19:12:02 gorban
// Corrected some Linter messages.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:12+02 jacob
// Initial revision
//
//
`include "uart_defines.v"
module uart_top (
wb_clk_i,
// Wishbone signals
wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_err_o, wb_ack_o, wb_sel_i,
int_o, // interrupt request
// UART signals
// serial input/output
stx_pad_o, srx_pad_i,
// modem signals
rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i
`ifdef UART_HAS_BAUDRATE_OUTPUT
, baud_o
`endif
);
parameter SIM = 0;
parameter debug = 0;
input wb_clk_i;
// WISHBONE interface
input wb_rst_i;
input [2:0] wb_adr_i;
input [7:0] wb_dat_i;
output [7:0] wb_dat_o;
input wb_we_i;
input wb_stb_i;
input wb_cyc_i;
input [3:0] wb_sel_i;
output wb_err_o;
output wb_ack_o;
output int_o;
// UART signals
input srx_pad_i;
output stx_pad_o;
output rts_pad_o;
input cts_pad_i;
output dtr_pad_o;
input dsr_pad_i;
input ri_pad_i;
input dcd_pad_i;
// optional baudrate output
`ifdef UART_HAS_BAUDRATE_OUTPUT
output baud_o;
`endif
wire stx_pad_o;
wire rts_pad_o;
wire dtr_pad_o;
wire [2:0] wb_adr_i;
wire [7:0] wb_dat_i;
wire [7:0] wb_dat_o;
wire [7:0] wb_dat8_i; // 8-bit internal data input
wire [7:0] wb_dat8_o; // 8-bit internal data output
wire [3:0] wb_sel_i; // WISHBONE select signal
wire [2:0] wb_adr_int;
wire we_o; // Write enable for registers
wire re_o; // Read enable for registers
//
// MODULE INSTANCES
//
assign wb_err_o = 1'b0;
//// WISHBONE interface module
uart_wb uart_wb_inst (
.clk( wb_clk_i ),
.wb_rst_i( wb_rst_i ),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_dat8_i(wb_dat8_i),
.wb_dat8_o(wb_dat8_o),
.wb_dat32_o(32'b0),
.wb_sel_i(4'b0),
.wb_we_i( wb_we_i ),
.wb_stb_i( wb_stb_i ),
.wb_cyc_i( wb_cyc_i ),
.wb_ack_o( wb_ack_o ),
.wb_adr_i(wb_adr_i),
.wb_adr_int(wb_adr_int),
.we_o( we_o ),
.re_o(re_o)
);
// Registers
uart_regs #(.SIM (SIM)) uart_regs_inst (
.clk( wb_clk_i ),
.wb_rst_i( wb_rst_i ),
.wb_addr_i( wb_adr_int ),
.wb_dat_i( wb_dat8_i ),
.wb_dat_o( wb_dat8_o ),
.wb_we_i( we_o ),
.wb_re_i(re_o),
.modem_inputs( {cts_pad_i, dsr_pad_i,
ri_pad_i, dcd_pad_i} ),
.stx_pad_o( stx_pad_o ),
.srx_pad_i( srx_pad_i ),
.rts_pad_o( rts_pad_o ),
.dtr_pad_o( dtr_pad_o ),
.int_o( int_o )
`ifdef UART_HAS_BAUDRATE_OUTPUT
, .baud_o(baud_o)
`endif
);
initial
begin
if(debug) begin
`ifdef UART_HAS_BAUDRATE_OUTPUT
$display("(%m) UART INFO: Has baudrate output\n");
`else
$display("(%m) UART INFO: Doesn't have baudrate output\n");
`endif
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_transmitter.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core transmitter logic ////
//// ////
//// Known problems (limits): ////
//// None known ////
//// ////
//// To Do: ////
//// Thourough testing. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.18 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.16 2002/01/08 11:29:40 mohor
// tf_pop was too wide. Now it is only 1 clk cycle width.
//
// Revision 1.15 2001/12/17 14:46:48 mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.14 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.13 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.12 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.11 2001/10/29 17:00:46 gorban
// fixed parity sending and tx_fifo resets over- and underrun
//
// Revision 1.10 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.9 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.6 2001/06/23 11:21:48 gorban
// DL made 16-bit long. Fixed transmission/reception bugs.
//
// Revision 1.5 2001/06/02 14:28:14 gorban
// Fixed receiver and transmitter. Major bug fixed.
//
// Revision 1.4 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/27 17:37:49 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2 2001/05/21 19:12:02 gorban
// Corrected some Linter messages.
//
// Revision 1.1 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:12+02 jacob
// Initial revision
//
//
`include "uart_defines.v"
module uart_transmitter
#(parameter SIM = 0)
(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask);
input clk;
input wb_rst_i;
input [7:0] lcr;
input tf_push;
input [7:0] wb_dat_i;
input enable;
input tx_reset;
input lsr_mask; //reset of fifo
output stx_pad_o;
output [2:0] tstate;
output [`UART_FIFO_COUNTER_W-1:0] tf_count;
reg [2:0] tstate;
reg [4:0] counter;
reg [2:0] bit_counter; // counts the bits to be sent
reg [6:0] shift_out; // output shift register
reg stx_o_tmp;
reg parity_xor; // parity of the word
reg tf_pop;
reg bit_out;
// TX FIFO instance
//
// Transmitter FIFO signals
wire [`UART_FIFO_WIDTH-1:0] tf_data_in;
wire [`UART_FIFO_WIDTH-1:0] tf_data_out;
wire tf_push;
wire tf_overrun;
wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
assign tf_data_in = wb_dat_i;
uart_tfifo fifo_tx( // error bit signal is not used in transmitter FIFO
.clk( clk ),
.wb_rst_i( wb_rst_i ),
.data_in( tf_data_in ),
.data_out( tf_data_out ),
.push( tf_push ),
.pop( tf_pop ),
.overrun( tf_overrun ),
.count( tf_count ),
.fifo_reset( tx_reset ),
.reset_status(lsr_mask)
);
// TRANSMITTER FINAL STATE MACHINE
localparam s_idle = 3'd0;
localparam s_send_start = 3'd1;
localparam s_send_byte = 3'd2;
localparam s_send_parity = 3'd3;
localparam s_send_stop = 3'd4;
localparam s_pop_byte = 3'd5;
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
begin
tstate <= s_idle;
stx_o_tmp <= 1'b1;
counter <= 5'b0;
shift_out <= 7'b0;
bit_out <= 1'b0;
parity_xor <= 1'b0;
tf_pop <= 1'b0;
bit_counter <= 3'b0;
end
else
if (enable | SIM)
begin
case (tstate)
s_idle : if (~|tf_count) // if tf_count==0
begin
tstate <= s_idle;
stx_o_tmp <= 1'b1;
end
else
begin
tf_pop <= 1'b0;
stx_o_tmp <= 1'b1;
tstate <= s_pop_byte;
end
s_pop_byte : begin
tf_pop <= 1'b1;
case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word
2'b00 : begin
bit_counter <= 3'b100;
parity_xor <= ^tf_data_out[4:0];
end
2'b01 : begin
bit_counter <= 3'b101;
parity_xor <= ^tf_data_out[5:0];
end
2'b10 : begin
bit_counter <= 3'b110;
parity_xor <= ^tf_data_out[6:0];
end
2'b11 : begin
bit_counter <= 3'b111;
parity_xor <= ^tf_data_out[7:0];
end
endcase
{shift_out[6:0], bit_out} <= tf_data_out;
tstate <= s_send_start;
end
s_send_start : begin
tf_pop <= 1'b0;
if (~|counter)
counter <= 5'b01111;
else
if (counter == 5'b00001)
begin
counter <= 0;
tstate <= s_send_byte;
end
else
counter <= counter - 5'd1;
stx_o_tmp <= 1'b0;
if (SIM) begin
tstate <= s_idle;
$write("%c", tf_data_out);
$fflush(32'h80000001);
end
end
s_send_byte : begin
if (~|counter)
counter <= 5'b01111;
else
if (counter == 5'b00001)
begin
if (bit_counter > 3'b0)
begin
bit_counter <= bit_counter - 3'd1;
{shift_out[5:0],bit_out } <= {shift_out[6:1], shift_out[0]};
tstate <= s_send_byte;
end
else // end of byte
if (~lcr[`UART_LC_PE])
begin
tstate <= s_send_stop;
end
else
begin
case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
2'b00: bit_out <= ~parity_xor;
2'b01: bit_out <= 1'b1;
2'b10: bit_out <= parity_xor;
2'b11: bit_out <= 1'b0;
endcase
tstate <= s_send_parity;
end
counter <= 0;
end
else
counter <= counter - 5'd1;
stx_o_tmp <= bit_out; // set output pin
end
s_send_parity : begin
if (~|counter)
counter <= 5'b01111;
else
if (counter == 5'b00001)
begin
counter <= 5'd0;
tstate <= s_send_stop;
end
else
counter <= counter - 5'd1;
stx_o_tmp <= bit_out;
end
s_send_stop : begin
if (~|counter)
begin
casez ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
3'b0??: counter <= 5'b01101; // 1 stop bit ok igor
3'b100: counter <= 5'b10101; // 1.5 stop bit
default: counter <= 5'b11101; // 2 stop bits
endcase
end
else
if (counter == 5'b00001)
begin
counter <= 0;
tstate <= s_idle;
end
else
counter <= counter - 5'd1;
stx_o_tmp <= 1'b1;
end
default : // should never get here
tstate <= s_idle;
endcase
end // end if enable
else
tf_pop <= 1'b0; // tf_pop must be 1 cycle width
end // transmitter logic
assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp; // Break condition
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_wb.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core WISHBONE interface. ////
//// ////
//// Known problems (limits): ////
//// Inserts one wait state on all transfers. ////
//// Note affected signals and the way they are affected. ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.16 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.15 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.12 2001/12/19 08:03:34 mohor
// Warnings cleared.
//
// Revision 1.11 2001/12/06 14:51:04 gorban
// Bug in LSR[0] is fixed.
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
//
// Revision 1.10 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.9 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.8 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.7 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.4 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/21 19:12:01 gorban
// Corrected some Linter messages.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:13+02 jacob
// Initial revision
//
//
// UART core WISHBONE interface
//
// Author: Jacob Gorban ([email protected])
// Company: Flextronics Semiconductor
//
`include "uart_defines.v"
module uart_wb (clk, wb_rst_i,
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i,
wb_adr_int, wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i,
we_o, re_o // Write and read enable output for the core
);
input clk;
// WISHBONE interface
input wb_rst_i;
input wb_we_i;
input wb_stb_i;
input wb_cyc_i;
input [3:0] wb_sel_i;
input [2:0] wb_adr_i; //WISHBONE address line
input [7:0] wb_dat_i; //input WISHBONE bus
output [7:0] wb_dat_o;
reg [7:0] wb_dat_o;
wire [7:0] wb_dat_i;
reg [7:0] wb_dat_is;
output [2:0] wb_adr_int; // internal signal for address bus
input [7:0] wb_dat8_o; // internal 8 bit output to be put into wb_dat_o
output [7:0] wb_dat8_i;
input [31:0] wb_dat32_o; // 32 bit data output (for debug interface)
output wb_ack_o;
output we_o;
output re_o;
wire we_o;
reg wb_ack_o;
reg [7:0] wb_dat8_i;
wire [7:0] wb_dat8_o;
wire [2:0] wb_adr_int; // internal signal for address bus
reg [2:0] wb_adr_is;
reg wb_we_is;
reg wb_cyc_is;
reg wb_stb_is;
wire [3:0] wb_sel_i;
reg wre ;// timing control signal for write or read enable
// wb_ack_o FSM
reg [1:0] wbstate;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) begin
wb_ack_o <= 1'b0;
wbstate <= 0;
wre <= 1'b1;
end else
case (wbstate)
0: begin
if (wb_stb_is & wb_cyc_is) begin
wre <= 0;
wbstate <= 1;
wb_ack_o <= 1;
end else begin
wre <= 1;
wb_ack_o <= 0;
end
end
1: begin
wb_ack_o <= 0;
wbstate <= 2;
wre <= 0;
end
2: begin
wb_ack_o <= 0;
wbstate <= 3;
wre <= 0;
end
3: begin
wb_ack_o <= 0;
wbstate <= 0;
wre <= 1;
end
endcase
assign we_o = wb_we_is & wb_stb_is & wb_cyc_is & wre ; //WE for registers
assign re_o = ~wb_we_is & wb_stb_is & wb_cyc_is & wre ; //RE for registers
// Sample input signals
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) begin
wb_adr_is <= 0;
wb_we_is <= 0;
wb_cyc_is <= 0;
wb_stb_is <= 0;
wb_dat_is <= 0;
end else begin
wb_adr_is <= wb_adr_i;
wb_we_is <= wb_we_i;
wb_cyc_is <= wb_cyc_i;
wb_stb_is <= wb_stb_i;
wb_dat_is <= wb_dat_i;
end
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
wb_dat_o <= 0;
else
wb_dat_o <= wb_dat8_o;
always @(wb_dat_is)
wb_dat8_i = wb_dat_is;
assign wb_adr_int = wb_adr_is;
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is a generic wishbone bus (B3). The number of masters and
* slaves are configurable. Ten slaves can be connected with a
* configurable memory map.
*
* Instantiation example:
* wb_bus_b3
* #(.DATA_WIDTH(32), .ADDR_WIDTH(32),
* .MASTERS(4), .SLAVES(2),
* .S0_RANGE_WIDTH(1), .S0_RANGE_MATCH(1'b0),
* .S1_RANGE_WIDTH(4), .S1_RANGE_MATCH(4'he))
* bus(.clk_i(clk), rst_i(rst),
* .m_adr_i({m_adr_i[3],..,m_adr_i[0]},
* ...
* );
*
* DATA_WIDTH and ADDR_WIDTH are defined in bits. DATA_WIDTH must be
* full bytes (i.e., multiple of 8)!
*
* The ports are flattened. That means, that all masters share the bus
* signal ports. With four masters and a data width of 32 bit the
* m_cyc_i port is 4 bit wide and the m_dat_i is 128 (=4*32) bit wide.
* The signals are arranged from right to left, meaning the m_dat_i is
* defined as [DATA_WIDTH*MASTERS-1:0] and each port m is assigned to
* [(m+1)*DATA_WIDTH-1:m*DATA_WIDTH].
*
* The memory map is defined with the S?_RANGE_WIDTH and
* S?_RANGE_MATCH parameters. The WIDTH sets the number of most
* significant bits (i.e., those from the left) that are relevant to
* define the memory range. The MATCH accordingly sets the value of
* those bits of the address that define the memory range.
*
* Example (32 bit addresses):
* Slave 0: 0x00000000-0x7fffffff
* Slave 1: 0x80000000-0xbfffffff
* Slave 2: 0xe0000000-0xe0ffffff
*
* Slave 0 is defined by the uppermost bit, which is 0 for this
* address range. Slave 1 is defined by the uppermost two bit, that
* are 10 for the memory range. Slave 2 is defined by 8 bit which are
* e0 for the memory range.
*
* This results in:
* S0_RANGE_WIDTH(1), S0_RANGE_MATCH(1'b0)
* S1_RANGE_WIDTH(2), S1_RANGE_MATCH(2'b10)
* S2_RANGE_WIDTH(8), S2_RANGE_MATCH(8'he0)
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module wb_bus_b3
#(
/* User parameters */
// Set the number of masters and slaves
parameter MASTERS = 2,
parameter SLAVES = 1,
// Set bus address and data width in bits
// DATA_WIDTH must be a multiple of 8 (full bytes)!
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32,
// Memory range definitions, see above
// The number of parameters actually limits the number of slaves as
// there is no generic way that is handled by all tools to define
// variable width parameter arrays.
parameter S0_ENABLE = 1,
parameter S0_RANGE_WIDTH = 1,
parameter S0_RANGE_MATCH = 1'b0,
parameter S1_ENABLE = 1,
parameter S1_RANGE_WIDTH = 1,
parameter S1_RANGE_MATCH = 1'b0,
parameter S2_ENABLE = 1,
parameter S2_RANGE_WIDTH = 1,
parameter S2_RANGE_MATCH = 1'b0,
parameter S3_ENABLE = 1,
parameter S3_RANGE_WIDTH = 1,
parameter S3_RANGE_MATCH = 1'b0,
parameter S4_ENABLE = 1,
parameter S4_RANGE_WIDTH = 1,
parameter S4_RANGE_MATCH = 1'b0,
parameter S5_ENABLE = 1,
parameter S5_RANGE_WIDTH = 1,
parameter S5_RANGE_MATCH = 1'b0,
parameter S6_ENABLE = 1,
parameter S6_RANGE_WIDTH = 1,
parameter S6_RANGE_MATCH = 1'b0,
parameter S7_ENABLE = 1,
parameter S7_RANGE_WIDTH = 1,
parameter S7_RANGE_MATCH = 1'b0,
parameter S8_ENABLE = 1,
parameter S8_RANGE_WIDTH = 1,
parameter S8_RANGE_MATCH = 1'b0,
parameter S9_ENABLE = 1,
parameter S9_RANGE_WIDTH = 1,
parameter S9_RANGE_MATCH = 1'b0,
/* Derived local parameters */
// Width of byte select registers
localparam SEL_WIDTH = DATA_WIDTH >> 3
)
(
/* Ports */
input clk_i,
input rst_i,
input [ADDR_WIDTH*MASTERS-1:0] m_adr_i,
input [DATA_WIDTH*MASTERS-1:0] m_dat_i,
input [MASTERS-1:0] m_cyc_i,
input [MASTERS-1:0] m_stb_i,
input [SEL_WIDTH*MASTERS-1:0] m_sel_i,
input [MASTERS-1:0] m_we_i,
input [MASTERS*3-1:0] m_cti_i,
input [MASTERS*2-1:0] m_bte_i,
output [DATA_WIDTH*MASTERS-1:0] m_dat_o,
output [MASTERS-1:0] m_ack_o,
output [MASTERS-1:0] m_err_o,
output [MASTERS-1:0] m_rty_o,
output [ADDR_WIDTH*SLAVES-1:0] s_adr_o,
output [DATA_WIDTH*SLAVES-1:0] s_dat_o,
output [SLAVES-1:0] s_cyc_o,
output [SLAVES-1:0] s_stb_o,
output [SEL_WIDTH*SLAVES-1:0] s_sel_o,
output [SLAVES-1:0] s_we_o,
output [SLAVES*3-1:0] s_cti_o,
output [SLAVES*2-1:0] s_bte_o,
input [DATA_WIDTH*SLAVES-1:0] s_dat_i,
input [SLAVES-1:0] s_ack_i,
input [SLAVES-1:0] s_err_i,
input [SLAVES-1:0] s_rty_i,
// The snoop port forwards all write accesses on their success for
// one cycle.
output [DATA_WIDTH-1:0] snoop_adr_o,
output snoop_en_o,
input bus_hold,
output bus_hold_ack
);
wire [ADDR_WIDTH-1:0] bus_adr;
wire [DATA_WIDTH-1:0] bus_wdat;
wire bus_cyc;
wire bus_stb;
wire [SEL_WIDTH-1:0] bus_sel;
wire bus_we;
wire [2:0] bus_cti;
wire [1:0] bus_bte;
wire [DATA_WIDTH-1:0] bus_rdat;
wire bus_ack;
wire bus_err;
wire bus_rty;
/* wb_mux AUTO_TEMPLATE(
.s_dat_o (bus_wdat),
.s_dat_i (bus_rdat),
.s_\(.*\)_o (bus_\1),
.s_\(.*\)_i (bus_\1),
); */
wb_mux
#(.MASTERS(MASTERS), .ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH))
u_mux(/*AUTOINST*/
// Outputs
.m_dat_o (m_dat_o[DATA_WIDTH*MASTERS-1:0]),
.m_ack_o (m_ack_o[MASTERS-1:0]),
.m_err_o (m_err_o[MASTERS-1:0]),
.m_rty_o (m_rty_o[MASTERS-1:0]),
.s_adr_o (bus_adr), // Templated
.s_dat_o (bus_wdat), // Templated
.s_cyc_o (bus_cyc), // Templated
.s_stb_o (bus_stb), // Templated
.s_sel_o (bus_sel), // Templated
.s_we_o (bus_we), // Templated
.s_cti_o (bus_cti), // Templated
.s_bte_o (bus_bte), // Templated
.bus_hold_ack (bus_hold_ack),
// Inputs
.clk_i (clk_i),
.rst_i (rst_i),
.m_adr_i (m_adr_i[ADDR_WIDTH*MASTERS-1:0]),
.m_dat_i (m_dat_i[DATA_WIDTH*MASTERS-1:0]),
.m_cyc_i (m_cyc_i[MASTERS-1:0]),
.m_stb_i (m_stb_i[MASTERS-1:0]),
.m_sel_i (m_sel_i[SEL_WIDTH*MASTERS-1:0]),
.m_we_i (m_we_i[MASTERS-1:0]),
.m_cti_i (m_cti_i[MASTERS*3-1:0]),
.m_bte_i (m_bte_i[MASTERS*2-1:0]),
.s_dat_i (bus_rdat), // Templated
.s_ack_i (bus_ack), // Templated
.s_err_i (bus_err), // Templated
.s_rty_i (bus_rty), // Templated
.bus_hold (bus_hold));
/* wb_decode AUTO_TEMPLATE(
.m_dat_o (bus_rdat),
.m_dat_i (bus_wdat),
.m_\(.*\)_i (bus_\1),
.m_\(.*\)_o (bus_\1),
); */
wb_decode
#(.SLAVES(SLAVES), .ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH),
.S0_ENABLE(S0_ENABLE),
.S0_RANGE_WIDTH(S0_RANGE_WIDTH), .S0_RANGE_MATCH(S0_RANGE_MATCH),
.S1_ENABLE(S1_ENABLE),
.S1_RANGE_WIDTH(S1_RANGE_WIDTH), .S1_RANGE_MATCH(S1_RANGE_MATCH),
.S2_ENABLE(S2_ENABLE),
.S2_RANGE_WIDTH(S2_RANGE_WIDTH), .S2_RANGE_MATCH(S2_RANGE_MATCH),
.S3_ENABLE(S3_ENABLE),
.S3_RANGE_WIDTH(S3_RANGE_WIDTH), .S3_RANGE_MATCH(S3_RANGE_MATCH),
.S4_ENABLE(S4_ENABLE),
.S4_RANGE_WIDTH(S4_RANGE_WIDTH), .S4_RANGE_MATCH(S4_RANGE_MATCH),
.S5_ENABLE(S5_ENABLE),
.S5_RANGE_WIDTH(S5_RANGE_WIDTH), .S5_RANGE_MATCH(S5_RANGE_MATCH),
.S6_ENABLE(S6_ENABLE),
.S6_RANGE_WIDTH(S6_RANGE_WIDTH), .S6_RANGE_MATCH(S6_RANGE_MATCH),
.S7_ENABLE(S7_ENABLE),
.S7_RANGE_WIDTH(S7_RANGE_WIDTH), .S7_RANGE_MATCH(S7_RANGE_MATCH),
.S8_ENABLE(S8_ENABLE),
.S8_RANGE_WIDTH(S8_RANGE_WIDTH), .S8_RANGE_MATCH(S8_RANGE_MATCH),
.S9_ENABLE(S9_ENABLE),
.S9_RANGE_WIDTH(S9_RANGE_WIDTH), .S9_RANGE_MATCH(S9_RANGE_MATCH))
u_decode(/*AUTOINST*/
// Outputs
.m_dat_o (bus_rdat), // Templated
.m_ack_o (bus_ack), // Templated
.m_err_o (bus_err), // Templated
.m_rty_o (bus_rty), // Templated
.s_adr_o (s_adr_o[ADDR_WIDTH*SLAVES-1:0]),
.s_dat_o (s_dat_o[DATA_WIDTH*SLAVES-1:0]),
.s_cyc_o (s_cyc_o[SLAVES-1:0]),
.s_stb_o (s_stb_o[SLAVES-1:0]),
.s_sel_o (s_sel_o[SEL_WIDTH*SLAVES-1:0]),
.s_we_o (s_we_o[SLAVES-1:0]),
.s_cti_o (s_cti_o[SLAVES*3-1:0]),
.s_bte_o (s_bte_o[SLAVES*2-1:0]),
// Inputs
.clk_i (clk_i),
.rst_i (rst_i),
.m_adr_i (bus_adr), // Templated
.m_dat_i (bus_wdat), // Templated
.m_cyc_i (bus_cyc), // Templated
.m_stb_i (bus_stb), // Templated
.m_sel_i (bus_sel), // Templated
.m_we_i (bus_we), // Templated
.m_cti_i (bus_cti), // Templated
.m_bte_i (bus_bte), // Templated
.s_dat_i (s_dat_i[DATA_WIDTH*SLAVES-1:0]),
.s_ack_i (s_ack_i[SLAVES-1:0]),
.s_err_i (s_err_i[SLAVES-1:0]),
.s_rty_i (s_rty_i[SLAVES-1:0]));
// Snoop address comes direct from master bus
assign snoop_adr_o = bus_adr;
// Snoop on acknowledge and write. Mask with strobe to be sure
// there actually is a something happing and no dangling signals
// and always ack'ing slaves.
assign snoop_en_o = bus_ack & bus_stb & bus_we;
endmodule // wb_bus_b3
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is a generic slave selector for the Wishbone bus (B3). The
* number of slaves is configurable and up to ten slaves can be
* connected with a configurable memory map.
*
* Instantiation example:
* wb_sselect
* #(.DATA_WIDTH(32), .ADDR_WIDTH(32),
* .SLAVES(2),
* .S0_ENABLE (1), .S0_RANGE_WIDTH(1), .S0_RANGE_MATCH(1'b0),
* .S1_ENABLE (1), .S1_RANGE_WIDTH(4), .S1_RANGE_MATCH(4'he))
* sselect(.clk_i(clk), rst_i(rst),
* .s_adr_o({m_adr_o[3],..,m_adr_o[0]},
* ...
* );
*
* DATA_WIDTH and ADDR_WIDTH are defined in bits. DATA_WIDTH must be
* full bytes (i.e., multiple of 8)!
*
* The ports are flattened. That means, that all slaves share the bus
* signal ports. With four slaves and a data width of 32 bit the
* s_cyc_o port is 4 bit wide and the s_dat_o is 128 (=4*32) bit wide.
* The signals are arranged from right to left, meaning the s_dat_o is
* defined as [DATA_WIDTH*SLAVES-1:0] and each port s is assigned to
* [(s+1)*DATA_WIDTH-1:s*DATA_WIDTH].
*
* The memory map is defined with the S?_RANGE_WIDTH and
* S?_RANGE_MATCH parameters. The WIDTH sets the number of most
* significant bits (i.e., those from the left) that are relevant to
* define the memory range. The MATCH accordingly sets the value of
* those bits of the address that define the memory range.
*
* Example (32 bit addresses):
* Slave 0: 0x00000000-0x7fffffff
* Slave 1: 0x80000000-0xbfffffff
* Slave 2: 0xe0000000-0xe0ffffff
*
* Slave 0 is defined by the uppermost bit, which is 0 for this
* address range. Slave 1 is defined by the uppermost two bit, that
* are 10 for the memory range. Slave 2 is defined by 8 bit which are
* e0 for the memory range.
*
* This results in:
* S0_RANGE_WIDTH(1), S0_RANGE_MATCH(1'b0)
* S1_RANGE_WIDTH(2), S1_RANGE_MATCH(2'b10)
* S2_RANGE_WIDTH(8), S2_RANGE_MATCH(8'he0)
*
*
* Finally, the slaves can be individually masked to ease
* instantiation using the Sx_ENABLE parameter. By defaults all slaves
* are enabled (and selected as long as x < SLAVES).
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module wb_decode
#(
/* User parameters */
// Set the number of slaves
parameter SLAVES = 3,
// Set bus address and data width in bits
// DATA_WIDTH must be a multiple of 8 (full bytes)!
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32,
/* Derived local parameters */
// Width of byte select registers
localparam SEL_WIDTH = DATA_WIDTH >> 3,
// Memory range definitions, see above
// The number of parameters actually limits the number of slaves as
// there is no generic way that is handled by all tools to define
// variable width parameter arrays.
parameter S0_ENABLE = 0,
parameter S0_RANGE_WIDTH = 1,
parameter S0_RANGE_MATCH = 1'b0,
parameter S1_ENABLE = 0,
parameter S1_RANGE_WIDTH = 2,
parameter S1_RANGE_MATCH = 2'b10,
parameter S2_ENABLE = 0,
parameter S2_RANGE_WIDTH = 8,
parameter S2_RANGE_MATCH = 8'he0,
parameter S3_ENABLE = 0,
parameter S3_RANGE_WIDTH = 16,
parameter S3_RANGE_MATCH = 1'b0,
parameter S4_ENABLE = 0,
parameter S4_RANGE_WIDTH = 32,
parameter S4_RANGE_MATCH = 1'b0,
parameter S5_ENABLE = 0,
parameter S5_RANGE_WIDTH = 64,
parameter S5_RANGE_MATCH = 1'b0,
parameter S6_ENABLE = 0,
parameter S6_RANGE_WIDTH = 128,
parameter S6_RANGE_MATCH = 1'b0,
parameter S7_ENABLE = 0,
parameter S7_RANGE_WIDTH = 256,
parameter S7_RANGE_MATCH = 1'b0,
parameter S8_ENABLE = 0,
parameter S8_RANGE_WIDTH = 512,
parameter S8_RANGE_MATCH = 1'b0,
parameter S9_ENABLE = 0,
parameter S9_RANGE_WIDTH = 1024,
parameter S9_RANGE_MATCH = 1'b0
)
(
/* Ports */
input clk_i,
input rst_i,
input [ADDR_WIDTH-1:0] m_adr_i,
input [DATA_WIDTH-1:0] m_dat_i,
input m_cyc_i,
input m_stb_i,
input [SEL_WIDTH-1:0] m_sel_i,
input m_we_i,
input [2:0] m_cti_i,
input [1:0] m_bte_i,
output reg [DATA_WIDTH-1:0] m_dat_o,
output m_ack_o,
output m_err_o,
output m_rty_o,
output reg [ADDR_WIDTH*SLAVES-1:0] s_adr_o,
output reg [DATA_WIDTH*SLAVES-1:0] s_dat_o,
output reg [SLAVES-1:0] s_cyc_o,
output reg [SLAVES-1:0] s_stb_o,
output reg [SEL_WIDTH*SLAVES-1:0] s_sel_o,
output reg [SLAVES-1:0] s_we_o,
output reg [SLAVES*3-1:0] s_cti_o,
output reg [SLAVES*2-1:0] s_bte_o,
input [DATA_WIDTH*SLAVES-1:0] s_dat_i,
input [SLAVES-1:0] s_ack_i,
input [SLAVES-1:0] s_err_i,
input [SLAVES-1:0] s_rty_i
);
wire [SLAVES-1:0] s_select;
// Generate the slave select signals based on the master bus
// address and the memory range parameters
generate
if (SLAVES > 0)
assign s_select[0] = S0_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S0_RANGE_WIDTH] == S0_RANGE_MATCH[S0_RANGE_WIDTH-1:0]);
if (SLAVES > 1)
assign s_select[1] = S1_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S1_RANGE_WIDTH] == S1_RANGE_MATCH[S1_RANGE_WIDTH-1:0]);
if (SLAVES > 2)
assign s_select[2] = S2_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S2_RANGE_WIDTH] == S2_RANGE_MATCH[S2_RANGE_WIDTH-1:0]);
if (SLAVES > 3)
assign s_select[3] = S3_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S3_RANGE_WIDTH] == S3_RANGE_MATCH[S3_RANGE_WIDTH-1:0]);
if (SLAVES > 4)
assign s_select[4] = S4_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S4_RANGE_WIDTH] == S4_RANGE_MATCH[S4_RANGE_WIDTH-1:0]);
if (SLAVES > 5)
assign s_select[5] = S5_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S5_RANGE_WIDTH] == S5_RANGE_MATCH[S5_RANGE_WIDTH-1:0]);
if (SLAVES > 6)
assign s_select[6] = S6_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S6_RANGE_WIDTH] == S6_RANGE_MATCH[S6_RANGE_WIDTH-1:0]);
if (SLAVES > 7)
assign s_select[7] = S7_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S7_RANGE_WIDTH] == S7_RANGE_MATCH[S7_RANGE_WIDTH-1:0]);
if (SLAVES > 8)
assign s_select[8] = S8_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S8_RANGE_WIDTH] == S8_RANGE_MATCH[S8_RANGE_WIDTH-1:0]);
if (SLAVES > 9)
assign s_select[9] = S9_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S9_RANGE_WIDTH] == S9_RANGE_MATCH[S9_RANGE_WIDTH-1:0]);
endgenerate
// If two s_select are high or none, we might have an bus error
wire bus_error;
assign bus_error = ~^s_select;
reg m_ack, m_err, m_rty;
// Mux the slave bus based on the slave select signal (one hot!)
always @(*) begin : bus_s_mux
integer i;
m_dat_o = {DATA_WIDTH{1'b0}};
m_ack = 1'bz;
m_err = 1'bz;
m_rty = 1'bz;
for (i = 0; i < SLAVES; i = i + 1) begin
s_adr_o[i*ADDR_WIDTH +: ADDR_WIDTH] = m_adr_i;
s_dat_o[i*DATA_WIDTH +: DATA_WIDTH] = m_dat_i;
s_sel_o[i*SEL_WIDTH +: SEL_WIDTH] = m_sel_i;
s_we_o[i] = m_we_i;
s_cti_o[i*3 +: 3] = m_cti_i;
s_bte_o[i*2 +: 2] = m_bte_i;
s_cyc_o[i] = m_cyc_i & s_select[i];
s_stb_o[i] = m_stb_i & s_select[i];
if (s_select[i]) begin
m_dat_o = s_dat_i[i*DATA_WIDTH +: DATA_WIDTH];
m_ack = s_ack_i[i];
m_err = s_err_i[i];
m_rty = s_rty_i[i];
end
end
end
assign m_ack_o = m_ack & !bus_error;
assign m_err_o = m_err | bus_error;
assign m_rty_o = m_rty & !bus_error;
endmodule // wb_sselect
|
/* Copyright (c) 2013 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is a round-robin arbiter for N participants, which is a
* parameter. The arbiter itself contains no register but is purely
* combinational which allows for various use cases. It simply
* calculates the next grant (nxt_gnt) based on the current grant
* (gnt) and the requests (req).
*
* That means, the gnt should in general be a register and especially
* there must be no combinational path from nxt_gnt to gnt!
*
* The normal usage is something like registering the gnt from
* nxt_gnt. Furthermore it is important that the gnt has an initial
* value which also must be one hot!
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
module wb_interconnect_arb_rr(/*AUTOARG*/
// Outputs
nxt_gnt,
// Inputs
req, gnt
);
/* User parameters */
// Number of participants
parameter N = 2;
/* Ports */
// Request
input [N-1:0] req;
// Current grant
input [N-1:0] gnt;
// Next grant
output [N-1:0] nxt_gnt;
// Sanity check
// synthesis translate_off
//always @(*)
// if (~^gnt)
// $fatal("signal <gnt> must always be one hot!");
// synthesis translate_on
// At a first glance, the computation of the nxt_gnt signal looks
// strange, but the principle is easy:
//
// * For each participant we compute a mask of width N. Based on
// the current gnt signal the mask contains a 1 at the position
// of other participants that will be served in round robin
// before the participant in case they request it.
//
// * The mask is 0 on all positions for the participant "left" of
// the currently granted participant as no other has precedence
// over this one. The mask has all one except the participant
// itself for the currently arbitrated participant.
//
// * From the mask and the request the nxt_gnt is calculated,
// roughly said as: if there is no other participant which has a
// higher precedence that also requests, the participant gets
// granted.
//
// Example 1:
// req = 1010
// gnt = 1000
// nxt_gnt = 0010
//
// mask[0] = 0000
// mask[1] = 0001
// mask[2] = 0011
// mask[3] = 0111
//
// Example 2:
// req = 1010
// gnt = 0100
// nxt_gnt = 1000
//
// mask[0] = 1000
// mask[1] = 1001
// mask[2] = 1011
// mask[3] = 0000
// Mask net
reg [N-1:0] mask [0:N-1];
// Calculate the mask
always @(*) begin : calc_mask
integer i,j;
for (i=0;i<N;i=i+1) begin
// Initialize mask as 0
mask[i] = {N{1'b0}};
// All participants to the "right" up to the current grant
// holder have precendence and therefore a 1 in the mask.
// First check if the next right from us has the grant.
// Afterwards the mask is calculated iteratively based on
// this.
if(i>0)
// For i=N:1 the next right is i-1
mask[i][i-1] = ~gnt[i-1];
else
// For i=0 the next right is N-1
mask[i][N-1] = ~gnt[N-1];
// Now the mask contains a 1 when the next right to us is not
// the grant holder. If it is the grant holder that means,
// that we are the next served (if necessary) as no other has
// higher precendence, which is then calculated in the
// following by filling up 1s up to the grant holder. To stop
// filling up there and not fill up any after this is
// iterative by always checking if the one before was not
// before the grant holder.
for (j=2;j<N;j=j+1) begin
if (i-j>=0)
mask[i][i-j] = mask[i][i-j+1] & ~gnt[i-j];
else if(i-j+1>=0)
mask[i][i-j+N] = mask[i][i-j+1] & ~gnt[i-j+N];
else
mask[i][i-j+N] = mask[i][i-j+N+1] & ~gnt[i-j+N];
end
end
end // always @ (*)
// Calculate the nxt_gnt
genvar k;
generate
for (k=0;k<N;k=k+1) begin : gen_nxt_gnt
// (mask[k] & req) masks all requests with higher precendence
// Example 1: 0: 0000 1: 0000 2: 0010 3: 0010
// Example 2: 0: 1000 1: 1000 2: 1010 3: 0000
//
// ~|(mask[k] & req) is there is none of them
// Example 1: 0: 1 1: 1 2: 0 3: 0
// Example 2: 1: 0 1: 0 2: 0 3: 1
//
// One might expect at this point that there was only one of
// them that matches, but this is guaranteed by the last part
// that is checking if this one has a request itself. In
// example 1, k=0 does not have a request, if it had, the
// result of the previous calculation would be 0 for k=1.
// Therefore: (~|(mask[k] & req) & req[k]) selects the next one.
// Example 1: 0: 0 1: 1 2: 0 3: 0
// Example 2: 0: 0 1: 0 2: 0 3: 1
//
// This is already the result. (0010 and 1000). Nevertheless,
// it is necessary to capture the case of no request at all
// (~|req). In that case, nxt_gnt would be 0, what iself
// leads to a problem in the next cycle (always grants).
// Therefore the current gnt is hold in case of no request by
// (~|req & gnt[k]).
assign nxt_gnt[k] = (~|(mask[k] & req) & req[k]) | (~|req & gnt[k]);
end
endgenerate
endmodule // wb_interconnect_arb_rr
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is a generic wishbone bus multiplexer (B3). The number of
* masters is configurable.
*
* DATA_WIDTH and ADDR_WIDTH are defined in bits. DATA_WIDTH must be
* full bytes (i.e., multiple of 8)!
*
* The ports are flattened. That means, that all masters share the bus
* signal ports. With four masters and a data width of 32 bit the
* m_cyc_i port is 4 bit wide and the m_dat_i is 128 (=4*32) bit wide.
* The signals are arranged from right to left, meaning the m_dat_i is
* defined as [DATA_WIDTH*MASTERS-1:0] and each port m is assigned to
* [(m+1)*DATA_WIDTH-1:m*DATA_WIDTH].
*
* Author(s):
* Stefan Wallentowitz <[email protected]>
*/
// TODO: * check bus hold signal correctness
module wb_mux
#(
/* User parameters */
// Set the number of slaves
parameter MASTERS = 1,
// Set bus address and data width in bits
// DATA_WIDTH must be a multiple of 8 (full bytes)!
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32,
/* Derived local parameters */
// Width of byte select registers
localparam SEL_WIDTH = DATA_WIDTH >> 3
)
(
/* Ports */
input clk_i,
input rst_i,
input [ADDR_WIDTH*MASTERS-1:0] m_adr_i,
input [DATA_WIDTH*MASTERS-1:0] m_dat_i,
input [MASTERS-1:0] m_cyc_i,
input [MASTERS-1:0] m_stb_i,
input [SEL_WIDTH*MASTERS-1:0] m_sel_i,
input [MASTERS-1:0] m_we_i,
input [MASTERS*3-1:0] m_cti_i,
input [MASTERS*2-1:0] m_bte_i,
output reg [DATA_WIDTH*MASTERS-1:0] m_dat_o,
output reg [MASTERS-1:0] m_ack_o,
output reg [MASTERS-1:0] m_err_o,
output reg [MASTERS-1:0] m_rty_o,
output reg [ADDR_WIDTH-1:0] s_adr_o,
output reg [DATA_WIDTH-1:0] s_dat_o,
output reg s_cyc_o,
output reg s_stb_o,
output reg [SEL_WIDTH-1:0] s_sel_o,
output reg s_we_o,
output reg [2:0] s_cti_o,
output reg [1:0] s_bte_o,
input [DATA_WIDTH-1:0] s_dat_i,
input s_ack_i,
input s_err_i,
input s_rty_i,
input bus_hold,
output reg bus_hold_ack
);
// The granted master is one hot encoded
wire [MASTERS-1:0] grant;
// The granted master from previous cycle (register)
reg [MASTERS-1:0] prev_grant;
// This is a net that masks the actual requests. The arbiter
// selects a different master each cycle. Therefore we need to
// actively control the return of the bus arbitration. That means
// as long as the granted master still holds is cycle signal, we
// mask out all other requests (be setting the requests to grant).
// When the cycle signal is released, we set the request to all
// masters cycle signals.
reg [MASTERS-1:0] m_req;
// This is the arbitration net from round robin
wire [MASTERS-1:0] arb_grant;
reg [MASTERS-1:0] prev_arb_grant;
// It is masked with the bus_hold_ack to hold back the arbitration
// as long as the bus is held
assign grant = arb_grant & {MASTERS{!bus_hold_ack}};
always @(*) begin
if (|(m_cyc_i & prev_grant)) begin
// The bus is not released this cycle
m_req = prev_grant;
bus_hold_ack = 1'b0;
end else begin
m_req = m_cyc_i;
bus_hold_ack = bus_hold;
end
end
// We register the grant signal. This is needed nevertheless for
// fair arbitration (round robin)
always @(posedge clk_i) begin
if (rst_i) begin
prev_arb_grant <= {{MASTERS-1{1'b0}},1'b1};
prev_grant <= {{MASTERS-1{1'b0}},1'b1};
end else begin
prev_arb_grant <= arb_grant;
prev_grant <= grant;
end
end
/* wb_interconnect_arb_rr AUTO_TEMPLATE(
.gnt (prev_arb_grant),
.nxt_gnt (arb_grant),
.req (m_req),
); */
wb_interconnect_arb_rr
#(.N(MASTERS))
u_arbiter(/*AUTOINST*/
// Outputs
.nxt_gnt (arb_grant), // Templated
// Inputs
.req (m_req), // Templated
.gnt (prev_arb_grant)); // Templated
// Mux the bus based on the grant signal which must be one hot!
always @(*) begin : bus_m_mux
integer i;
s_adr_o = {ADDR_WIDTH{1'bx}};
s_dat_o = {DATA_WIDTH{1'bx}};
s_sel_o = {SEL_WIDTH{1'bx}};
s_we_o = 1'bx;
s_cti_o = 3'bx;
s_bte_o = 2'bx;
s_cyc_o = 1'b0;
s_stb_o = 1'b0;
for (i = 0; i < MASTERS; i = i + 1) begin
m_dat_o[i*DATA_WIDTH +: DATA_WIDTH] = s_dat_i;
m_ack_o[i] = grant[i] & s_ack_i;
m_err_o[i] = grant[i] & s_err_i;
m_rty_o[i] = grant[i] & s_rty_i;
if (grant[i]) begin
s_adr_o = m_adr_i[(i+1)*ADDR_WIDTH-1 -: ADDR_WIDTH];
s_dat_o = m_dat_i[(i+1)*DATA_WIDTH-1 -: DATA_WIDTH];
s_sel_o = m_sel_i[(i+1)*SEL_WIDTH-1 -: SEL_WIDTH];
s_we_o = m_we_i[i];
s_cti_o = m_cti_i[(i+1)*3-1 -: 3];
s_bte_o = m_bte_i[(i+1)*2-1 -: 2];
s_cyc_o = m_cyc_i[i];
s_stb_o = m_stb_i[i];
end
end
end
endmodule // wb_sselect
|
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// assumes input does not change between start going high and out_valid
module aes_128(clk, start, state, key, out, out_valid);
input clk;
input start;
input [127:0] state, key;
output [127:0] out;
output out_valid;
reg [127:0] s0, k0;
wire [127:0] s1, s2, s3, s4, s5, s6, s7, s8, s9,
k1, k2, k3, k4, k5, k6, k7, k8, k9,
k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b, k8b, k9b;
reg start_r;
always @(posedge clk)
begin
start_r <= start;
end
wire start_posedge = start & ~start_r;
reg [4:0] validCounter;
always @ (posedge clk)
begin
if(start_posedge)
begin
s0 <= state ^ key;
k0 <= key;
validCounter <= 21;
end
else if(~out_valid)
begin
validCounter <= validCounter - 1;
end
end
assign out_valid = (validCounter == 0);
expand_key_128
a1 (clk, k0, k1, k0b, 8'h1),
a2 (clk, k1, k2, k1b, 8'h2),
a3 (clk, k2, k3, k2b, 8'h4),
a4 (clk, k3, k4, k3b, 8'h8),
a5 (clk, k4, k5, k4b, 8'h10),
a6 (clk, k5, k6, k5b, 8'h20),
a7 (clk, k6, k7, k6b, 8'h40),
a8 (clk, k7, k8, k7b, 8'h80),
a9 (clk, k8, k9, k8b, 8'h1b),
a10 (clk, k9, , k9b, 8'h36);
one_round
r1 (clk, s0, k0b, s1),
r2 (clk, s1, k1b, s2),
r3 (clk, s2, k2b, s3),
r4 (clk, s3, k3b, s4),
r5 (clk, s4, k4b, s5),
r6 (clk, s5, k5b, s6),
r7 (clk, s6, k6b, s7),
r8 (clk, s7, k7b, s8),
r9 (clk, s8, k8b, s9);
final_round
rf (clk, s9, k9b, out);
endmodule
module expand_key_128(clk, in, out_1, out_2, rcon);
input clk;
input [127:0] in;
input [7:0] rcon;
output reg [127:0] out_1;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3,
v0, v1, v2, v3;
reg [31:0] k0a, k1a, k2a, k3a;
wire [31:0] k0b, k1b, k2b, k3b, k4a;
assign {k0, k1, k2, k3} = in;
assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
assign v1 = v0 ^ k1;
assign v2 = v1 ^ k2;
assign v3 = v2 ^ k3;
always @ (posedge clk)
{k0a, k1a, k2a, k3a} <= {v0, v1, v2, v3};
S4
S4_0 (clk, {k3[23:0], k3[31:24]}, k4a);
assign k0b = k0a ^ k4a;
assign k1b = k1a ^ k4a;
assign k2b = k2a ^ k4a;
assign k3b = k3a ^ k4a;
always @ (posedge clk)
out_1 <= {k0b, k1b, k2b, k3b};
assign out_2 = {k0b, k1b, k2b, k3b};
endmodule
|
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// This is a fully unrolled implementation
module aes_192 (clk, rst, start, state, key, out, out_valid);
input clk;
input rst;
input start;
input [127:0] state;
input [191:0] key;
output [127:0] out;
output out_valid;
// Internals signals and such
reg [127:0] s0;
reg [191:0] k0;
wire [127:0] s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11;
wire [191:0] k1, k2, k3, k4, k5, k6, k7, k8, k9, k10, k11;
wire [127:0] k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b, k8b, k9b, k10b, k11b;
reg start_r;
wire start_posedge = start & ~start_r;
reg [4:0] validCounter;
always @(posedge clk or posedge rst)
begin
if (rst)
start_r <= 1'b0;
else
start_r <= start;
end // end always
always @ (posedge clk or posedge rst)
begin
if (rst) begin
s0 <= 0;
k0 <= 0;
validCounter <= 0;
end else
if(start_posedge)
begin
s0 <= state ^ key[191:64];
k0 <= key;
validCounter <= 26;
end
else if(validCounter > 1)
begin
validCounter <= validCounter - 1;
end
end // end always
assign out_valid = (validCounter == 1);
expand_key_type_D_192 a0 (clk, rst, k0, 8'h1, k1, k0b);
expand_key_type_B_192 a1 (clk, rst, k1, k2, k1b);
expand_key_type_A_192 a2 (clk, rst, k2, 8'h2, k3, k2b);
expand_key_type_C_192 a3 (clk, rst, k3, 8'h4, k4, k3b);
expand_key_type_B_192 a4 (clk, rst, k4, k5, k4b);
expand_key_type_A_192 a5 (clk, rst, k5, 8'h8, k6, k5b);
expand_key_type_C_192 a6 (clk, rst, k6, 8'h10, k7, k6b);
expand_key_type_B_192 a7 (clk, rst, k7, k8, k7b);
expand_key_type_A_192 a8 (clk, rst, k8, 8'h20, k9, k8b);
expand_key_type_C_192 a9 (clk, rst, k9, 8'h40, k10, k9b);
expand_key_type_B_192 a10 (clk, rst, k10, k11, k10b);
expand_key_type_A_192 a11 (clk, rst, k11, 8'h80, , k11b);
one_round
r1 (clk, rst, s0, k0b, s1),
r2 (clk, rst, s1, k1b, s2),
r3 (clk, rst, s2, k2b, s3),
r4 (clk, rst, s3, k3b, s4),
r5 (clk, rst, s4, k4b, s5),
r6 (clk, rst, s5, k5b, s6),
r7 (clk, rst, s6, k6b, s7),
r8 (clk, rst, s7, k7b, s8),
r9 (clk, rst, s8, k8b, s9),
r10 (clk, rst, s9, k9b, s10),
r11 (clk, rst, s10, k10b, s11);
final_round
rf (clk, rst, s11, k11b, out);
endmodule
/* expand k0,k1,k2,k3 for every two clock cycles */
module expand_key_type_A_192 (clk, rst, in, rcon, out_1, out_2);
input clk;
input rst;
input [191:0] in;
input [7:0] rcon;
output reg [191:0] out_1;
output [127:0] out_2;
// Internal signals
wire [31:0] k0, k1, k2, k3, k4, k5, v0, v1, v2, v3;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a;
wire [31:0] k0b, k1b, k2b, k3b, k4b, k5b, k6a;
assign {k0, k1, k2, k3, k4, k5} = in;
assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
assign v1 = v0 ^ k1;
assign v2 = v1 ^ k2;
assign v3 = v2 ^ k3;
always @ (posedge clk or posedge rst)
begin
if (rst)
{k0a, k1a, k2a, k3a, k4a, k5a} <= {32'd0, 32'd0, 32'd0, 32'd0, 32'd0, 32'd0};
else
{k0a, k1a, k2a, k3a, k4a, k5a} <= {v0, v1, v2, v3, k4, k5};
end // end always
S4 S4_0 (clk, rst, {k5[23:0], k5[31:24]}, k6a);
assign k0b = k0a ^ k6a;
assign k1b = k1a ^ k6a;
assign k2b = k2a ^ k6a;
assign k3b = k3a ^ k6a;
assign {k4b, k5b} = {k4a, k5a};
always @ (posedge clk or posedge rst)
begin
if (rst)
out_1 <= 0;
else
out_1 <= {k0b, k1b, k2b, k3b, k4b, k5b};
end // end always
assign out_2 = {k0b, k1b, k2b, k3b};
endmodule // end module expand_key_type_A_192
/* expand k2,k3,k4,k5 for every two clock cycles */
module expand_key_type_B_192 (clk, rst, in, out_1, out_2);
input clk;
input rst;
input [191:0] in;
output reg [191:0] out_1;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3, k4, k5, v2, v3, v4, v5;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a;
assign {k0, k1, k2, k3, k4, k5} = in;
assign v2 = k1 ^ k2;
assign v3 = v2 ^ k3;
assign v4 = v3 ^ k4;
assign v5 = v4 ^ k5;
always @ (posedge clk or posedge rst)
begin
if (rst)
{k0a, k1a, k2a, k3a, k4a, k5a} <= {32'd0, 32'd0, 32'd0, 32'd0, 32'd0, 32'd0};
else
{k0a, k1a, k2a, k3a, k4a, k5a} <= {k0, k1, v2, v3, v4, v5};
end // end always
always @ (posedge clk or posedge rst)
begin
if (rst)
out_1 <= 0;
else
out_1 <= {k0a, k1a, k2a, k3a, k4a, k5a};
end
assign out_2 = {k2a, k3a, k4a, k5a};
endmodule // end expand_key_type_B_192
/* expand k0,k1,k4,k5 for every two clock cycles */
module expand_key_type_C_192 (clk, rst, in, rcon, out_1, out_2);
input clk;
input rst;
input [191:0] in;
input [7:0] rcon;
output reg [191:0] out_1;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3, k4, k5, v4, v5, v0, v1;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a;
wire [31:0] k0b, k1b, k2b, k3b, k4b, k5b, k6a;
assign {k0, k1, k2, k3, k4, k5} = in;
assign v4 = k3 ^ k4;
assign v5 = v4 ^ k5;
assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
assign v1 = v0 ^ k1;
always @ (posedge clk or posedge rst)
begin
if (rst)
{k0a, k1a, k2a, k3a, k4a, k5a} <= {32'd0, 32'd0, 32'd0, 32'd0, 32'd0, 32'd0};
else
{k0a, k1a, k2a, k3a, k4a, k5a} <= {v0, v1, k2, k3, v4, v5};
end
S4 S4_0 (clk, rst, {v5[23:0], v5[31:24]}, k6a);
assign k0b = k0a ^ k6a;
assign k1b = k1a ^ k6a;
assign {k2b, k3b, k4b, k5b} = {k2a, k3a, k4a, k5a};
always @ (posedge clk or posedge rst)
begin
if (rst)
out_1 <= 0;
else
out_1 <= {k0b, k1b, k2b, k3b, k4b, k5b};
end
assign out_2 = {k4b, k5b, k0b, k1b};
endmodule // end expand_key_type_C_192
/* expand k0,k1 for every two clock cycles */
module expand_key_type_D_192 (clk, rst, in, rcon, out_1, out_2);
input clk;
input rst;
input [191:0] in;
input [7:0] rcon;
output reg [191:0] out_1;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3, k4, k5, v0, v1;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a;
wire [31:0] k0b, k1b, k2b, k3b, k4b, k5b, k6a;
assign {k0, k1, k2, k3, k4, k5} = in;
assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
assign v1 = v0 ^ k1;
always @ (posedge clk or posedge rst)
begin
if (rst)
{k0a, k1a, k2a, k3a, k4a, k5a} <= {32'd0, 32'd0, 32'd0, 32'd0, 32'd0, 32'd0};
else
{k0a, k1a, k2a, k3a, k4a, k5a} <= {v0, v1, k2, k3, k4, k5};
end // end always
S4 S4_0 (clk, rst, {k5[23:0], k5[31:24]}, k6a);
assign k0b = k0a ^ k6a;
assign k1b = k1a ^ k6a;
assign {k2b, k3b, k4b, k5b} = {k2a, k3a, k4a, k5a};
always @ (posedge clk or posedge rst)
begin
if (rst)
out_1 <= 0;
else
out_1 <= {k0b, k1b, k2b, k3b, k4b, k5b};
end // end always
assign out_2 = {k4b, k5b, k0b, k1b};
endmodule // end expand_key_type_D_192
|
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : aes_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-AES core
//
module aes_top(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
wb_ack_o, wb_err_o, wb_dat_o,
wb_clk_i, wb_rst_i, int_o
);
parameter dw = 32;
parameter aw = 32;
input [aw-1:0] wb_adr_i;
input wb_cyc_i;
input [dw-1:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_stb_i;
input wb_we_i;
output wb_ack_o;
output wb_err_o;
output reg [dw-1:0] wb_dat_o;
output int_o;
input wb_clk_i;
input wb_rst_i;
// As of now, no errors are generated
assign wb_err_o = 1'b0;
// Interrupt is unused
assign int_o = 1'b0;
// Internal registers
reg start, start_r;
reg [31:0] pt [0:3];
reg [31:0] key [0:5];
reg wb_stb_i_r;
wire [127:0] pt_big = {pt[0], pt[1], pt[2], pt[3]};
wire [191:0] key_big = {key[0], key[1], key[2], key[3], key[4], key[5]};
wire [127:0] ct;
wire ct_valid;
// Generate the acknowledgement signal
assign wb_ack_o = wb_stb_i_r && wb_stb_i;
// Implement MD5 I/O memory map interface
// Write side
always @(posedge wb_clk_i or negedge wb_rst_i)
begin
if(wb_rst_i)
begin
start <= 0;
start_r <= 0;
pt[0] <= 0;
pt[1] <= 0;
pt[2] <= 0;
pt[3] <= 0;
key[0] <= 0;
key[1] <= 0;
key[2] <= 0;
key[3] <= 0;
key[4] <= 0;
key[5] <= 0;
wb_stb_i_r <= 1'b0;
end
else begin
// Generate registered version of start (for edge detection)
start_r <= start;
// Generate a registered version of the write strobe
wb_stb_i_r <= wb_stb_i;
// Perform a write
if(wb_stb_i & wb_we_i) begin
case(wb_adr_i[5:2])
0: start <= wb_dat_i[0];
1: pt[3] <= wb_dat_i;
2: pt[2] <= wb_dat_i;
3: pt[1] <= wb_dat_i;
4: pt[0] <= wb_dat_i;
5: key[5] <= wb_dat_i;
6: key[4] <= wb_dat_i;
7: key[3] <= wb_dat_i;
8: key[2] <= wb_dat_i;
9: key[1] <= wb_dat_i;
10: key[0] <= wb_dat_i;
default:
;
endcase
end else begin // end if wb_stb_i & wb_we_i
start <= 1'b0;
end
end // end else begin
end // always @ (posedge wb_clk_i)
// Implement MD5 I/O memory map interface
// Read side
always @(*)
begin
case(wb_adr_i[5:2])
1:
wb_dat_o = pt[3];
2:
wb_dat_o = pt[2];
3:
wb_dat_o = pt[1];
4:
wb_dat_o = pt[0];
5:
wb_dat_o = key[5];
6:
wb_dat_o = key[4];
7:
wb_dat_o = key[3];
8:
wb_dat_o = key[2];
9:
wb_dat_o = key[1];
10:
wb_dat_o = key[0];
11:
wb_dat_o = {31'b0, ct_valid};
12:
wb_dat_o = ct[127:96];
13:
wb_dat_o = ct[95:64];
14:
wb_dat_o = ct[63:32];
15:
wb_dat_o = ct[31:0];
default:
wb_dat_o = 32'b0;
endcase
end // always @ (*)
aes_192 aes(
.clk(wb_clk_i),
.rst(wb_rst_i),
.state(pt_big),
.key(key_big),
.start(start && ~start_r), // start on detected position edge
.out(ct),
.out_valid(ct_valid)
);
endmodule
|
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : aes_top_axi4lite.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides an axi4-lite wrapper for the wishbone based-AES core
//
module aes_top_axi4lite (
// Clock & Reset
input logic clk_i,
input logic rst_ni,
// AXI4-Lite Slave Interface
AXI_LITE.Slave slave
);
// AES wishbone slave wires
wire wb_clk;
wire wb_rst;
wire wb_rst_n;
wire [slave.AXI_ADDR_WIDTH - 1:0] wbs_d_aes_adr_i;
wire [slave.AXI_DATA_WIDTH - 1:0] wbs_d_aes_dat_i;
wire [3:0] wbs_d_aes_sel_i;
wire wbs_d_aes_we_i;
wire wbs_d_aes_cyc_i;
wire wbs_d_aes_stb_i;
wire [slave.AXI_DATA_WIDTH - 1:0] wbs_d_aes_dat_o;
wire wbs_d_aes_ack_o;
// Instantiate the AXI4Lite to Wishbone bridge
bonfire_axi4l2wb #(
.ADRWIDTH (slave.AXI_ADDR_WIDTH),
.FAST_READ_TERM (1'd0)
) bonfire_axi4l2wb_inst (
.S_AXI_ACLK (clk_i),
.S_AXI_ARESETN (rst_ni),
.S_AXI_AWADDR (slave.aw_addr),
.S_AXI_AWVALID (slave.aw_valid),
.S_AXI_AWREADY (slave.aw_ready),
.S_AXI_WDATA (slave.w_data),
.S_AXI_WSTRB (slave.w_strb),
.S_AXI_WVALID (slave.w_valid),
.S_AXI_WREADY (slave.w_ready),
.S_AXI_ARADDR (slave.ar_addr),
.S_AXI_ARVALID (slave.ar_valid),
.S_AXI_ARREADY (slave.ar_ready),
.S_AXI_RDATA (slave.r_data),
.S_AXI_RRESP (slave.r_resp),
.S_AXI_RVALID (slave.r_valid),
.S_AXI_RREADY (slave.r_ready),
.S_AXI_BRESP (slave.b_resp),
.S_AXI_BVALID (slave.b_valid),
.S_AXI_BREADY (slave.b_ready),
.wb_clk_o (wb_clk),
.wb_rst_o (wb_rst),
.wb_addr_o (wbs_d_aes_adr_i),
.wb_dat_o (wbs_d_aes_dat_i),
.wb_we_o (wbs_d_aes_we_i),
.wb_sel_o (wbs_d_aes_sel_i),
.wb_stb_o (wbs_d_aes_stb_i),
.wb_cyc_o (wbs_d_aes_cyc_i),
.wb_dat_i (wbs_d_aes_dat_o),
.wb_ack_i (wbs_d_aes_ack_o)
);
// Instantiate the wishbone-based AES Core
aes_top aes (
// Wishbone Slave interface
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.wb_dat_i (wbs_d_aes_dat_i),
.wb_adr_i (wbs_d_aes_adr_i),
.wb_sel_i (wbs_d_aes_sel_i[3:0]),
.wb_we_i (wbs_d_aes_we_i),
.wb_cyc_i (wbs_d_aes_cyc_i),
.wb_stb_i (wbs_d_aes_stb_i),
.wb_dat_o (wbs_d_aes_dat_o),
.wb_err_o (),
.wb_ack_o (wbs_d_aes_ack_o),
// Processor interrupt
.int_o ()
);
endmodule // end aes_top_axi4lite
|
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* verilator lint_off UNOPTFLAT */
/* one AES round for every two clock cycles */
module one_round (clk, rst, state_in, key, state_out);
input clk;
input rst;
input [127:0] state_in, key;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
p00, p01, p02, p03,
p10, p11, p12, p13,
p20, p21, p22, p23,
p30, p31, p32, p33,
k0, k1, k2, k3;
assign {k0, k1, k2, k3} = key;
assign {s0, s1, s2, s3} = state_in;
table_lookup
t0 (clk, rst, s0, p00, p01, p02, p03),
t1 (clk, rst, s1, p10, p11, p12, p13),
t2 (clk, rst, s2, p20, p21, p22, p23),
t3 (clk, rst, s3, p30, p31, p32, p33);
assign z0 = p00 ^ p11 ^ p22 ^ p33 ^ k0;
assign z1 = p03 ^ p10 ^ p21 ^ p32 ^ k1;
assign z2 = p02 ^ p13 ^ p20 ^ p31 ^ k2;
assign z3 = p01 ^ p12 ^ p23 ^ p30 ^ k3;
always @ (posedge clk)
state_out <= {z0, z1, z2, z3};
endmodule
/* AES final round for every two clock cycles */
module final_round (clk, rst, state_in, key_in, state_out);
input clk;
input rst;
input [127:0] state_in;
input [127:0] key_in;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
k0, k1, k2, k3;
wire [7:0] p00, p01, p02, p03,
p10, p11, p12, p13,
p20, p21, p22, p23,
p30, p31, p32, p33;
assign {k0, k1, k2, k3} = key_in;
assign {s0, s1, s2, s3} = state_in;
S4
S4_1 (clk, rst, s0, {p00, p01, p02, p03}),
S4_2 (clk, rst, s1, {p10, p11, p12, p13}),
S4_3 (clk, rst, s2, {p20, p21, p22, p23}),
S4_4 (clk, rst, s3, {p30, p31, p32, p33});
assign z0 = {p00, p11, p22, p33} ^ k0;
assign z1 = {p10, p21, p32, p03} ^ k1;
assign z2 = {p20, p31, p02, p13} ^ k2;
assign z3 = {p30, p01, p12, p23} ^ k3;
always @ (posedge clk or posedge rst)
if (rst)
state_out <= 0;
else
state_out <= {z0, z1, z2, z3};
endmodule
|
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* verilator lint_off UNOPTFLAT */
module table_lookup (clk, rst, state, p0, p1, p2, p3);
input clk;
input rst;
input [31:0] state;
output [31:0] p0, p1, p2, p3;
wire [7:0] b0, b1, b2, b3;
assign {b0, b1, b2, b3} = state;
T
t0 (clk, rst, b0, {p0[23:0], p0[31:24]}),
t1 (clk, rst, b1, {p1[15:0], p1[31:16]}),
t2 (clk, rst, b2, {p2[7:0], p2[31:8]} ),
t3 (clk, rst, b3, p3);
endmodule // end table_lookup
/* substitue four bytes in a word */
module S4 (clk, rst, in, out);
input clk;
input rst;
input [31:0] in;
output [31:0] out;
S
S_0 (clk, rst, in[31:24], out[31:24]),
S_1 (clk, rst, in[23:16], out[23:16]),
S_2 (clk, rst, in[15:8], out[15:8] ),
S_3 (clk, rst, in[7:0], out[7:0] );
endmodule // end S4
/* S_box, S_box, S_box*(x+1), S_box*x */
module T (clk, rst, in, out);
input clk;
input rst;
input [7:0] in;
output [31:0] out;
S
s0 (clk, rst, in, out[31:24]);
assign out[23:16] = out[31:24];
xS
s4 (clk, rst, in, out[7:0]);
assign out[15:8] = out[23:16] ^ out[7:0];
endmodule // end T
/* S box */
module S (clk, rst, in, out);
input clk;
input rst;
input [7:0] in;
output reg [7:0] out;
always @ (posedge clk or posedge rst)
if (rst)
out <= 8'd0;
else
case (in)
8'h00: out <= 8'h63;
8'h01: out <= 8'h7c;
8'h02: out <= 8'h77;
8'h03: out <= 8'h7b;
8'h04: out <= 8'hf2;
8'h05: out <= 8'h6b;
8'h06: out <= 8'h6f;
8'h07: out <= 8'hc5;
8'h08: out <= 8'h30;
8'h09: out <= 8'h01;
8'h0a: out <= 8'h67;
8'h0b: out <= 8'h2b;
8'h0c: out <= 8'hfe;
8'h0d: out <= 8'hd7;
8'h0e: out <= 8'hab;
8'h0f: out <= 8'h76;
8'h10: out <= 8'hca;
8'h11: out <= 8'h82;
8'h12: out <= 8'hc9;
8'h13: out <= 8'h7d;
8'h14: out <= 8'hfa;
8'h15: out <= 8'h59;
8'h16: out <= 8'h47;
8'h17: out <= 8'hf0;
8'h18: out <= 8'had;
8'h19: out <= 8'hd4;
8'h1a: out <= 8'ha2;
8'h1b: out <= 8'haf;
8'h1c: out <= 8'h9c;
8'h1d: out <= 8'ha4;
8'h1e: out <= 8'h72;
8'h1f: out <= 8'hc0;
8'h20: out <= 8'hb7;
8'h21: out <= 8'hfd;
8'h22: out <= 8'h93;
8'h23: out <= 8'h26;
8'h24: out <= 8'h36;
8'h25: out <= 8'h3f;
8'h26: out <= 8'hf7;
8'h27: out <= 8'hcc;
8'h28: out <= 8'h34;
8'h29: out <= 8'ha5;
8'h2a: out <= 8'he5;
8'h2b: out <= 8'hf1;
8'h2c: out <= 8'h71;
8'h2d: out <= 8'hd8;
8'h2e: out <= 8'h31;
8'h2f: out <= 8'h15;
8'h30: out <= 8'h04;
8'h31: out <= 8'hc7;
8'h32: out <= 8'h23;
8'h33: out <= 8'hc3;
8'h34: out <= 8'h18;
8'h35: out <= 8'h96;
8'h36: out <= 8'h05;
8'h37: out <= 8'h9a;
8'h38: out <= 8'h07;
8'h39: out <= 8'h12;
8'h3a: out <= 8'h80;
8'h3b: out <= 8'he2;
8'h3c: out <= 8'heb;
8'h3d: out <= 8'h27;
8'h3e: out <= 8'hb2;
8'h3f: out <= 8'h75;
8'h40: out <= 8'h09;
8'h41: out <= 8'h83;
8'h42: out <= 8'h2c;
8'h43: out <= 8'h1a;
8'h44: out <= 8'h1b;
8'h45: out <= 8'h6e;
8'h46: out <= 8'h5a;
8'h47: out <= 8'ha0;
8'h48: out <= 8'h52;
8'h49: out <= 8'h3b;
8'h4a: out <= 8'hd6;
8'h4b: out <= 8'hb3;
8'h4c: out <= 8'h29;
8'h4d: out <= 8'he3;
8'h4e: out <= 8'h2f;
8'h4f: out <= 8'h84;
8'h50: out <= 8'h53;
8'h51: out <= 8'hd1;
8'h52: out <= 8'h00;
8'h53: out <= 8'hed;
8'h54: out <= 8'h20;
8'h55: out <= 8'hfc;
8'h56: out <= 8'hb1;
8'h57: out <= 8'h5b;
8'h58: out <= 8'h6a;
8'h59: out <= 8'hcb;
8'h5a: out <= 8'hbe;
8'h5b: out <= 8'h39;
8'h5c: out <= 8'h4a;
8'h5d: out <= 8'h4c;
8'h5e: out <= 8'h58;
8'h5f: out <= 8'hcf;
8'h60: out <= 8'hd0;
8'h61: out <= 8'hef;
8'h62: out <= 8'haa;
8'h63: out <= 8'hfb;
8'h64: out <= 8'h43;
8'h65: out <= 8'h4d;
8'h66: out <= 8'h33;
8'h67: out <= 8'h85;
8'h68: out <= 8'h45;
8'h69: out <= 8'hf9;
8'h6a: out <= 8'h02;
8'h6b: out <= 8'h7f;
8'h6c: out <= 8'h50;
8'h6d: out <= 8'h3c;
8'h6e: out <= 8'h9f;
8'h6f: out <= 8'ha8;
8'h70: out <= 8'h51;
8'h71: out <= 8'ha3;
8'h72: out <= 8'h40;
8'h73: out <= 8'h8f;
8'h74: out <= 8'h92;
8'h75: out <= 8'h9d;
8'h76: out <= 8'h38;
8'h77: out <= 8'hf5;
8'h78: out <= 8'hbc;
8'h79: out <= 8'hb6;
8'h7a: out <= 8'hda;
8'h7b: out <= 8'h21;
8'h7c: out <= 8'h10;
8'h7d: out <= 8'hff;
8'h7e: out <= 8'hf3;
8'h7f: out <= 8'hd2;
8'h80: out <= 8'hcd;
8'h81: out <= 8'h0c;
8'h82: out <= 8'h13;
8'h83: out <= 8'hec;
8'h84: out <= 8'h5f;
8'h85: out <= 8'h97;
8'h86: out <= 8'h44;
8'h87: out <= 8'h17;
8'h88: out <= 8'hc4;
8'h89: out <= 8'ha7;
8'h8a: out <= 8'h7e;
8'h8b: out <= 8'h3d;
8'h8c: out <= 8'h64;
8'h8d: out <= 8'h5d;
8'h8e: out <= 8'h19;
8'h8f: out <= 8'h73;
8'h90: out <= 8'h60;
8'h91: out <= 8'h81;
8'h92: out <= 8'h4f;
8'h93: out <= 8'hdc;
8'h94: out <= 8'h22;
8'h95: out <= 8'h2a;
8'h96: out <= 8'h90;
8'h97: out <= 8'h88;
8'h98: out <= 8'h46;
8'h99: out <= 8'hee;
8'h9a: out <= 8'hb8;
8'h9b: out <= 8'h14;
8'h9c: out <= 8'hde;
8'h9d: out <= 8'h5e;
8'h9e: out <= 8'h0b;
8'h9f: out <= 8'hdb;
8'ha0: out <= 8'he0;
8'ha1: out <= 8'h32;
8'ha2: out <= 8'h3a;
8'ha3: out <= 8'h0a;
8'ha4: out <= 8'h49;
8'ha5: out <= 8'h06;
8'ha6: out <= 8'h24;
8'ha7: out <= 8'h5c;
8'ha8: out <= 8'hc2;
8'ha9: out <= 8'hd3;
8'haa: out <= 8'hac;
8'hab: out <= 8'h62;
8'hac: out <= 8'h91;
8'had: out <= 8'h95;
8'hae: out <= 8'he4;
8'haf: out <= 8'h79;
8'hb0: out <= 8'he7;
8'hb1: out <= 8'hc8;
8'hb2: out <= 8'h37;
8'hb3: out <= 8'h6d;
8'hb4: out <= 8'h8d;
8'hb5: out <= 8'hd5;
8'hb6: out <= 8'h4e;
8'hb7: out <= 8'ha9;
8'hb8: out <= 8'h6c;
8'hb9: out <= 8'h56;
8'hba: out <= 8'hf4;
8'hbb: out <= 8'hea;
8'hbc: out <= 8'h65;
8'hbd: out <= 8'h7a;
8'hbe: out <= 8'hae;
8'hbf: out <= 8'h08;
8'hc0: out <= 8'hba;
8'hc1: out <= 8'h78;
8'hc2: out <= 8'h25;
8'hc3: out <= 8'h2e;
8'hc4: out <= 8'h1c;
8'hc5: out <= 8'ha6;
8'hc6: out <= 8'hb4;
8'hc7: out <= 8'hc6;
8'hc8: out <= 8'he8;
8'hc9: out <= 8'hdd;
8'hca: out <= 8'h74;
8'hcb: out <= 8'h1f;
8'hcc: out <= 8'h4b;
8'hcd: out <= 8'hbd;
8'hce: out <= 8'h8b;
8'hcf: out <= 8'h8a;
8'hd0: out <= 8'h70;
8'hd1: out <= 8'h3e;
8'hd2: out <= 8'hb5;
8'hd3: out <= 8'h66;
8'hd4: out <= 8'h48;
8'hd5: out <= 8'h03;
8'hd6: out <= 8'hf6;
8'hd7: out <= 8'h0e;
8'hd8: out <= 8'h61;
8'hd9: out <= 8'h35;
8'hda: out <= 8'h57;
8'hdb: out <= 8'hb9;
8'hdc: out <= 8'h86;
8'hdd: out <= 8'hc1;
8'hde: out <= 8'h1d;
8'hdf: out <= 8'h9e;
8'he0: out <= 8'he1;
8'he1: out <= 8'hf8;
8'he2: out <= 8'h98;
8'he3: out <= 8'h11;
8'he4: out <= 8'h69;
8'he5: out <= 8'hd9;
8'he6: out <= 8'h8e;
8'he7: out <= 8'h94;
8'he8: out <= 8'h9b;
8'he9: out <= 8'h1e;
8'hea: out <= 8'h87;
8'heb: out <= 8'he9;
8'hec: out <= 8'hce;
8'hed: out <= 8'h55;
8'hee: out <= 8'h28;
8'hef: out <= 8'hdf;
8'hf0: out <= 8'h8c;
8'hf1: out <= 8'ha1;
8'hf2: out <= 8'h89;
8'hf3: out <= 8'h0d;
8'hf4: out <= 8'hbf;
8'hf5: out <= 8'he6;
8'hf6: out <= 8'h42;
8'hf7: out <= 8'h68;
8'hf8: out <= 8'h41;
8'hf9: out <= 8'h99;
8'hfa: out <= 8'h2d;
8'hfb: out <= 8'h0f;
8'hfc: out <= 8'hb0;
8'hfd: out <= 8'h54;
8'hfe: out <= 8'hbb;
8'hff: out <= 8'h16;
endcase
endmodule
/* S box * x */
module xS (clk, rst, in, out);
input clk;
input rst;
input [7:0] in;
output reg [7:0] out;
always @ (posedge clk or posedge rst)
if (rst)
out <= 8'd0;
else
case (in)
8'h00: out <= 8'hc6;
8'h01: out <= 8'hf8;
8'h02: out <= 8'hee;
8'h03: out <= 8'hf6;
8'h04: out <= 8'hff;
8'h05: out <= 8'hd6;
8'h06: out <= 8'hde;
8'h07: out <= 8'h91;
8'h08: out <= 8'h60;
8'h09: out <= 8'h02;
8'h0a: out <= 8'hce;
8'h0b: out <= 8'h56;
8'h0c: out <= 8'he7;
8'h0d: out <= 8'hb5;
8'h0e: out <= 8'h4d;
8'h0f: out <= 8'hec;
8'h10: out <= 8'h8f;
8'h11: out <= 8'h1f;
8'h12: out <= 8'h89;
8'h13: out <= 8'hfa;
8'h14: out <= 8'hef;
8'h15: out <= 8'hb2;
8'h16: out <= 8'h8e;
8'h17: out <= 8'hfb;
8'h18: out <= 8'h41;
8'h19: out <= 8'hb3;
8'h1a: out <= 8'h5f;
8'h1b: out <= 8'h45;
8'h1c: out <= 8'h23;
8'h1d: out <= 8'h53;
8'h1e: out <= 8'he4;
8'h1f: out <= 8'h9b;
8'h20: out <= 8'h75;
8'h21: out <= 8'he1;
8'h22: out <= 8'h3d;
8'h23: out <= 8'h4c;
8'h24: out <= 8'h6c;
8'h25: out <= 8'h7e;
8'h26: out <= 8'hf5;
8'h27: out <= 8'h83;
8'h28: out <= 8'h68;
8'h29: out <= 8'h51;
8'h2a: out <= 8'hd1;
8'h2b: out <= 8'hf9;
8'h2c: out <= 8'he2;
8'h2d: out <= 8'hab;
8'h2e: out <= 8'h62;
8'h2f: out <= 8'h2a;
8'h30: out <= 8'h08;
8'h31: out <= 8'h95;
8'h32: out <= 8'h46;
8'h33: out <= 8'h9d;
8'h34: out <= 8'h30;
8'h35: out <= 8'h37;
8'h36: out <= 8'h0a;
8'h37: out <= 8'h2f;
8'h38: out <= 8'h0e;
8'h39: out <= 8'h24;
8'h3a: out <= 8'h1b;
8'h3b: out <= 8'hdf;
8'h3c: out <= 8'hcd;
8'h3d: out <= 8'h4e;
8'h3e: out <= 8'h7f;
8'h3f: out <= 8'hea;
8'h40: out <= 8'h12;
8'h41: out <= 8'h1d;
8'h42: out <= 8'h58;
8'h43: out <= 8'h34;
8'h44: out <= 8'h36;
8'h45: out <= 8'hdc;
8'h46: out <= 8'hb4;
8'h47: out <= 8'h5b;
8'h48: out <= 8'ha4;
8'h49: out <= 8'h76;
8'h4a: out <= 8'hb7;
8'h4b: out <= 8'h7d;
8'h4c: out <= 8'h52;
8'h4d: out <= 8'hdd;
8'h4e: out <= 8'h5e;
8'h4f: out <= 8'h13;
8'h50: out <= 8'ha6;
8'h51: out <= 8'hb9;
8'h52: out <= 8'h00;
8'h53: out <= 8'hc1;
8'h54: out <= 8'h40;
8'h55: out <= 8'he3;
8'h56: out <= 8'h79;
8'h57: out <= 8'hb6;
8'h58: out <= 8'hd4;
8'h59: out <= 8'h8d;
8'h5a: out <= 8'h67;
8'h5b: out <= 8'h72;
8'h5c: out <= 8'h94;
8'h5d: out <= 8'h98;
8'h5e: out <= 8'hb0;
8'h5f: out <= 8'h85;
8'h60: out <= 8'hbb;
8'h61: out <= 8'hc5;
8'h62: out <= 8'h4f;
8'h63: out <= 8'hed;
8'h64: out <= 8'h86;
8'h65: out <= 8'h9a;
8'h66: out <= 8'h66;
8'h67: out <= 8'h11;
8'h68: out <= 8'h8a;
8'h69: out <= 8'he9;
8'h6a: out <= 8'h04;
8'h6b: out <= 8'hfe;
8'h6c: out <= 8'ha0;
8'h6d: out <= 8'h78;
8'h6e: out <= 8'h25;
8'h6f: out <= 8'h4b;
8'h70: out <= 8'ha2;
8'h71: out <= 8'h5d;
8'h72: out <= 8'h80;
8'h73: out <= 8'h05;
8'h74: out <= 8'h3f;
8'h75: out <= 8'h21;
8'h76: out <= 8'h70;
8'h77: out <= 8'hf1;
8'h78: out <= 8'h63;
8'h79: out <= 8'h77;
8'h7a: out <= 8'haf;
8'h7b: out <= 8'h42;
8'h7c: out <= 8'h20;
8'h7d: out <= 8'he5;
8'h7e: out <= 8'hfd;
8'h7f: out <= 8'hbf;
8'h80: out <= 8'h81;
8'h81: out <= 8'h18;
8'h82: out <= 8'h26;
8'h83: out <= 8'hc3;
8'h84: out <= 8'hbe;
8'h85: out <= 8'h35;
8'h86: out <= 8'h88;
8'h87: out <= 8'h2e;
8'h88: out <= 8'h93;
8'h89: out <= 8'h55;
8'h8a: out <= 8'hfc;
8'h8b: out <= 8'h7a;
8'h8c: out <= 8'hc8;
8'h8d: out <= 8'hba;
8'h8e: out <= 8'h32;
8'h8f: out <= 8'he6;
8'h90: out <= 8'hc0;
8'h91: out <= 8'h19;
8'h92: out <= 8'h9e;
8'h93: out <= 8'ha3;
8'h94: out <= 8'h44;
8'h95: out <= 8'h54;
8'h96: out <= 8'h3b;
8'h97: out <= 8'h0b;
8'h98: out <= 8'h8c;
8'h99: out <= 8'hc7;
8'h9a: out <= 8'h6b;
8'h9b: out <= 8'h28;
8'h9c: out <= 8'ha7;
8'h9d: out <= 8'hbc;
8'h9e: out <= 8'h16;
8'h9f: out <= 8'had;
8'ha0: out <= 8'hdb;
8'ha1: out <= 8'h64;
8'ha2: out <= 8'h74;
8'ha3: out <= 8'h14;
8'ha4: out <= 8'h92;
8'ha5: out <= 8'h0c;
8'ha6: out <= 8'h48;
8'ha7: out <= 8'hb8;
8'ha8: out <= 8'h9f;
8'ha9: out <= 8'hbd;
8'haa: out <= 8'h43;
8'hab: out <= 8'hc4;
8'hac: out <= 8'h39;
8'had: out <= 8'h31;
8'hae: out <= 8'hd3;
8'haf: out <= 8'hf2;
8'hb0: out <= 8'hd5;
8'hb1: out <= 8'h8b;
8'hb2: out <= 8'h6e;
8'hb3: out <= 8'hda;
8'hb4: out <= 8'h01;
8'hb5: out <= 8'hb1;
8'hb6: out <= 8'h9c;
8'hb7: out <= 8'h49;
8'hb8: out <= 8'hd8;
8'hb9: out <= 8'hac;
8'hba: out <= 8'hf3;
8'hbb: out <= 8'hcf;
8'hbc: out <= 8'hca;
8'hbd: out <= 8'hf4;
8'hbe: out <= 8'h47;
8'hbf: out <= 8'h10;
8'hc0: out <= 8'h6f;
8'hc1: out <= 8'hf0;
8'hc2: out <= 8'h4a;
8'hc3: out <= 8'h5c;
8'hc4: out <= 8'h38;
8'hc5: out <= 8'h57;
8'hc6: out <= 8'h73;
8'hc7: out <= 8'h97;
8'hc8: out <= 8'hcb;
8'hc9: out <= 8'ha1;
8'hca: out <= 8'he8;
8'hcb: out <= 8'h3e;
8'hcc: out <= 8'h96;
8'hcd: out <= 8'h61;
8'hce: out <= 8'h0d;
8'hcf: out <= 8'h0f;
8'hd0: out <= 8'he0;
8'hd1: out <= 8'h7c;
8'hd2: out <= 8'h71;
8'hd3: out <= 8'hcc;
8'hd4: out <= 8'h90;
8'hd5: out <= 8'h06;
8'hd6: out <= 8'hf7;
8'hd7: out <= 8'h1c;
8'hd8: out <= 8'hc2;
8'hd9: out <= 8'h6a;
8'hda: out <= 8'hae;
8'hdb: out <= 8'h69;
8'hdc: out <= 8'h17;
8'hdd: out <= 8'h99;
8'hde: out <= 8'h3a;
8'hdf: out <= 8'h27;
8'he0: out <= 8'hd9;
8'he1: out <= 8'heb;
8'he2: out <= 8'h2b;
8'he3: out <= 8'h22;
8'he4: out <= 8'hd2;
8'he5: out <= 8'ha9;
8'he6: out <= 8'h07;
8'he7: out <= 8'h33;
8'he8: out <= 8'h2d;
8'he9: out <= 8'h3c;
8'hea: out <= 8'h15;
8'heb: out <= 8'hc9;
8'hec: out <= 8'h87;
8'hed: out <= 8'haa;
8'hee: out <= 8'h50;
8'hef: out <= 8'ha5;
8'hf0: out <= 8'h03;
8'hf1: out <= 8'h59;
8'hf2: out <= 8'h09;
8'hf3: out <= 8'h1a;
8'hf4: out <= 8'h65;
8'hf5: out <= 8'hd7;
8'hf6: out <= 8'h84;
8'hf7: out <= 8'hd0;
8'hf8: out <= 8'h82;
8'hf9: out <= 8'h29;
8'hfa: out <= 8'h5a;
8'hfb: out <= 8'h1e;
8'hfc: out <= 8'h7b;
8'hfd: out <= 8'ha8;
8'hfe: out <= 8'h6d;
8'hff: out <= 8'h2c;
endcase
endmodule
|
// Copyright (c) 2014-2018 ETH Zurich, University of Bologna
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Fabian Schuiki <[email protected]>
/// An address resolver.
///
/// Matches an address against a routing table and produces the index of the
/// matching slave.
module axi_address_resolver #(
/// The address width.
parameter int ADDR_WIDTH = -1,
/// The number of slaves.
parameter int NUM_SLAVE = -1,
/// The number of rules.
parameter int NUM_RULES = -1
)(
AXI_ROUTING_RULES.xbar rules ,
input logic [ADDR_WIDTH-1:0] addr_i ,
output logic [$clog2(NUM_SLAVE)-1:0] match_idx_o ,
output logic match_ok_o
);
logic [NUM_SLAVE-1:0][NUM_RULES-1:0] matched_rules;
logic [NUM_SLAVE-1:0] matched_slaves;
for (genvar i = 0; i < NUM_SLAVE; i++) begin : g_slave
// Match each of the rules.
for (genvar j = 0; j < NUM_RULES; j++) begin : g_rule
logic [ADDR_WIDTH-1:0] base, mask;
logic enabled;
assign base = rules.rules[i][j].base;
assign mask = rules.rules[i][j].mask;
assign enabled = rules.rules[i][j].enabled;
// If the rules is disabled, it matches nothing.
assign matched_rules[i][j] = (enabled && (addr_i & mask) == (base & mask));
end
// Check which slaves matched.
assign matched_slaves[i] = |matched_rules[i];
end
// // If anything matched the address, output ok.
assign match_ok_o = |matched_slaves;
// Determine the index of the slave that matched.
// find_first_one #(.WIDTH(NUM_SLAVE), .FLIP(0)) i_lzc (
// .in_i ( matched_slaves ),
// .first_one_o ( match_idx_o ),
// .no_ones_o ( )
// );
// Ensure that we have a one-hot match. If we don't, this implies that the
// rules in the routing table are not mututally exclusive.
`ifndef SYNTHESIS
always @(matched_rules, matched_slaves) begin
assert ($onehot0(matched_rules)) else $error("%m: more than one rule matches 0x%0h: %0b", addr_i, matched_rules);
assert ($onehot0(matched_slaves)) else $error("%m: more than one slave matches 0x%0h: %0b", addr_i, matched_slaves);
end
`endif
endmodule
|
// Copyright (c) 2014-2018 ETH Zurich, University of Bologna
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Fabian Schuiki <[email protected]>
/// A round-robin arbiter.
module axi_arbiter #(
/// The number of requestors.
parameter int NUM_REQ = -1
)(
input logic clk_i ,
input logic rst_ni ,
AXI_ARBITRATION.arb arb
);
`ifndef SYNTHESIS
initial begin
assert(NUM_REQ >= 0);
assert(arb.NUM_REQ == NUM_REQ);
end
`endif
logic [$clog2(NUM_REQ)-1:0] count_d, count_q;
axi_arbiter_tree #(
.NUM_REQ ( NUM_REQ ),
.ID_WIDTH ( 0 )
) i_tree (
.in_req_i ( arb.in_req ),
.in_ack_o ( arb.in_ack ),
.in_id_i ( '0 ),
.out_req_o ( arb.out_req ),
.out_ack_i ( arb.out_ack ),
.out_id_o ( arb.out_sel ),
.shift_i ( count_q )
);
always_ff @(posedge clk_i or negedge rst_ni) begin
if (~rst_ni) begin
count_q <= '0;
end else if (arb.out_req && arb.out_ack) begin
count_q <= (count_d == NUM_REQ ? '0 : count_d);
end
end
assign count_d = count_q + 1;
endmodule
/// An arbitration tree.
module axi_arbiter_tree #(
/// The number of requestors.
parameter int NUM_REQ = -1,
/// The width of the ID on the requestor side.
parameter int ID_WIDTH = -1
)(
input logic [NUM_REQ-1:0] in_req_i ,
output logic [NUM_REQ-1:0] in_ack_o ,
input logic [NUM_REQ-1:0][ID_WIDTH-1:0] in_id_i ,
output logic out_req_o ,
input logic out_ack_i ,
output logic [ID_WIDTH+$clog2(NUM_REQ)-1:0] out_id_o ,
input logic [$clog2(NUM_REQ)-1:0] shift_i
);
`ifndef SYNTHESIS
initial begin
assert(NUM_REQ >= 0);
assert(ID_WIDTH >= 0);
end
`endif
// Calculate the number of requests after the head multiplexers. This is equal
// to ceil(NUM_REQ/2).
localparam int NUM_INNER_REQ = NUM_REQ > 0 ? 2**($clog2(NUM_REQ)-1) : 0;
localparam logic [ID_WIDTH:0] ID_MASK = (1 << ID_WIDTH) - 1;
// Extract the bit that we use for shifting the priorities in the head.
logic shift_bit;
assign shift_bit = shift_i[$high(shift_i)];
// Perform pairwise arbitration on the head.
logic [NUM_INNER_REQ-1:0] inner_req, inner_ack;
logic [NUM_INNER_REQ-1:0][ID_WIDTH:0] inner_id;
for (genvar i = 0; i < NUM_INNER_REQ; i++) begin : g_head
localparam iA = i*2;
localparam iB = i*2+1;
if (iB < NUM_REQ) begin
// Decide who wins arbitration. If both A and B issue a request, shift_bit
// is used as a tie breaker. Otherwise we simply grant the request.
logic sel;
always_comb begin
if (in_req_i[iA] && in_req_i[iB])
sel = shift_bit;
else if (in_req_i[iA])
sel = 0;
else if (in_req_i[iB])
sel = 1;
else
sel = 0;
end
assign inner_req[i] = in_req_i[iA] | in_req_i[iB];
assign in_ack_o[iA] = inner_ack[i] && (sel == 0);
assign in_ack_o[iB] = inner_ack[i] && (sel == 1);
assign inner_id[i] = (sel << ID_WIDTH) | ((sel ? in_id_i[iB] : in_id_i[iA]) & ID_MASK);
end else if (iA < NUM_REQ) begin
assign inner_req[i] = in_req_i[iA];
assign in_ack_o[iA] = inner_ack[i];
assign inner_id[i] = in_id_i[iA] & ID_MASK;
end
end
// Instantiate the tail of the tree.
if (NUM_INNER_REQ > 1) begin : g_tail
axi_arbiter_tree #(
.NUM_REQ ( NUM_INNER_REQ ),
.ID_WIDTH ( ID_WIDTH+1 )
) i_tail (
.in_req_i ( inner_req ),
.in_ack_o ( inner_ack ),
.in_id_i ( inner_id ),
.out_req_o ( out_req_o ),
.out_ack_i ( out_ack_i ),
.out_id_o ( out_id_o ),
.shift_i ( shift_i[$high(shift_i)-1:0] )
);
end else if (NUM_INNER_REQ == 1) begin : g_tail
assign out_req_o = inner_req;
assign inner_ack = out_ack_i;
assign out_id_o = inner_id[0];
end else begin : g_tail
assign out_req_o = in_req_i[0];
assign in_ack_o[0] = out_ack_i;
assign out_id_o = in_id_i[0];
end
endmodule
|
// Copyright (c) 2014-2018 ETH Zurich, University of Bologna
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Fabian Schuiki <[email protected]>
//
// This file defines the interfaces we support.
import axi_pkg::*;
/// An AXI4 interface.
interface AXI_BUS #(
parameter AXI_ADDR_WIDTH = -1,
parameter AXI_DATA_WIDTH = -1,
parameter AXI_ID_WIDTH = -1,
parameter AXI_USER_WIDTH = -1
);
localparam AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8;
typedef logic [AXI_ID_WIDTH-1:0] id_t;
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_STRB_WIDTH-1:0] strb_t;
typedef logic [AXI_USER_WIDTH-1:0] user_t;
id_t aw_id;
addr_t aw_addr;
logic [7:0] aw_len;
logic [2:0] aw_size;
burst_t aw_burst;
logic aw_lock;
cache_t aw_cache;
prot_t aw_prot;
qos_t aw_qos;
region_t aw_region;
logic [5:0] aw_atop;
user_t aw_user;
logic aw_valid;
logic aw_ready;
data_t w_data;
strb_t w_strb;
logic w_last;
user_t w_user;
logic w_valid;
logic w_ready;
id_t b_id;
resp_t b_resp;
user_t b_user;
logic b_valid;
logic b_ready;
id_t ar_id;
addr_t ar_addr;
logic [7:0] ar_len;
logic [2:0] ar_size;
burst_t ar_burst;
logic ar_lock;
cache_t ar_cache;
prot_t ar_prot;
qos_t ar_qos;
region_t ar_region;
user_t ar_user;
logic ar_valid;
logic ar_ready;
id_t r_id;
data_t r_data;
resp_t r_resp;
logic r_last;
user_t r_user;
logic r_valid;
logic r_ready;
modport Master (
output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_valid, input aw_ready,
output w_data, w_strb, w_last, w_user, w_valid, input w_ready,
input b_id, b_resp, b_user, b_valid, output b_ready,
output ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, input ar_ready,
input r_id, r_data, r_resp, r_last, r_user, r_valid, output r_ready
);
modport Slave (
input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_valid, output aw_ready,
input w_data, w_strb, w_last, w_user, w_valid, output w_ready,
output b_id, b_resp, b_user, b_valid, input b_ready,
input ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, output ar_ready,
output r_id, r_data, r_resp, r_last, r_user, r_valid, input r_ready
);
endinterface
/// A clocked AXI4 interface for use in design verification.
interface AXI_BUS_DV #(
parameter AXI_ADDR_WIDTH = -1,
parameter AXI_DATA_WIDTH = -1,
parameter AXI_ID_WIDTH = -1,
parameter AXI_USER_WIDTH = -1
)(
input logic clk_i
);
localparam AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8;
typedef logic [AXI_ID_WIDTH-1:0] id_t;
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_STRB_WIDTH-1:0] strb_t;
typedef logic [AXI_USER_WIDTH-1:0] user_t;
id_t aw_id;
addr_t aw_addr;
logic [7:0] aw_len;
logic [2:0] aw_size;
burst_t aw_burst;
logic aw_lock;
cache_t aw_cache;
prot_t aw_prot;
qos_t aw_qos;
region_t aw_region;
logic [5:0] aw_atop;
user_t aw_user;
logic aw_valid;
logic aw_ready;
data_t w_data;
strb_t w_strb;
logic w_last;
user_t w_user;
logic w_valid;
logic w_ready;
id_t b_id;
resp_t b_resp;
user_t b_user;
logic b_valid;
logic b_ready;
id_t ar_id;
addr_t ar_addr;
logic [7:0] ar_len;
logic [2:0] ar_size;
burst_t ar_burst;
logic ar_lock;
cache_t ar_cache;
prot_t ar_prot;
qos_t ar_qos;
region_t ar_region;
user_t ar_user;
logic ar_valid;
logic ar_ready;
id_t r_id;
data_t r_data;
resp_t r_resp;
logic r_last;
user_t r_user;
logic r_valid;
logic r_ready;
modport Master (
output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_valid, input aw_ready,
output w_data, w_strb, w_last, w_user, w_valid, input w_ready,
input b_id, b_resp, b_user, b_valid, output b_ready,
output ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, input ar_ready,
input r_id, r_data, r_resp, r_last, r_user, r_valid, output r_ready
);
modport Slave (
input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_valid, output aw_ready,
input w_data, w_strb, w_last, w_user, w_valid, output w_ready,
output b_id, b_resp, b_user, b_valid, input b_ready,
input ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, output ar_ready,
output r_id, r_data, r_resp, r_last, r_user, r_valid, input r_ready
);
endinterface
/// An asynchronous AXI4 interface.
interface AXI_BUS_ASYNC
#(
parameter AXI_ADDR_WIDTH = -1,
parameter AXI_DATA_WIDTH = -1,
parameter AXI_ID_WIDTH = -1,
parameter AXI_USER_WIDTH = -1,
parameter BUFFER_WIDTH = -1
);
localparam AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8;
logic [AXI_ID_WIDTH-1:0] aw_id;
logic [AXI_ADDR_WIDTH-1:0] aw_addr;
logic [7:0] aw_len;
logic [2:0] aw_size;
logic [1:0] aw_burst;
logic aw_lock;
logic [3:0] aw_cache;
logic [2:0] aw_prot;
logic [3:0] aw_qos;
logic [3:0] aw_region;
logic [5:0] aw_atop;
logic [AXI_USER_WIDTH-1:0] aw_user;
logic [BUFFER_WIDTH-1:0] aw_writetoken;
logic [BUFFER_WIDTH-1:0] aw_readpointer;
logic [AXI_DATA_WIDTH-1:0] w_data;
logic [AXI_STRB_WIDTH-1:0] w_strb;
logic w_last;
logic [AXI_USER_WIDTH-1:0] w_user;
logic [BUFFER_WIDTH-1:0] w_writetoken;
logic [BUFFER_WIDTH-1:0] w_readpointer;
logic [AXI_ID_WIDTH-1:0] b_id;
logic [1:0] b_resp;
logic [AXI_USER_WIDTH-1:0] b_user;
logic [BUFFER_WIDTH-1:0] b_writetoken;
logic [BUFFER_WIDTH-1:0] b_readpointer;
logic [AXI_ID_WIDTH-1:0] ar_id;
logic [AXI_ADDR_WIDTH-1:0] ar_addr;
logic [7:0] ar_len;
logic [2:0] ar_size;
logic [1:0] ar_burst;
logic ar_lock;
logic [3:0] ar_cache;
logic [2:0] ar_prot;
logic [3:0] ar_qos;
logic [3:0] ar_region;
logic [AXI_USER_WIDTH-1:0] ar_user;
logic [BUFFER_WIDTH-1:0] ar_writetoken;
logic [BUFFER_WIDTH-1:0] ar_readpointer;
logic [AXI_ID_WIDTH-1:0] r_id;
logic [AXI_DATA_WIDTH-1:0] r_data;
logic [1:0] r_resp;
logic r_last;
logic [AXI_USER_WIDTH-1:0] r_user;
logic [BUFFER_WIDTH-1:0] r_writetoken;
logic [BUFFER_WIDTH-1:0] r_readpointer;
modport Master (
output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_writetoken, input aw_readpointer,
output w_data, w_strb, w_last, w_user, w_writetoken, input w_readpointer,
input b_id, b_resp, b_user, b_writetoken, output b_readpointer,
output ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_writetoken, input ar_readpointer,
input r_id, r_data, r_resp, r_last, r_user, r_writetoken, output r_readpointer
);
modport Slave (
input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_writetoken, output aw_readpointer,
input w_data, w_strb, w_last, w_user, w_writetoken, output w_readpointer,
output b_id, b_resp, b_user, b_writetoken, input b_readpointer,
input ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_writetoken, output ar_readpointer,
output r_id, r_data, r_resp, r_last, r_user, r_writetoken, input r_readpointer
);
endinterface
/// An AXI4-Lite interface.
interface AXI_LITE #(
parameter AXI_ADDR_WIDTH = -1,
parameter AXI_DATA_WIDTH = -1
);
localparam AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8;
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_STRB_WIDTH-1:0] strb_t;
// AW channel
addr_t aw_addr;
logic aw_valid;
logic aw_ready;
data_t w_data;
strb_t w_strb;
logic w_valid;
logic w_ready;
resp_t b_resp;
logic b_valid;
logic b_ready;
addr_t ar_addr;
logic ar_valid;
logic ar_ready;
data_t r_data;
resp_t r_resp;
logic r_valid;
logic r_ready;
modport Master (
output aw_addr, aw_valid, input aw_ready,
output w_data, w_strb, w_valid, input w_ready,
input b_resp, b_valid, output b_ready,
output ar_addr, ar_valid, input ar_ready,
input r_data, r_resp, r_valid, output r_ready
);
modport Slave (
input aw_addr, aw_valid, output aw_ready,
input w_data, w_strb, w_valid, output w_ready,
output b_resp, b_valid, input b_ready,
input ar_addr, ar_valid, output ar_ready,
output r_data, r_resp, r_valid, input r_ready
);
endinterface
/// A clocked AXI4-Lite interface for use in design verification.
interface AXI_LITE_DV #(
parameter AXI_ADDR_WIDTH = -1,
parameter AXI_DATA_WIDTH = -1
)(
input logic clk_i
);
localparam AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8;
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_STRB_WIDTH-1:0] strb_t;
// AW channel
addr_t aw_addr;
logic aw_valid;
logic aw_ready;
data_t w_data;
strb_t w_strb;
logic w_valid;
logic w_ready;
resp_t b_resp;
logic b_valid;
logic b_ready;
addr_t ar_addr;
logic ar_valid;
logic ar_ready;
data_t r_data;
resp_t r_resp;
logic r_valid;
logic r_ready;
modport Master (
output aw_addr, aw_valid, input aw_ready,
output w_data, w_strb, w_valid, input w_ready,
input b_resp, b_valid, output b_ready,
output ar_addr, ar_valid, input ar_ready,
input r_data, r_resp, r_valid, output r_ready
);
modport Slave (
input aw_addr, aw_valid, output aw_ready,
input w_data, w_strb, w_valid, output w_ready,
output b_resp, b_valid, input b_ready,
input ar_addr, ar_valid, output ar_ready,
output r_data, r_resp, r_valid, input r_ready
);
endinterface
/// An AXI routing table.
///
/// For each slave, multiple rules can be defined. Each rule consists of an
/// address mask and a base. Addresses are masked and then compared against the
/// base to decide where transfers need to go.
interface AXI_ROUTING_RULES #(
/// The address width.
parameter int AXI_ADDR_WIDTH = 1,
/// The number of slaves in the routing table.
parameter int NUM_SLAVE = 1,
/// The number of rules in the routing table.
parameter int NUM_RULES = 1
);
struct packed {
logic enabled;
logic [AXI_ADDR_WIDTH-1:0] mask;
logic [AXI_ADDR_WIDTH-1:0] base;
} [NUM_RULES-1:0] rules [NUM_SLAVE];
modport xbar(input rules);
modport cfg(output rules);
endinterface
/// An AXI arbitration interface.
interface AXI_ARBITRATION #(
/// The number of requestors.
parameter int NUM_REQ = -1
);
// Incoming requests.
logic [NUM_REQ-1:0] in_req;
logic [NUM_REQ-1:0] in_ack;
// Outgoing request.
logic out_req;
logic out_ack;
logic [$clog2(NUM_REQ)-1:0] out_sel;
// The arbiter side of the interface.
modport arb(input in_req, out_ack, output out_req, out_sel, in_ack);
// The requestor side of the interface.
modport req(output in_req, out_ack, input out_req, out_sel, in_ack);
endinterface
|
// Copyright (c) 2014-2018 ETH Zurich, University of Bologna
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Fabian Schuiki <[email protected]>
/// A connector that joins two AXI interfaces.
module axi_join (
AXI_BUS.Slave in,
AXI_BUS.Master out
);
`ifndef SYNTHESIS
initial begin
assert(in.AXI_ADDR_WIDTH == out.AXI_ADDR_WIDTH);
assert(in.AXI_DATA_WIDTH == out.AXI_DATA_WIDTH);
assert(in.AXI_ID_WIDTH <= out.AXI_ID_WIDTH );
assert(in.AXI_USER_WIDTH == out.AXI_USER_WIDTH);
end
`endif
assign out.aw_id = in.aw_id;
assign out.aw_addr = in.aw_addr;
assign out.aw_len = in.aw_len;
assign out.aw_size = in.aw_size;
assign out.aw_burst = in.aw_burst;
assign out.aw_lock = in.aw_lock;
assign out.aw_cache = in.aw_cache;
assign out.aw_prot = in.aw_prot;
assign out.aw_qos = in.aw_qos;
assign out.aw_region = in.aw_region;
assign out.aw_atop = in.aw_atop;
assign out.aw_user = in.aw_user;
assign out.aw_valid = in.aw_valid;
assign out.w_data = in.w_data;
assign out.w_strb = in.w_strb;
assign out.w_last = in.w_last;
assign out.w_user = in.w_user;
assign out.w_valid = in.w_valid;
assign out.b_ready = in.b_ready;
assign out.ar_id = in.ar_id;
assign out.ar_addr = in.ar_addr;
assign out.ar_len = in.ar_len;
assign out.ar_size = in.ar_size;
assign out.ar_burst = in.ar_burst;
assign out.ar_lock = in.ar_lock;
assign out.ar_cache = in.ar_cache;
assign out.ar_prot = in.ar_prot;
assign out.ar_qos = in.ar_qos;
assign out.ar_region = in.ar_region;
assign out.ar_user = in.ar_user;
assign out.ar_valid = in.ar_valid;
assign out.r_ready = in.r_ready;
assign in.aw_ready = out.aw_ready;
assign in.w_ready = out.w_ready;
assign in.b_id = out.b_id;
assign in.b_resp = out.b_resp;
assign in.b_user = out.b_user;
assign in.b_valid = out.b_valid;
assign in.ar_ready = out.ar_ready;
assign in.r_id = out.r_id;
assign in.r_data = out.r_data;
assign in.r_resp = out.r_resp;
assign in.r_last = out.r_last;
assign in.r_user = out.r_user;
assign in.r_valid = out.r_valid;
endmodule
|
// Copyright (c) 2014-2018 ETH Zurich, University of Bologna
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Fabian Schuiki <[email protected]>
/// A connector that joins two AXI-Lite interfaces.
module axi_lite_join (
AXI_LITE.Slave in,
AXI_LITE.Master out
);
`ifndef SYNTHESIS
initial begin
assert(in.AXI_ADDR_WIDTH == out.AXI_ADDR_WIDTH);
assert(in.AXI_DATA_WIDTH == out.AXI_DATA_WIDTH);
end
`endif
assign out.aw_addr = in.aw_addr;
assign out.aw_valid = in.aw_valid;
assign out.w_data = in.w_data;
assign out.w_strb = in.w_strb;
assign out.w_valid = in.w_valid;
assign out.b_ready = in.b_ready;
assign out.ar_addr = in.ar_addr;
assign out.ar_valid = in.ar_valid;
assign out.r_ready = in.r_ready;
assign in.aw_ready = out.aw_ready;
assign in.w_ready = out.w_ready;
assign in.b_resp = out.b_resp;
assign in.b_valid = out.b_valid;
assign in.ar_ready = out.ar_ready;
assign in.r_data = out.r_data;
assign in.r_resp = out.r_resp;
assign in.r_valid = out.r_valid;
endmodule
|
// Copyright (c) 2014-2018 ETH Zurich, University of Bologna
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Fabian Schuiki <[email protected]>
/// An AXI4-Lite to AXI4 adapter.
module axi_lite_to_axi (
AXI_LITE.Slave in,
AXI_BUS.Master out
);
`ifndef SYNTHESIS
initial begin
assert(in.AXI_ADDR_WIDTH == out.AXI_ADDR_WIDTH);
assert(in.AXI_DATA_WIDTH == out.AXI_DATA_WIDTH);
end
`endif
assign out.aw_id = '0;
assign out.aw_addr = in.aw_addr;
assign out.aw_len = '0;
assign out.aw_size = $unsigned($clog2($bits(out.w_data)/8));
assign out.aw_burst = axi_pkg::BURST_FIXED;
assign out.aw_lock = '0;
assign out.aw_cache = '0; // non-modifiable and non-bufferable mandated by std
assign out.aw_prot = '0;
assign out.aw_qos = '0;
assign out.aw_region = '0;
assign out.aw_atop = '0;
assign out.aw_user = '0;
assign out.aw_valid = in.aw_valid;
assign in.aw_ready = out.aw_ready;
assign out.w_data = in.w_data;
assign out.w_strb = in.w_strb;
assign out.w_last = '1;
assign out.w_user = '0;
assign out.w_valid = in.w_valid;
assign in.w_ready = out.w_ready;
assign in.b_resp = out.b_resp;
assign in.b_valid = out.b_valid;
assign out.b_ready = in.b_ready;
assign out.ar_id = '0;
assign out.ar_addr = in.ar_addr;
assign out.ar_len = '0;
assign out.ar_size = $unsigned($clog2($bits(out.r_data)/8));
assign out.ar_burst = axi_pkg::BURST_FIXED;
assign out.ar_lock = '0;
assign out.ar_cache = '0; // non-modifiable and non-bufferable mandated by std
assign out.ar_prot = '0;
assign out.ar_qos = '0;
assign out.ar_region = '0;
assign out.ar_user = '0;
assign out.ar_valid = in.ar_valid;
assign in.ar_ready = out.ar_ready;
assign in.r_data = out.r_data;
assign in.r_resp = out.r_resp;
assign in.r_valid = out.r_valid;
assign out.r_ready = in.r_ready;
endmodule
|
// Copyright (c) 2014-2018 ETH Zurich, University of Bologna
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Fabian Schuiki <[email protected]>
///`include "axi_bus.sv"
import axi_pkg::*;
/// An AXI4-Lite crossbar.
module axi_lite_xbar #(
/// The address width.
parameter int ADDR_WIDTH = -1,
/// The data width.
parameter int DATA_WIDTH = -1,
/// The number of master ports.
parameter int NUM_MASTER = 1,
/// The number of slave ports.
parameter int NUM_SLAVE = 1,
/// The number of routing rules.
parameter int NUM_RULES = -1
)(
input logic clk_i ,
input logic rst_ni ,
//AXI_LITE.in master [1:0] ,
//AXI_LITE.out slave [11:0] ,
AXI_LITE.Slave master [NUM_MASTER] ,
AXI_LITE.Master slave [NUM_SLAVE] ,
AXI_ROUTING_RULES.xbar rules
);
// The arbitration bus.
AXI_ARBITRATION #(.NUM_REQ(NUM_MASTER)) s_arb_rd(), s_arb_wr();
// For now just instantiate the simple crossbar. We may want to add different
// implementations later.
axi_lite_xbar_simple #(
.ADDR_WIDTH ( ADDR_WIDTH ),
.DATA_WIDTH ( DATA_WIDTH ),
.NUM_MASTER ( NUM_MASTER ),
.NUM_SLAVE ( NUM_SLAVE ),
.NUM_RULES ( NUM_RULES )
) i_simple (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.master ( master ),
.slave ( slave ),
.rules ( rules ),
.arb_rd ( s_arb_rd.req ),
.arb_wr ( s_arb_wr.req )
);
// Instantiate round-robin arbiters for the read and write channels.
axi_arbiter #(
.NUM_REQ ( NUM_MASTER )
) i_arb_rd (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.arb ( s_arb_rd.arb )
);
axi_arbiter #(
.NUM_REQ ( NUM_MASTER )
) i_arb_wr (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.arb ( s_arb_wr.arb )
);
endmodule
/// A simple implementation of an AXI4-Lite crossbar. Can only serve one master
/// at a time.
module axi_lite_xbar_simple #(
/// The address width.
parameter int ADDR_WIDTH = -1,
/// The data width.
parameter int DATA_WIDTH = -1,
/// The number of master ports.
parameter int NUM_MASTER = 1,
/// The number of slave ports.
parameter int NUM_SLAVE = 1,
/// The number of routing rules.
parameter int NUM_RULES = -1
)(
input logic clk_i ,
input logic rst_ni ,
//AXI_LITE.in master [NUM_MASTER] ,
//AXI_LITE.out slave [NUM_SLAVE] ,
AXI_LITE.Slave master [NUM_MASTER] ,
AXI_LITE.Master slave [NUM_SLAVE] ,
AXI_ROUTING_RULES.xbar rules ,
AXI_ARBITRATION.req arb_rd ,
AXI_ARBITRATION.req arb_wr
);
`ifndef SYNTHESIS
initial begin
assert(NUM_MASTER > 0);
assert(NUM_SLAVE > 0);
assert(NUM_RULES > 0);
assert(rules.AXI_ADDR_WIDTH == ADDR_WIDTH);
assert(rules.NUM_SLAVE == NUM_SLAVE);
end
// Check master address widths are all equal.
for (genvar i = 0; i < NUM_MASTER; i++) begin : g_chk_master
initial begin
assert(master[i].AXI_ADDR_WIDTH == ADDR_WIDTH);
assert(master[i].AXI_DATA_WIDTH == DATA_WIDTH);
end
end
// Check slave address widths are all equal.
for (genvar i = 0; i < NUM_SLAVE; i++) begin
initial begin
assert(slave[i].AXI_ADDR_WIDTH == ADDR_WIDTH);
assert(slave[i].AXI_DATA_WIDTH == DATA_WIDTH);
end
end
`endif
typedef logic [ADDR_WIDTH-1:0] addr_t;
typedef logic [DATA_WIDTH-1:0] data_t;
typedef logic [DATA_WIDTH/8-1:0] strb_t;
typedef logic [$clog2(NUM_MASTER)-1:0] master_id_t;
typedef logic [$clog2(NUM_SLAVE)-1:0] slave_id_t;
// The tag specifies which master is currently being served, and what slave it
// is targeting. There are independent tags for read and write.
struct packed {
master_id_t master;
slave_id_t slave;
} tag_rd_d, tag_wr_d, tag_rd_q, tag_wr_q;
enum { RD_IDLE, RD_REQ, RD_RESP, RD_ERR_RESP } state_rd_d, state_rd_q;
enum { WR_IDLE, WR_REQ, WR_DATA, WR_RESP, WR_ERR_DATA, WR_ERR_RESP } state_wr_d, state_wr_q;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (~rst_ni) begin
state_rd_q <= RD_IDLE;
state_wr_q <= WR_IDLE;
tag_rd_q <= '0;
tag_wr_q <= '0;
end else begin
state_rd_q <= state_rd_d;
state_wr_q <= state_wr_d;
tag_rd_q <= tag_rd_d;
tag_wr_q <= tag_wr_d;
end
end
// Generate the master-side multiplexer. This allows one of the masters to be
// contacted by setting the master_sel_{rd,wr} signal.
master_id_t master_sel_rd, master_sel_wr;
addr_t [NUM_MASTER-1:0] master_araddr_pack;
logic [NUM_MASTER-1:0] master_rready_pack;
addr_t [NUM_MASTER-1:0] master_awaddr_pack;
data_t [NUM_MASTER-1:0] master_wdata_pack;
strb_t [NUM_MASTER-1:0] master_wstrb_pack;
logic [NUM_MASTER-1:0] master_wvalid_pack;
logic [NUM_MASTER-1:0] master_bready_pack;
addr_t master_araddr;
logic master_arready;
data_t master_rdata;
resp_t master_rresp;
logic master_rvalid;
logic master_rready;
addr_t master_awaddr;
logic master_awready;
data_t master_wdata;
strb_t master_wstrb;
logic master_wvalid;
logic master_wready;
resp_t master_bresp;
logic master_bvalid;
logic master_bready;
for (genvar i = 0; i < NUM_MASTER; i++) begin
assign master_araddr_pack[i] = master[i].ar_addr;
assign master[i].ar_ready = master_arready && (i == master_sel_rd);
assign master[i].r_data = master_rdata;
assign master[i].r_resp = master_rresp;
assign master[i].r_valid = master_rvalid && (i == master_sel_rd);
assign master_rready_pack[i] = master[i].r_ready;
assign master_awaddr_pack[i] = master[i].aw_addr;
assign master[i].aw_ready = master_awready && (i == master_sel_wr);
assign master_wdata_pack[i] = master[i].w_data;
assign master_wstrb_pack[i] = master[i].w_strb;
assign master_wvalid_pack[i] = master[i].w_valid;
assign master[i].w_ready = master_wready && (i == master_sel_wr);
assign master[i].b_resp = master_bresp;
assign master_bready_pack[i] = master[i].b_ready;
assign master[i].b_valid = master_bvalid && (i == master_sel_wr);
end
assign master_araddr = master_araddr_pack [master_sel_rd];
assign master_rready = master_rready_pack [master_sel_rd];
assign master_awaddr = master_awaddr_pack [master_sel_wr];
assign master_wdata = master_wdata_pack [master_sel_wr];
assign master_wstrb = master_wstrb_pack [master_sel_wr];
assign master_wvalid = master_wvalid_pack [master_sel_wr];
assign master_bready = master_bready_pack [master_sel_wr];
// Generate the slave-side multiplexer. This allows one of the slaves to be
// contacted by setting the slave_sel_{rd,wr} signal.
slave_id_t slave_sel_rd, slave_sel_wr;
logic [NUM_SLAVE-1:0] slave_arready_pack;
data_t [NUM_SLAVE-1:0] slave_rdata_pack;
resp_t [NUM_SLAVE-1:0] slave_rresp_pack;
logic [NUM_SLAVE-1:0] slave_rvalid_pack;
logic [NUM_SLAVE-1:0] slave_awready_pack;
logic [NUM_SLAVE-1:0] slave_wready_pack;
resp_t [NUM_SLAVE-1:0] slave_bresp_pack;
logic [NUM_SLAVE-1:0] slave_bvalid_pack;
addr_t slave_araddr;
logic slave_arvalid;
logic slave_arready;
data_t slave_rdata;
resp_t slave_rresp;
logic slave_rvalid;
logic slave_rready;
addr_t slave_awaddr;
logic slave_awvalid;
logic slave_awready;
data_t slave_wdata;
strb_t slave_wstrb;
logic slave_wvalid;
logic slave_wready;
resp_t slave_bresp;
logic slave_bvalid;
logic slave_bready;
for (genvar i = 0; i < NUM_SLAVE; i++) begin
assign slave[i].ar_addr = slave_araddr;
assign slave[i].ar_valid = slave_arvalid && (i == slave_sel_rd);
assign slave_arready_pack[i] = slave[i].ar_ready;
assign slave_rdata_pack[i] = slave[i].r_data;
assign slave_rresp_pack[i] = slave[i].r_resp;
assign slave_rvalid_pack[i] = slave[i].r_valid;
assign slave[i].r_ready = slave_rready && (i == slave_sel_rd);
assign slave[i].aw_addr = slave_awaddr;
assign slave[i].aw_valid = slave_awvalid && (i == slave_sel_wr);
assign slave_awready_pack[i] = slave[i].aw_ready;
assign slave[i].w_data = slave_wdata;
assign slave[i].w_strb = slave_wstrb;
assign slave[i].w_valid = slave_wvalid && (i == slave_sel_wr);
assign slave_wready_pack[i] = slave[i].w_ready;
assign slave_bresp_pack[i] = slave[i].b_resp;
assign slave_bvalid_pack[i] = slave[i].b_valid;
assign slave[i].b_ready = slave_bready && (i == slave_sel_wr);
end
assign slave_arready = slave_arready_pack [slave_sel_rd];
assign slave_rdata = slave_rdata_pack [slave_sel_rd];
assign slave_rresp = slave_rresp_pack [slave_sel_rd];
assign slave_rvalid = slave_rvalid_pack [slave_sel_rd];
assign slave_awready = slave_awready_pack [slave_sel_wr];
assign slave_wready = slave_wready_pack [slave_sel_wr];
assign slave_bresp = slave_bresp_pack [slave_sel_wr];
assign slave_bvalid = slave_bvalid_pack [slave_sel_wr];
// Route the valid signals of the masters to the arbiters. They will decide
// which request will be granted.
for (genvar i = 0; i < NUM_MASTER; i++) begin
assign arb_rd.in_req[i] = master[i].ar_valid;
assign arb_wr.in_req[i] = master[i].aw_valid;
end
// Perform address resolution.
addr_t rd_resolve_addr, wr_resolve_addr;
logic [$clog2(NUM_SLAVE)-1:0] rd_match_idx, wr_match_idx;
logic rd_match_ok, wr_match_ok;
axi_address_resolver #(
.ADDR_WIDTH( ADDR_WIDTH ),
.NUM_SLAVE ( NUM_SLAVE ),
.NUM_RULES ( NUM_RULES )
) i_rd_resolver (
.rules ( rules ),
.addr_i ( rd_resolve_addr ),
.match_idx_o ( rd_match_idx ),
.match_ok_o ( rd_match_ok )
);
axi_address_resolver #(
.ADDR_WIDTH( ADDR_WIDTH ),
.NUM_SLAVE ( NUM_SLAVE ),
.NUM_RULES ( NUM_RULES )
) i_wr_resolver (
.rules ( rules ),
.addr_i ( wr_resolve_addr ),
.match_idx_o ( wr_match_idx ),
.match_ok_o ( wr_match_ok )
);
// Read state machine.
always_comb begin
state_rd_d = state_rd_q;
tag_rd_d = tag_rd_q;
arb_rd.out_ack = 0;
master_sel_rd = tag_rd_q.master;
slave_sel_rd = tag_rd_q.slave;
rd_resolve_addr = master_araddr;
slave_araddr = master_araddr;
slave_arvalid = 0;
master_arready = 0;
master_rdata = slave_rdata;
master_rresp = slave_rresp;
master_rvalid = 0;
slave_rready = 0;
case (state_rd_q)
RD_IDLE: begin
master_sel_rd = arb_rd.out_sel;
if (arb_rd.out_req) begin
arb_rd.out_ack = 1;
tag_rd_d.master = arb_rd.out_sel;
state_rd_d = RD_REQ;
end
end
RD_REQ: begin
slave_sel_rd = rd_match_idx;
tag_rd_d.slave = rd_match_idx;
// If the address resolution was successful, propagate the request and
// wait for a response. Otherwise immediately return an error.
if (rd_match_ok) begin
slave_arvalid = 1;
if (slave_arready) begin
state_rd_d = RD_RESP;
master_arready = 1;
end
end else begin
state_rd_d = RD_ERR_RESP;
master_arready = 1;
end
end
RD_RESP: begin
master_rvalid = slave_rvalid;
slave_rready = master_rready;
if (slave_rvalid && master_rready) begin
state_rd_d = RD_IDLE;
end
end
// Address resolution failed. Return an error response.
RD_ERR_RESP: begin
master_rresp = axi_pkg::RESP_DECERR;
master_rvalid = 1;
if (master_rready) begin
state_rd_d = RD_IDLE;
end
end
default: state_rd_d = RD_IDLE;
endcase
end
// Write state machine.
always_comb begin
state_wr_d = state_wr_q;
tag_wr_d = tag_wr_q;
arb_wr.out_ack = 0;
master_sel_wr = tag_wr_q.master;
slave_sel_wr = tag_wr_q.slave;
wr_resolve_addr = master_awaddr;
slave_awaddr = master_awaddr;
slave_awvalid = 0;
master_awready = 0;
slave_wdata = master_wdata;
slave_wstrb = master_wstrb;
slave_wvalid = 0;
master_wready = 0;
master_bresp = slave_bresp;
master_bvalid = 0;
slave_bready = 0;
case (state_wr_q)
WR_IDLE: begin
master_sel_wr = arb_wr.out_sel;
if (arb_wr.out_req) begin
arb_wr.out_ack = 1;
tag_wr_d.master = arb_wr.out_sel;
state_wr_d = WR_REQ;
end
end
WR_REQ: begin
slave_sel_wr = wr_match_idx;
tag_wr_d.slave = wr_match_idx;
// If the address resolution was successful, propagate the request and
// wait for a response. Otherwise immediately return an error.
if (wr_match_ok) begin
slave_awvalid = 1;
if (slave_awready) begin
state_wr_d = WR_DATA;
master_awready = 1;
end
end else begin
state_wr_d = WR_ERR_DATA;
master_awready = 1;
end
end
WR_DATA: begin
master_wready = slave_wready;
slave_wvalid = master_wvalid;
if (slave_wvalid && master_wready) begin
state_wr_d = WR_RESP;
end
end
WR_RESP: begin
master_bvalid = slave_bvalid;
slave_bready = master_bready;
if (slave_bvalid && master_bready) begin
state_wr_d = WR_IDLE;
end
end
// Address resolution failed. Discard the data transfer.
WR_ERR_DATA: begin
master_wready = 1;
if (master_wvalid) begin
state_wr_d = WR_ERR_RESP;
end
end
// Address resolution failed. Return an error response.
WR_ERR_RESP: begin
master_bresp = axi_pkg::RESP_DECERR;
master_bvalid = 1;
if (master_bready) begin
state_wr_d = WR_IDLE;
end
end
default: state_wr_d = WR_IDLE;
endcase
end
endmodule
|
// Copyright (c) 2014-2018 ETH Zurich, University of Bologna
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Fabian Schuiki <[email protected]>
/// A connector allows addresses of AXI requests to be changed.
module axi_modify_address #(
parameter int ADDR_WIDTH_IN = -1,
parameter int ADDR_WIDTH_OUT = ADDR_WIDTH_IN
)(
AXI_BUS.Slave in,
AXI_BUS.Master out,
output logic [ADDR_WIDTH_IN-1:0] aw_addr_in,
output logic [ADDR_WIDTH_IN-1:0] ar_addr_in,
input logic [ADDR_WIDTH_OUT-1:0] aw_addr_out,
input logic [ADDR_WIDTH_OUT-1:0] ar_addr_out
);
`ifndef SYNTHESIS
initial begin
assert(ADDR_WIDTH_IN > 0);
assert(ADDR_WIDTH_OUT > 0);
end
`endif
assign aw_addr_in = in.aw_addr;
assign ar_addr_in = in.ar_addr;
assign out.aw_id = in.aw_id;
assign out.aw_addr = aw_addr_out;
assign out.aw_len = in.aw_len;
assign out.aw_size = in.aw_size;
assign out.aw_burst = in.aw_burst;
assign out.aw_lock = in.aw_lock;
assign out.aw_cache = in.aw_cache;
assign out.aw_prot = in.aw_prot;
assign out.aw_qos = in.aw_qos;
assign out.aw_region = in.aw_region;
assign out.aw_atop = in.aw_atop;
assign out.aw_user = in.aw_user;
assign out.aw_valid = in.aw_valid;
assign out.w_data = in.w_data;
assign out.w_strb = in.w_strb;
assign out.w_last = in.w_last;
assign out.w_user = in.w_user;
assign out.w_valid = in.w_valid;
assign out.b_ready = in.b_ready;
assign out.ar_id = in.ar_id;
assign out.ar_addr = ar_addr_out;
assign out.ar_len = in.ar_len;
assign out.ar_size = in.ar_size;
assign out.ar_burst = in.ar_burst;
assign out.ar_lock = in.ar_lock;
assign out.ar_cache = in.ar_cache;
assign out.ar_prot = in.ar_prot;
assign out.ar_qos = in.ar_qos;
assign out.ar_region = in.ar_region;
assign out.ar_user = in.ar_user;
assign out.ar_valid = in.ar_valid;
assign out.r_ready = in.r_ready;
assign in.aw_ready = out.aw_ready;
assign in.w_ready = out.w_ready;
assign in.b_id = out.b_id;
assign in.b_resp = out.b_resp;
assign in.b_user = out.b_user;
assign in.b_valid = out.b_valid;
assign in.ar_ready = out.ar_ready;
assign in.r_id = out.r_id;
assign in.r_data = out.r_data;
assign in.r_resp = out.r_resp;
assign in.r_last = out.r_last;
assign in.r_user = out.r_user;
assign in.r_valid = out.r_valid;
endmodule
|
// Copyright (c) 2014-2018 ETH Zurich, University of Bologna
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Fabian Schuiki <[email protected]>
package axi_pkg;
typedef logic [1:0] burst_t;
typedef logic [1:0] resp_t;
typedef logic [3:0] cache_t;
typedef logic [2:0] prot_t;
typedef logic [3:0] qos_t;
typedef logic [3:0] region_t;
typedef logic [7:0] len_t;
typedef logic [2:0] size_t;
typedef logic [5:0] atop_t; // atomic operations
typedef logic [3:0] nsaid_t; // non-secure address identifier
localparam BURST_FIXED = 2'b00;
localparam BURST_INCR = 2'b01;
localparam BURST_WRAP = 2'b10;
localparam RESP_OKAY = 2'b00;
localparam RESP_EXOKAY = 2'b01;
localparam RESP_SLVERR = 2'b10;
localparam RESP_DECERR = 2'b11;
localparam CACHE_BUFFERABLE = 4'b0001;
localparam CACHE_MODIFIABLE = 4'b0010;
localparam CACHE_RD_ALLOC = 4'b0100;
localparam CACHE_WR_ALLOC = 4'b1000;
// ATOP[5:0]
localparam ATOP_ATOMICSWAP = 6'b110000;
localparam ATOP_ATOMICCMP = 6'b110001;
// ATOP[5:4]
localparam ATOP_NONE = 2'b00;
localparam ATOP_ATOMICSTORE = 2'b01;
localparam ATOP_ATOMICLOAD = 2'b10;
// ATOP[3]
localparam ATOP_LITTLE_END = 1'b0;
localparam ATOP_BIG_END = 1'b1;
// ATOP[2:0]
localparam ATOP_ADD = 3'b000;
localparam ATOP_CLR = 3'b001;
localparam ATOP_EOR = 3'b010;
localparam ATOP_SET = 3'b011;
localparam ATOP_SMAX = 3'b100;
localparam ATOP_SMIN = 3'b101;
localparam ATOP_UMAX = 3'b110;
localparam ATOP_UMIN = 3'b111;
// 4 is recommended by AXI standard, so lets stick to it, do not change
localparam IdWidth = 4;
localparam UserWidth = 1;
localparam AddrWidth = 64;
localparam DataWidth = 64;
localparam StrbWidth = DataWidth / 8;
typedef logic [IdWidth-1:0] id_t;
typedef logic [AddrWidth-1:0] addr_t;
typedef logic [DataWidth-1:0] data_t;
typedef logic [StrbWidth-1:0] strb_t;
typedef logic [UserWidth-1:0] user_t;
// AW Channel
typedef struct packed {
id_t id;
addr_t addr;
len_t len;
size_t size;
burst_t burst;
logic lock;
cache_t cache;
prot_t prot;
qos_t qos;
region_t region;
atop_t atop;
} aw_chan_t;
// W Channel
typedef struct packed {
data_t data;
strb_t strb;
logic last;
} w_chan_t;
// B Channel
typedef struct packed {
id_t id;
resp_t resp;
} b_chan_t;
// AR Channel
typedef struct packed {
id_t id;
addr_t addr;
len_t len;
size_t size;
burst_t burst;
logic lock;
cache_t cache;
prot_t prot;
qos_t qos;
region_t region;
} ar_chan_t;
// R Channel
typedef struct packed {
id_t id;
data_t data;
resp_t resp;
logic last;
} r_chan_t;
endpackage
|
// Copyright (c) 2014-2018 ETH Zurich, University of Bologna
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Fabian Schuiki <[email protected]>
//
// This file defines the interfaces we support.
import axi_pkg::*;
/// A set of testbench utilities for AXI interfaces.
package axi_test;
/// A driver for AXI4-Lite interface.
class axi_lite_driver #(
parameter int AW ,
parameter int DW ,
parameter time TA = 0ns , // stimuli application time
parameter time TT = 0ns // stimuli test time
);
virtual AXI_LITE_DV #(
.AXI_ADDR_WIDTH(AW),
.AXI_DATA_WIDTH(DW)
) axi;
function new(
virtual AXI_LITE_DV #(
.AXI_ADDR_WIDTH(AW),
.AXI_DATA_WIDTH(DW)
) axi
);
this.axi = axi;
endfunction
task reset_master;
axi.aw_addr <= '0;
axi.aw_valid <= '0;
axi.w_valid <= '0;
axi.w_data <= '0;
axi.w_strb <= '0;
axi.b_ready <= '0;
axi.ar_valid <= '0;
axi.ar_addr <= '0;
axi.r_ready <= '0;
endtask
task reset_slave;
axi.aw_ready <= '0;
axi.w_ready <= '0;
axi.b_resp <= '0;
axi.b_valid <= '0;
axi.ar_ready <= '0;
axi.r_data <= '0;
axi.r_resp <= '0;
axi.r_valid <= '0;
endtask
task cycle_start;
#TT;
endtask
task cycle_end;
@(posedge axi.clk_i);
endtask
/// Issue a beat on the AW channel.
task send_aw (
input logic [AW-1:0] addr
);
axi.aw_addr <= #TA addr;
axi.aw_valid <= #TA 1;
cycle_start();
while (axi.aw_ready != 1) begin cycle_end(); cycle_start(); end
cycle_end();
axi.aw_addr <= #TA '0;
axi.aw_valid <= #TA 0;
endtask
/// Issue a beat on the W channel.
task send_w (
input logic [DW-1:0] data,
input logic [DW/8-1:0] strb
);
axi.w_data <= #TA data;
axi.w_strb <= #TA strb;
axi.w_valid <= #TA 1;
cycle_start();
while (axi.w_ready != 1) begin cycle_end(); cycle_start(); end
cycle_end();
axi.w_data <= #TA '0;
axi.w_strb <= #TA '0;
axi.w_valid <= #TA 0;
endtask
/// Issue a beat on the B channel.
task send_b (
input axi_pkg::resp_t resp
);
axi.b_resp <= #TA resp;
axi.b_valid <= #TA 1;
cycle_start();
while (axi.b_ready != 1) begin cycle_end(); cycle_start(); end
cycle_end();
axi.b_resp <= #TA '0;
axi.b_valid <= #TA 0;
endtask
/// Issue a beat on the AR channel.
task send_ar (
input logic [AW-1:0] addr
);
axi.ar_addr <= #TA addr;
axi.ar_valid <= #TA 1;
cycle_start();
while (axi.ar_ready != 1) begin cycle_end(); cycle_start(); end
cycle_end();
axi.ar_addr <= #TA '0;
axi.ar_valid <= #TA 0;
endtask
/// Issue a beat on the R channel.
task send_r (
input logic [DW-1:0] data,
input axi_pkg::resp_t resp
);
axi.r_data <= #TA data;
axi.r_resp <= #TA resp;
axi.r_valid <= #TA 1;
cycle_start();
while (axi.r_ready != 1) begin cycle_end(); cycle_start(); end
cycle_end();
axi.r_data <= #TA '0;
axi.r_resp <= #TA '0;
axi.r_valid <= #TA 0;
endtask
/// Wait for a beat on the AW channel.
task recv_aw (
output [AW-1:0] addr
);
axi.aw_ready <= #TA 1;
cycle_start();
while (axi.aw_valid != 1) begin cycle_end(); cycle_start(); end
addr = axi.aw_addr;
cycle_end();
axi.aw_ready <= #TA 0;
endtask
/// Wait for a beat on the W channel.
task recv_w (
output [DW-1:0] data,
output [DW/8-1:0] strb
);
axi.w_ready <= #TA 1;
cycle_start();
while (axi.w_valid != 1) begin cycle_end(); cycle_start(); end
data = axi.w_data;
strb = axi.w_strb;
cycle_end();
axi.w_ready <= #TA 0;
endtask
/// Wait for a beat on the B channel.
task recv_b (
output axi_pkg::resp_t resp
);
axi.b_ready <= #TA 1;
cycle_start();
while (axi.b_valid != 1) begin cycle_end(); cycle_start(); end
resp = axi.b_resp;
cycle_end();
axi.b_ready <= #TA 0;
endtask
/// Wait for a beat on the AR channel.
task recv_ar (
output [AW-1:0] addr
);
axi.ar_ready <= #TA 1;
cycle_start();
while (axi.ar_valid != 1) begin cycle_end(); cycle_start(); end
addr = axi.ar_addr;
cycle_end();
axi.ar_ready <= #TA 0;
endtask
/// Wait for a beat on the R channel.
task recv_r (
output [DW-1:0] data,
output axi_pkg::resp_t resp
);
axi.r_ready <= #TA 1;
cycle_start();
while (axi.r_valid != 1) begin cycle_end(); cycle_start(); end
data = axi.r_data;
resp = axi.r_resp;
cycle_end();
axi.r_ready <= #TA 0;
endtask
endclass
/// The data transferred on a beat on the AW/AR channels.
class axi_ax_beat #(
parameter AW,
parameter IW,
parameter UW
);
rand logic [IW-1:0] ax_id = '0;
rand logic [AW-1:0] ax_addr = '0;
logic [7:0] ax_len = '0;
logic [2:0] ax_size = '0;
logic [1:0] ax_burst = '0;
logic ax_lock = '0;
logic [3:0] ax_cache = '0;
logic [2:0] ax_prot = '0;
logic [3:0] ax_qos = '0;
logic [3:0] ax_region = '0;
logic [5:0] ax_atop = '0; // Only defined on the AW channel.
rand logic [UW-1:0] ax_user = '0;
endclass
/// The data transferred on a beat on the W channel.
class axi_w_beat #(
parameter DW,
parameter UW
);
rand logic [DW-1:0] w_data = '0;
rand logic [DW/8-1:0] w_strb = '0;
logic w_last = '0;
rand logic [UW-1:0] w_user = '0;
endclass
/// The data transferred on a beat on the B channel.
class axi_b_beat #(
parameter IW,
parameter UW
);
rand logic [IW-1:0] b_id = '0;
axi_pkg::resp_t b_resp = '0;
rand logic [UW-1:0] b_user = '0;
endclass
/// The data transferred on a beat on the R channel.
class axi_r_beat #(
parameter DW,
parameter IW,
parameter UW
);
rand logic [IW-1:0] r_id = '0;
rand logic [DW-1:0] r_data = '0;
axi_pkg::resp_t r_resp = '0;
logic r_last = '0;
rand logic [UW-1:0] r_user = '0;
endclass
/// A driver for AXI4 interface.
class axi_driver #(
parameter int AW ,
parameter int DW ,
parameter int IW ,
parameter int UW ,
parameter time TA = 0ns , // stimuli application time
parameter time TT = 0ns // stimuli test time
);
virtual AXI_BUS_DV #(
.AXI_ADDR_WIDTH(AW),
.AXI_DATA_WIDTH(DW),
.AXI_ID_WIDTH(IW),
.AXI_USER_WIDTH(UW)
) axi;
typedef axi_ax_beat #(.AW(AW), .IW(IW), .UW(UW)) ax_beat_t;
typedef axi_w_beat #(.DW(DW), .UW(UW)) w_beat_t;
typedef axi_b_beat #(.IW(IW), .UW(UW)) b_beat_t;
typedef axi_r_beat #(.DW(DW), .IW(IW), .UW(UW)) r_beat_t;
function new(
virtual AXI_BUS_DV #(
.AXI_ADDR_WIDTH(AW),
.AXI_DATA_WIDTH(DW),
.AXI_ID_WIDTH(IW),
.AXI_USER_WIDTH(UW)
) axi
);
this.axi = axi;
endfunction
task reset_master;
axi.aw_id <= '0;
axi.aw_addr <= '0;
axi.aw_len <= '0;
axi.aw_size <= '0;
axi.aw_burst <= '0;
axi.aw_lock <= '0;
axi.aw_cache <= '0;
axi.aw_prot <= '0;
axi.aw_qos <= '0;
axi.aw_region <= '0;
axi.aw_atop <= '0;
axi.aw_user <= '0;
axi.aw_valid <= '0;
axi.w_data <= '0;
axi.w_strb <= '0;
axi.w_last <= '0;
axi.w_user <= '0;
axi.w_valid <= '0;
axi.b_ready <= '0;
axi.ar_id <= '0;
axi.ar_addr <= '0;
axi.ar_len <= '0;
axi.ar_size <= '0;
axi.ar_burst <= '0;
axi.ar_lock <= '0;
axi.ar_cache <= '0;
axi.ar_prot <= '0;
axi.ar_qos <= '0;
axi.ar_region <= '0;
axi.ar_user <= '0;
axi.ar_valid <= '0;
axi.r_ready <= '0;
endtask
task reset_slave;
axi.aw_ready <= '0;
axi.w_ready <= '0;
axi.b_id <= '0;
axi.b_resp <= '0;
axi.b_user <= '0;
axi.b_valid <= '0;
axi.ar_ready <= '0;
axi.r_id <= '0;
axi.r_data <= '0;
axi.r_resp <= '0;
axi.r_last <= '0;
axi.r_user <= '0;
axi.r_valid <= '0;
endtask
task cycle_start;
#TT;
endtask
task cycle_end;
@(posedge axi.clk_i);
endtask
/// Issue a beat on the AW channel.
task send_aw (
input ax_beat_t beat
);
axi.aw_id <= #TA beat.ax_id;
axi.aw_addr <= #TA beat.ax_addr;
axi.aw_len <= #TA beat.ax_len;
axi.aw_size <= #TA beat.ax_size;
axi.aw_burst <= #TA beat.ax_burst;
axi.aw_lock <= #TA beat.ax_lock;
axi.aw_cache <= #TA beat.ax_cache;
axi.aw_prot <= #TA beat.ax_prot;
axi.aw_qos <= #TA beat.ax_qos;
axi.aw_region <= #TA beat.ax_region;
axi.aw_atop <= #TA beat.ax_atop;
axi.aw_user <= #TA beat.ax_user;
axi.aw_valid <= #TA 1;
cycle_start();
while (axi.aw_ready != 1) begin cycle_end(); cycle_start(); end
cycle_end();
axi.aw_id <= #TA '0;
axi.aw_addr <= #TA '0;
axi.aw_len <= #TA '0;
axi.aw_size <= #TA '0;
axi.aw_burst <= #TA '0;
axi.aw_lock <= #TA '0;
axi.aw_cache <= #TA '0;
axi.aw_prot <= #TA '0;
axi.aw_qos <= #TA '0;
axi.aw_region <= #TA '0;
axi.aw_atop <= #TA '0;
axi.aw_user <= #TA '0;
axi.aw_valid <= #TA 0;
endtask
/// Issue a beat on the W channel.
task send_w (
input w_beat_t beat
);
axi.w_data <= #TA beat.w_data;
axi.w_strb <= #TA beat.w_strb;
axi.w_last <= #TA beat.w_last;
axi.w_user <= #TA beat.w_user;
axi.w_valid <= #TA 1;
cycle_start();
while (axi.w_ready != 1) begin cycle_end(); cycle_start(); end
cycle_end();
axi.w_data <= #TA '0;
axi.w_strb <= #TA '0;
axi.w_last <= #TA '0;
axi.w_user <= #TA '0;
axi.w_valid <= #TA 0;
endtask
/// Issue a beat on the B channel.
task send_b (
input b_beat_t beat
);
axi.b_id <= #TA beat.b_id;
axi.b_resp <= #TA beat.b_resp;
axi.b_user <= #TA beat.b_user;
axi.b_valid <= #TA 1;
cycle_start();
while (axi.b_ready != 1) begin cycle_end(); cycle_start(); end
cycle_end();
axi.b_id <= #TA '0;
axi.b_resp <= #TA '0;
axi.b_user <= #TA '0;
axi.b_valid <= #TA 0;
endtask
/// Issue a beat on the AR channel.
task send_ar (
input ax_beat_t beat
);
axi.ar_id <= #TA beat.ax_id;
axi.ar_addr <= #TA beat.ax_addr;
axi.ar_len <= #TA beat.ax_len;
axi.ar_size <= #TA beat.ax_size;
axi.ar_burst <= #TA beat.ax_burst;
axi.ar_lock <= #TA beat.ax_lock;
axi.ar_cache <= #TA beat.ax_cache;
axi.ar_prot <= #TA beat.ax_prot;
axi.ar_qos <= #TA beat.ax_qos;
axi.ar_region <= #TA beat.ax_region;
axi.ar_user <= #TA beat.ax_user;
axi.ar_valid <= #TA 1;
cycle_start();
while (axi.ar_ready != 1) begin cycle_end(); cycle_start(); end
cycle_end();
axi.ar_id <= #TA '0;
axi.ar_addr <= #TA '0;
axi.ar_len <= #TA '0;
axi.ar_size <= #TA '0;
axi.ar_burst <= #TA '0;
axi.ar_lock <= #TA '0;
axi.ar_cache <= #TA '0;
axi.ar_prot <= #TA '0;
axi.ar_qos <= #TA '0;
axi.ar_region <= #TA '0;
axi.ar_user <= #TA '0;
axi.ar_valid <= #TA 0;
endtask
/// Issue a beat on the R channel.
task send_r (
input r_beat_t beat
);
axi.r_id <= #TA beat.r_id;
axi.r_data <= #TA beat.r_data;
axi.r_resp <= #TA beat.r_resp;
axi.r_last <= #TA beat.r_last;
axi.r_user <= #TA beat.r_user;
axi.r_valid <= #TA 1;
cycle_start();
while (axi.r_ready != 1) begin cycle_end(); cycle_start(); end
cycle_end();
axi.r_id <= #TA '0;
axi.r_data <= #TA '0;
axi.r_resp <= #TA '0;
axi.r_last <= #TA '0;
axi.r_user <= #TA '0;
axi.r_valid <= #TA 0;
endtask
/// Wait for a beat on the AW channel.
task recv_aw (
output ax_beat_t beat
);
axi.aw_ready <= #TA 1;
cycle_start();
while (axi.aw_valid != 1) begin cycle_end(); cycle_start(); end
beat = new;
beat.ax_id = axi.aw_id;
beat.ax_addr = axi.aw_addr;
beat.ax_len = axi.aw_len;
beat.ax_size = axi.aw_size;
beat.ax_burst = axi.aw_burst;
beat.ax_lock = axi.aw_lock;
beat.ax_cache = axi.aw_cache;
beat.ax_prot = axi.aw_prot;
beat.ax_qos = axi.aw_qos;
beat.ax_region = axi.aw_region;
beat.ax_atop = axi.aw_atop;
beat.ax_user = axi.aw_user;
cycle_end();
axi.aw_ready <= #TA 0;
endtask
/// Wait for a beat on the W channel.
task recv_w (
output w_beat_t beat
);
axi.w_ready <= #TA 1;
cycle_start();
while (axi.w_valid != 1) begin cycle_end(); cycle_start(); end
beat = new;
beat.w_data = axi.w_data;
beat.w_strb = axi.w_strb;
beat.w_last = axi.w_last;
beat.w_user = axi.w_user;
cycle_end();
axi.w_ready <= #TA 0;
endtask
/// Wait for a beat on the B channel.
task recv_b (
output b_beat_t beat
);
axi.b_ready <= #TA 1;
cycle_start();
while (axi.b_valid != 1) begin cycle_end(); cycle_start(); end
beat = new;
beat.b_id = axi.b_id;
beat.b_resp = axi.b_resp;
beat.b_user = axi.b_user;
cycle_end();
axi.b_ready <= #TA 0;
endtask
/// Wait for a beat on the AR channel.
task recv_ar (
output ax_beat_t beat
);
axi.ar_ready <= #TA 1;
cycle_start();
while (axi.ar_valid != 1) begin cycle_end(); cycle_start(); end
beat = new;
beat.ax_id = axi.ar_id;
beat.ax_addr = axi.ar_addr;
beat.ax_len = axi.ar_len;
beat.ax_size = axi.ar_size;
beat.ax_burst = axi.ar_burst;
beat.ax_lock = axi.ar_lock;
beat.ax_cache = axi.ar_cache;
beat.ax_prot = axi.ar_prot;
beat.ax_qos = axi.ar_qos;
beat.ax_region = axi.ar_region;
beat.ax_atop = 'X; // Not defined on the AR channel.
beat.ax_user = axi.ar_user;
cycle_end();
axi.ar_ready <= #TA 0;
endtask
/// Wait for a beat on the R channel.
task recv_r (
output r_beat_t beat
);
axi.r_ready <= #TA 1;
cycle_start();
while (axi.r_valid != 1) begin cycle_end(); cycle_start(); end
beat = new;
beat.r_id = axi.r_id;
beat.r_data = axi.r_data;
beat.r_resp = axi.r_resp;
beat.r_last = axi.r_last;
beat.r_user = axi.r_user;
cycle_end();
axi.r_ready <= #TA 0;
endtask
endclass
endpackage
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